diff options
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/cpu/armv7/Makefile | 1 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/u8500/Makefile | 9 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/u8500/clock.c | 74 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/u8500/cpu.c | 176 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/u8500/lowlevel.S | 21 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/u8500/prcmu.c | 214 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/u8500/timer.c | 135 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-u8500/clock.h | 53 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-u8500/db8500_gpio.h | 42 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-u8500/db8500_pincfg.h | 170 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-u8500/gpio.h | 231 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-u8500/hardware.h | 94 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-u8500/prcmu.h | 64 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-u8500/sys_proto.h | 12 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-u8500/u8500.h | 31 |
15 files changed, 0 insertions, 1327 deletions
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index 79a38df2cb..c8d142220a 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -52,5 +52,4 @@ obj-$(CONFIG_RMOBILE) += rmobile/ obj-$(CONFIG_ARCH_S5PC1XX) += s5pc1xx/ obj-$(if $(filter stv0991,$(SOC)),y) += stv0991/ obj-$(CONFIG_ARCH_SUNXI) += sunxi/ -obj-$(CONFIG_U8500) += u8500/ obj-$(CONFIG_VF610) += vf610/ diff --git a/arch/arm/cpu/armv7/u8500/Makefile b/arch/arm/cpu/armv7/u8500/Makefile deleted file mode 100644 index fad9d4ae3a..0000000000 --- a/arch/arm/cpu/armv7/u8500/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := timer.o clock.o prcmu.o cpu.o -obj-y += lowlevel.o diff --git a/arch/arm/cpu/armv7/u8500/clock.c b/arch/arm/cpu/armv7/u8500/clock.c deleted file mode 100644 index 1e3b3d5205..0000000000 --- a/arch/arm/cpu/armv7/u8500/clock.c +++ /dev/null @@ -1,74 +0,0 @@ -/* - * (C) Copyright 2009 ST-Ericsson - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/hardware.h> - -DECLARE_GLOBAL_DATA_PTR; - -struct clkrst { - unsigned int pcken; - unsigned int pckdis; - unsigned int kcken; - unsigned int kckdis; -}; - -static unsigned int clkrst_base[] = { - U8500_CLKRST1_BASE, - U8500_CLKRST2_BASE, - U8500_CLKRST3_BASE, - 0, - U8500_CLKRST5_BASE, - U8500_CLKRST6_BASE, - U8500_CLKRST7_BASE, /* ED only */ -}; - -/* Turn on peripheral clock at PRCC level */ -void u8500_clock_enable(int periph, int cluster, int kern) -{ - struct clkrst *clkrst = (struct clkrst *) clkrst_base[periph - 1]; - - if (kern != -1) - writel(1 << kern, &clkrst->kcken); - - if (cluster != -1) - writel(1 << cluster, &clkrst->pcken); -} - -void db8500_clocks_init(void) -{ - /* - * Enable all clocks. This is u-boot, we can enable it all. There is no - * powersave in u-boot. - */ - - u8500_clock_enable(1, 9, -1); /* GPIO0 */ - u8500_clock_enable(2, 11, -1);/* GPIO1 */ - u8500_clock_enable(3, 8, -1); /* GPIO2 */ - u8500_clock_enable(5, 1, -1); /* GPIO3 */ - u8500_clock_enable(3, 6, 6); /* UART2 */ - u8500_clock_enable(3, 3, 3); /* I2C0 */ - u8500_clock_enable(1, 5, 5); /* SDI0 */ - u8500_clock_enable(2, 4, 2); /* SDI4 */ - u8500_clock_enable(6, 6, -1); /* MTU0 */ - u8500_clock_enable(3, 4, 4); /* SDI2 */ - - /* - * Enabling clocks for all devices which are AMBA devices in the - * kernel. Otherwise they will not get probe()'d because the - * peripheral ID register will not be powered. - */ - - /* XXX: some of these differ between ED/V1 */ - - u8500_clock_enable(1, 1, 1); /* UART1 */ - u8500_clock_enable(1, 0, 0); /* UART0 */ - u8500_clock_enable(3, 2, 2); /* SSP1 */ - u8500_clock_enable(3, 1, 1); /* SSP0 */ - u8500_clock_enable(2, 8, -1); /* SPI0 */ - u8500_clock_enable(2, 5, 3); /* MSP2 */ -} diff --git a/arch/arm/cpu/armv7/u8500/cpu.c b/arch/arm/cpu/armv7/u8500/cpu.c deleted file mode 100644 index d8634bebbd..0000000000 --- a/arch/arm/cpu/armv7/u8500/cpu.c +++ /dev/null @@ -1,176 +0,0 @@ -/* - * Copyright (C) 2012 Linaro Limited - * Mathieu Poirier <mathieu.poirier@linaro.org> - * - * Based on original code from Joakim Axelsson at ST-Ericsson - * (C) Copyright 2010 ST-Ericsson - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/prcmu.h> -#include <asm/arch/clock.h> -#include <asm/arch/hardware.h> - -#include <asm/arch/hardware.h> - -#define CPUID_DB8500V1 0x411fc091 -#define CPUID_DB8500V2 0x412fc091 -#define ASICID_DB8500V11 0x008500A1 - -#define CACHE_CONTR_BASE 0xA0412000 -/* Cache controller register offsets - * as found in ARM's technical reference manual - */ -#define CACHE_INVAL_BY_WAY (CACHE_CONTR_BASE + 0x77C) -#define CACHE_LOCKDOWN_BY_D (CACHE_CONTR_BASE + 0X900) -#define CACHE_LOCKDOWN_BY_I (CACHE_CONTR_BASE + 0X904) - -static unsigned int read_asicid(void); - -static inline unsigned int read_cpuid(void) -{ - unsigned int val; - - /* Main ID register (MIDR) */ - asm("mrc p15, 0, %0, c0, c0, 0" - : "=r" (val) - : - : "cc"); - - return val; -} - -static int cpu_is_u8500v11(void) -{ - return read_asicid() == ASICID_DB8500V11; -} - -static int cpu_is_u8500v2(void) -{ - return read_cpuid() == CPUID_DB8500V2; -} - -static unsigned int read_asicid(void) -{ - unsigned int *address; - - if (cpu_is_u8500v2()) - address = (void *) U8500_ASIC_ID_LOC_V2; - else - address = (void *) U8500_ASIC_ID_LOC_ED_V1; - - return readl(address); -} - -void cpu_cache_initialization(void) -{ - unsigned int value; - /* invalidate all cache entries */ - writel(0xFFFF, CACHE_INVAL_BY_WAY); - - /* ways are set to '0' when they are totally - * cleaned and invalidated - */ - do { - value = readl(CACHE_INVAL_BY_WAY); - } while (value & 0xFF); - - /* Invalidate register 9 D and I lockdown */ - writel(0xFF, CACHE_LOCKDOWN_BY_D); - writel(0xFF, CACHE_LOCKDOWN_BY_I); -} - -#ifdef CONFIG_ARCH_CPU_INIT -/* - * SOC specific cpu init - */ -int arch_cpu_init(void) -{ - db8500_prcmu_init(); - db8500_clocks_init(); - - return 0; -} -#endif /* CONFIG_ARCH_CPU_INIT */ - -#ifdef CONFIG_MMC - -int u8500_mmc_power_init(void) -{ - int ret; - int enable, voltage; - int ab8500_revision; - - if (!cpu_is_u8500v11() && !cpu_is_u8500v2()) - return 0; - - /* Get AB8500 revision */ - ret = ab8500_read(AB8500_MISC, AB8500_REV_REG); - if (ret < 0) - goto out; - - ab8500_revision = ret; - - /* - * On v1.1 HREF boards (HREF+), Vaux3 needs to be enabled for the SD - * card to work. This is done by enabling the regulators in the AB8500 - * via PRCMU I2C transactions. - * - * This code is derived from the handling of AB8500_LDO_VAUX3 in - * ab8500_ldo_enable() and ab8500_ldo_disable() in Linux. - * - * Turn off and delay is required to have it work across soft reboots. - */ - - /* Turn off (read-modify-write) */ - ret = ab8500_read(AB8500_REGU_CTRL2, - AB8500_REGU_VRF1VAUX3_REGU_REG); - if (ret < 0) - goto out; - - enable = ret; - - /* Turn off */ - ret = ab8500_write(AB8500_REGU_CTRL2, - AB8500_REGU_VRF1VAUX3_REGU_REG, - enable & ~LDO_VAUX3_ENABLE_MASK); - if (ret < 0) - goto out; - - udelay(10 * 1000); - - /* Set the voltage to 2.91 V or 2.9 V without overriding VRF1 value */ - ret = ab8500_read(AB8500_REGU_CTRL2, - AB8500_REGU_VRF1VAUX3_SEL_REG); - if (ret < 0) - goto out; - - voltage = ret; - - if (ab8500_revision < 0x20) { - voltage &= ~LDO_VAUX3_SEL_MASK; - voltage |= LDO_VAUX3_SEL_2V9; - } else { - voltage &= ~LDO_VAUX3_V2_SEL_MASK; - voltage |= LDO_VAUX3_V2_SEL_2V91; - } - - ret = ab8500_write(AB8500_REGU_CTRL2, - AB8500_REGU_VRF1VAUX3_SEL_REG, voltage); - if (ret < 0) - goto out; - - /* Turn on the supply */ - enable &= ~LDO_VAUX3_ENABLE_MASK; - enable |= LDO_VAUX3_ENABLE_VAL; - - ret = ab8500_write(AB8500_REGU_CTRL2, - AB8500_REGU_VRF1VAUX3_REGU_REG, enable); - -out: - return ret; -} -#endif /* CONFIG_MMC */ diff --git a/arch/arm/cpu/armv7/u8500/lowlevel.S b/arch/arm/cpu/armv7/u8500/lowlevel.S deleted file mode 100644 index d3e3920601..0000000000 --- a/arch/arm/cpu/armv7/u8500/lowlevel.S +++ /dev/null @@ -1,21 +0,0 @@ -/* - * (C) Copyright 2011 ST-Ericsson - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <config.h> -#include <linux/linkage.h> - -ENTRY(lowlevel_init) - mov pc, lr -ENDPROC(lowlevel_init) - - .align 5 -ENTRY(reset_cpu) - ldr r0, =CFG_PRCMU_BASE - ldr r1, =0x1 - str r1, [r0, #0x228] -_loop_forever: - b _loop_forever -ENDPROC(reset_cpu) diff --git a/arch/arm/cpu/armv7/u8500/prcmu.c b/arch/arm/cpu/armv7/u8500/prcmu.c deleted file mode 100644 index 26ffdc2e02..0000000000 --- a/arch/arm/cpu/armv7/u8500/prcmu.c +++ /dev/null @@ -1,214 +0,0 @@ -/* - * Copyright (C) 2009 ST-Ericsson SA - * - * Adapted from the Linux version: - * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * NOTE: This currently does not support the I2C workaround access method. - */ - -#include <common.h> -#include <config.h> -#include <asm/io.h> -#include <asm/arch/hardware.h> -#include <asm/types.h> -#include <asm/io.h> -#include <asm/errno.h> -#include <asm/arch/prcmu.h> - -/* CPU mailbox registers */ -#define PRCMU_I2C_WRITE(slave) \ - (((slave) << 1) | I2CWRITE | (1 << 6)) -#define PRCMU_I2C_READ(slave) \ - (((slave) << 1) | I2CREAD | (1 << 6)) - -#define I2C_MBOX_BIT (1 << 5) - -static int prcmu_is_ready(void) -{ - int ready = readb(PRCM_XP70_CUR_PWR_STATE) == AP_EXECUTE; - if (!ready) - printf("PRCMU firmware not ready\n"); - return ready; -} - -static int wait_for_i2c_mbx_rdy(void) -{ - int timeout = 10000; - - if (readl(PRCM_ARM_IT1_VAL) & I2C_MBOX_BIT) { - printf("prcmu: warning i2c mailbox was not acked\n"); - /* clear mailbox 5 ack irq */ - writel(I2C_MBOX_BIT, PRCM_ARM_IT1_CLEAR); - } - - /* check any already on-going transaction */ - while ((readl(PRCM_MBOX_CPU_VAL) & I2C_MBOX_BIT) && timeout) - timeout--; - - if (timeout == 0) - return -1; - - return 0; -} - -static int wait_for_i2c_req_done(void) -{ - int timeout = 10000; - - /* Set an interrupt to XP70 */ - writel(I2C_MBOX_BIT, PRCM_MBOX_CPU_SET); - - /* wait for mailbox 5 (i2c) ack */ - while (!(readl(PRCM_ARM_IT1_VAL) & I2C_MBOX_BIT) && timeout) - timeout--; - - if (timeout == 0) - return -1; - - return 0; -} - -/** - * prcmu_i2c_read - PRCMU - 4500 communication using PRCMU I2C - * @reg: - db8500 register bank to be accessed - * @slave: - db8500 register to be accessed - * Returns: ACK_MB5 value containing the status - */ -int prcmu_i2c_read(u8 reg, u16 slave) -{ - uint8_t i2c_status; - uint8_t i2c_val; - int ret; - - if (!prcmu_is_ready()) - return -1; - - debug("\nprcmu_4500_i2c_read:bank=%x;reg=%x;\n", - reg, slave); - - ret = wait_for_i2c_mbx_rdy(); - if (ret) { - printf("prcmu_i2c_read: mailbox became not ready\n"); - return ret; - } - - /* prepare the data for mailbox 5 */ - writeb(PRCMU_I2C_READ(reg), PRCM_REQ_MB5_I2COPTYPE_REG); - writeb((1 << 3) | 0x0, PRCM_REQ_MB5_BIT_FIELDS); - writeb(slave, PRCM_REQ_MB5_I2CSLAVE); - writeb(0, PRCM_REQ_MB5_I2CVAL); - - ret = wait_for_i2c_req_done(); - if (ret) { - printf("prcmu_i2c_read: mailbox request timed out\n"); - return ret; - } - - /* retrieve values */ - debug("ack-mb5:transfer status = %x\n", - readb(PRCM_ACK_MB5_STATUS)); - debug("ack-mb5:reg bank = %x\n", readb(PRCM_ACK_MB5) >> 1); - debug("ack-mb5:slave_add = %x\n", - readb(PRCM_ACK_MB5_SLAVE)); - debug("ack-mb5:reg_val = %d\n", readb(PRCM_ACK_MB5_VAL)); - - i2c_status = readb(PRCM_ACK_MB5_STATUS); - i2c_val = readb(PRCM_ACK_MB5_VAL); - /* clear mailbox 5 ack irq */ - writel(I2C_MBOX_BIT, PRCM_ARM_IT1_CLEAR); - - if (i2c_status == I2C_RD_OK) - return i2c_val; - - printf("prcmu_i2c_read:read return status= %d\n", i2c_status); - return -1; -} - -/** - * prcmu_i2c_write - PRCMU-db8500 communication using PRCMU I2C - * @reg: - db8500 register bank to be accessed - * @slave: - db800 register to be written to - * @reg_data: - the data to write - * Returns: ACK_MB5 value containing the status - */ -int prcmu_i2c_write(u8 reg, u16 slave, u8 reg_data) -{ - uint8_t i2c_status; - int ret; - - if (!prcmu_is_ready()) - return -1; - - debug("\nprcmu_4500_i2c_write:bank=%x;reg=%x;\n", - reg, slave); - - ret = wait_for_i2c_mbx_rdy(); - if (ret) { - printf("prcmu_i2c_write: mailbox became not ready\n"); - return ret; - } - - /* prepare the data for mailbox 5 */ - writeb(PRCMU_I2C_WRITE(reg), PRCM_REQ_MB5_I2COPTYPE_REG); - writeb((1 << 3) | 0x0, PRCM_REQ_MB5_BIT_FIELDS); - writeb(slave, PRCM_REQ_MB5_I2CSLAVE); - writeb(reg_data, PRCM_REQ_MB5_I2CVAL); - - ret = wait_for_i2c_req_done(); - if (ret) { - printf("prcmu_i2c_write: mailbox request timed out\n"); - return ret; - } - - /* retrieve values */ - debug("ack-mb5:transfer status = %x\n", - readb(PRCM_ACK_MB5_STATUS)); - debug("ack-mb5:reg bank = %x\n", readb(PRCM_ACK_MB5) >> 1); - debug("ack-mb5:slave_add = %x\n", - readb(PRCM_ACK_MB5_SLAVE)); - debug("ack-mb5:reg_val = %d\n", readb(PRCM_ACK_MB5_VAL)); - - i2c_status = readb(PRCM_ACK_MB5_STATUS); - debug("\ni2c_status = %x\n", i2c_status); - /* clear mailbox 5 ack irq */ - writel(I2C_MBOX_BIT, PRCM_ARM_IT1_CLEAR); - - if (i2c_status == I2C_WR_OK) - return 0; - - printf("%s: i2c_status : 0x%x\n", __func__, i2c_status); - return -1; -} - -void u8500_prcmu_enable(u32 *reg) -{ - writel(readl(reg) | (1 << 8), reg); -} - -void db8500_prcmu_init(void) -{ - /* Enable timers */ - writel(1 << 17, PRCM_TCR); - - u8500_prcmu_enable((u32 *)PRCM_PER1CLK_MGT_REG); - u8500_prcmu_enable((u32 *)PRCM_PER2CLK_MGT_REG); - u8500_prcmu_enable((u32 *)PRCM_PER3CLK_MGT_REG); - /* PER4CLK does not exist */ - u8500_prcmu_enable((u32 *)PRCM_PER5CLK_MGT_REG); - u8500_prcmu_enable((u32 *)PRCM_PER6CLK_MGT_REG); - /* Only exists in ED but is always ok to write to */ - u8500_prcmu_enable((u32 *)PRCM_PER7CLK_MGT_REG); - - u8500_prcmu_enable((u32 *)PRCM_UARTCLK_MGT_REG); - u8500_prcmu_enable((u32 *)PRCM_I2CCLK_MGT_REG); - - u8500_prcmu_enable((u32 *)PRCM_SDMMCCLK_MGT_REG); - - /* Clean up the mailbox interrupts after pre-u-boot code. */ - writel(I2C_MBOX_BIT, PRCM_ARM_IT1_CLEAR); -} diff --git a/arch/arm/cpu/armv7/u8500/timer.c b/arch/arm/cpu/armv7/u8500/timer.c deleted file mode 100644 index 6b74e13d9c..0000000000 --- a/arch/arm/cpu/armv7/u8500/timer.c +++ /dev/null @@ -1,135 +0,0 @@ -/* - * Copyright (C) 2010 Linaro Limited - * John Rigby <john.rigby@linaro.org> - * - * Based on original from Linux kernel source and - * internal ST-Ericsson U-Boot source. - * (C) Copyright 2009 Alessandro Rubini - * (C) Copyright 2010 ST-Ericsson - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/hardware.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* - * The MTU device has some interrupt control registers - * followed by 4 timers. - */ - -/* The timers */ -struct u8500_mtu_timer { - u32 lr; /* Load value */ - u32 cv; /* Current value */ - u32 cr; /* Control reg */ - u32 bglr; /* ??? */ -}; - -/* The MTU that contains the timers */ -struct u8500_mtu { - u32 imsc; /* Interrupt mask set/clear */ - u32 ris; /* Raw interrupt status */ - u32 mis; /* Masked interrupt status */ - u32 icr; /* Interrupt clear register */ - struct u8500_mtu_timer pt[4]; -}; - -/* bits for the control register */ -#define MTU_CR_ONESHOT 0x01 /* if 0 = wraps reloading from BGLR */ -#define MTU_CR_32BITS 0x02 - -#define MTU_CR_PRESCALE_1 0x00 -#define MTU_CR_PRESCALE_16 0x04 -#define MTU_CR_PRESCALE_256 0x08 -#define MTU_CR_PRESCALE_MASK 0x0c - -#define MTU_CR_PERIODIC 0x40 /* if 0 = free-running */ -#define MTU_CR_ENA 0x80 - -/* - * The MTU is clocked at 133 MHz by default. (V1 and later) - */ -#define TIMER_CLOCK (133 * 1000 * 1000 / 16) -#define COUNT_TO_USEC(x) ((x) * 16 / 133) -#define USEC_TO_COUNT(x) ((x) * 133 / 16) -#define TICKS_PER_HZ (TIMER_CLOCK / CONFIG_SYS_HZ) -#define TICKS_TO_HZ(x) ((x) / TICKS_PER_HZ) -#define TIMER_LOAD_VAL 0xffffffff - -/* - * MTU timer to use (from 0 to 3). - */ -#define MTU_TIMER 2 - -static struct u8500_mtu_timer *timer_base = - &((struct u8500_mtu *)U8500_MTU0_BASE_V1)->pt[MTU_TIMER]; - -/* macro to read the 32 bit timer: since it decrements, we invert read value */ -#define READ_TIMER() (~readl(&timer_base->cv)) - -/* Configure a free-running, auto-wrap counter with /16 prescaler */ -int timer_init(void) -{ - writel(MTU_CR_ENA | MTU_CR_PRESCALE_16 | MTU_CR_32BITS, - &timer_base->cr); - return 0; -} - -ulong get_timer_masked(void) -{ - /* current tick value */ - ulong now = TICKS_TO_HZ(READ_TIMER()); - - if (now >= gd->arch.lastinc) { /* normal (non rollover) */ - gd->arch.tbl += (now - gd->arch.lastinc); - } else { /* rollover */ - gd->arch.tbl += (TICKS_TO_HZ(TIMER_LOAD_VAL) - - gd->arch.lastinc) + now; - } - gd->arch.lastinc = now; - return gd->arch.tbl; -} - -/* Delay x useconds */ -void __udelay(ulong usec) -{ - long tmo = usec * (TIMER_CLOCK / 1000) / 1000; - ulong now, last = READ_TIMER(); - - while (tmo > 0) { - now = READ_TIMER(); - if (now > last) /* normal (non rollover) */ - tmo -= now - last; - else /* rollover */ - tmo -= TIMER_LOAD_VAL - last + now; - last = now; - } -} - -ulong get_timer(ulong base) -{ - return get_timer_masked() - base; -} - -/* - * Emulation of Power architecture long long timebase. - * - * TODO: Support gd->arch.tbu for real long long timebase. - */ -unsigned long long get_ticks(void) -{ - return get_timer(0); -} - -/* - * Emulation of Power architecture timebase. - * NB: Low resolution compared to Power tbclk. - */ -ulong get_tbclk(void) -{ - return CONFIG_SYS_HZ; -} diff --git a/arch/arm/include/asm/arch-u8500/clock.h b/arch/arm/include/asm/arch-u8500/clock.h deleted file mode 100644 index 1b2fdb7923..0000000000 --- a/arch/arm/include/asm/arch-u8500/clock.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2009 - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_CLOCK -#define __ASM_ARCH_CLOCK - -struct prcmu { - unsigned int armclkfix_mgt; - unsigned int armclk_mgt; - unsigned int svammdspclk_mgt; - unsigned int siammdspclk_mgt; - unsigned int reserved; - unsigned int sgaclk_mgt; - unsigned int uartclk_mgt; - unsigned int msp02clk_mgt; - unsigned int i2cclk_mgt; - unsigned int sdmmcclk_mgt; - unsigned int slimclk_mgt; - unsigned int per1clk_mgt; - unsigned int per2clk_mgt; - unsigned int per3clk_mgt; - unsigned int per5clk_mgt; - unsigned int per6clk_mgt; - unsigned int per7clk_mgt; - unsigned int lcdclk_mgt; - unsigned int reserved1; - unsigned int bmlclk_mgt; - unsigned int hsitxclk_mgt; - unsigned int hsirxclk_mgt; - unsigned int hdmiclk_mgt; - unsigned int apeatclk_mgt; - unsigned int apetraceclk_mgt; - unsigned int mcdeclk_mgt; - unsigned int ipi2cclk_mgt; - unsigned int dsialtclk_mgt; - unsigned int spare2clk_mgt; - unsigned int dmaclk_mgt; - unsigned int b2r2clk_mgt; - unsigned int tvclk_mgt; - unsigned int unused[82]; - unsigned int tcr; - unsigned int unused1[23]; - unsigned int ape_softrst; -}; - -extern void u8500_clock_enable(int periph, int kern, int cluster); - -void db8500_clocks_init(void); - -#endif /* __ASM_ARCH_CLOCK */ diff --git a/arch/arm/include/asm/arch-u8500/db8500_gpio.h b/arch/arm/include/asm/arch-u8500/db8500_gpio.h deleted file mode 100644 index 7c85a89172..0000000000 --- a/arch/arm/include/asm/arch-u8500/db8500_gpio.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Structures and registers for GPIO access in the Nomadik SoC - * - * Code ported from Nomadik GPIO driver in ST-Ericsson Linux kernel code. - * The purpose is that GPIO config found in kernel should work by simply - * copy-paste it to U-boot. - * - * Ported to U-boot by: - * Copyright (C) 2010 Joakim Axelsson <joakim.axelsson AT stericsson.com> - * Copyright (C) 2008 STMicroelectronics - * Author: Prafulla WADASKAR <prafulla.wadaskar@st.com> - * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __DB8500_GPIO_H__ -#define __DB8500_GPIO_H__ - -/* Alternate functions: function C is set in hw by setting both A and B */ -enum db8500_gpio_alt { - DB8500_GPIO_ALT_GPIO = 0, - DB8500_GPIO_ALT_A = 1, - DB8500_GPIO_ALT_B = 2, - DB8500_GPIO_ALT_C = (DB8500_GPIO_ALT_A | DB8500_GPIO_ALT_B) -}; - -enum db8500_gpio_pull { - DB8500_GPIO_PULL_NONE, - DB8500_GPIO_PULL_UP, - DB8500_GPIO_PULL_DOWN -}; - -void db8500_gpio_set_pull(unsigned gpio, enum db8500_gpio_pull pull); -void db8500_gpio_make_input(unsigned gpio); -int db8500_gpio_get_input(unsigned gpio); -void db8500_gpio_make_output(unsigned gpio, int val); -void db8500_gpio_set_output(unsigned gpio, int val); - -#endif /* __DB8500_GPIO_H__ */ diff --git a/arch/arm/include/asm/arch-u8500/db8500_pincfg.h b/arch/arm/include/asm/arch-u8500/db8500_pincfg.h deleted file mode 100644 index 64957016c1..0000000000 --- a/arch/arm/include/asm/arch-u8500/db8500_pincfg.h +++ /dev/null @@ -1,170 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * Code ported from Nomadik GPIO driver in ST-Ericsson Linux kernel code. - * The purpose is that GPIO config found in kernel should work by simply - * copy-paste it to U-boot. Ported 2010 to U-boot by: - * Author: Joakim Axelsson <joakim.axelsson AT stericsson.com> - * - * License terms: GNU General Public License, version 2 - * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson - * - * - * Based on arch/arm/mach-pxa/include/mach/mfp.h: - * Copyright (C) 2007 Marvell International Ltd. - * eric miao <eric.miao@marvell.com> - */ - -#ifndef __DB8500_PINCFG_H -#define __DB8500_PINCFG_H - -#include "db8500_gpio.h" - -/* - * U-boot info: - * SLPM (sleep mode) config will be ignored by U-boot but it is still - * possible to configure it in order to keep cut-n-paste compability - * with Linux kernel config. - * - * pin configurations are represented by 32-bit integers: - * - * bit 0.. 8 - Pin Number (512 Pins Maximum) - * bit 9..10 - Alternate Function Selection - * bit 11..12 - Pull up/down state - * bit 13 - Sleep mode behaviour (not used in U-boot) - * bit 14 - Direction - * bit 15 - Value (if output) - * bit 16..18 - SLPM pull up/down state (not used in U-boot) - * bit 19..20 - SLPM direction (not used in U-boot) - * bit 21..22 - SLPM Value (if output) (not used in U-boot) - * - * to facilitate the definition, the following macros are provided - * - * PIN_CFG_DEFAULT - default config (0): - * pull up/down = disabled - * sleep mode = input/wakeup - * direction = input - * value = low - * SLPM direction = same as normal - * SLPM pull = same as normal - * SLPM value = same as normal - * - * PIN_CFG - default config with alternate function - * PIN_CFG_PULL - default config with alternate function and pull up/down - */ - -/* Sleep mode */ -enum db8500_gpio_slpm { - DB8500_GPIO_SLPM_INPUT, - DB8500_GPIO_SLPM_WAKEUP_ENABLE = DB8500_GPIO_SLPM_INPUT, - DB8500_GPIO_SLPM_NOCHANGE, - DB8500_GPIO_SLPM_WAKEUP_DISABLE = DB8500_GPIO_SLPM_NOCHANGE, -}; - -#define PIN_NUM_MASK 0x1ff -#define PIN_NUM(x) ((x) & PIN_NUM_MASK) - -#define PIN_ALT_SHIFT 9 -#define PIN_ALT_MASK (0x3 << PIN_ALT_SHIFT) -#define PIN_ALT(x) (((x) & PIN_ALT_MASK) >> PIN_ALT_SHIFT) -#define PIN_GPIO (DB8500_GPIO_ALT_GPIO << PIN_ALT_SHIFT) -#define PIN_ALT_A (DB8500_GPIO_ALT_A << PIN_ALT_SHIFT) -#define PIN_ALT_B (DB8500_GPIO_ALT_B << PIN_ALT_SHIFT) -#define PIN_ALT_C (DB8500_GPIO_ALT_C << PIN_ALT_SHIFT) - -#define PIN_PULL_SHIFT 11 -#define PIN_PULL_MASK (0x3 << PIN_PULL_SHIFT) -#define PIN_PULL(x) (((x) & PIN_PULL_MASK) >> PIN_PULL_SHIFT) -#define PIN_PULL_NONE (DB8500_GPIO_PULL_NONE << PIN_PULL_SHIFT) -#define PIN_PULL_UP (DB8500_GPIO_PULL_UP << PIN_PULL_SHIFT) -#define PIN_PULL_DOWN (DB8500_GPIO_PULL_DOWN << PIN_PULL_SHIFT) - -#define PIN_SLPM_SHIFT 13 -#define PIN_SLPM_MASK (0x1 << PIN_SLPM_SHIFT) -#define PIN_SLPM(x) (((x) & PIN_SLPM_MASK) >> PIN_SLPM_SHIFT) -#define PIN_SLPM_MAKE_INPUT (DB8500_GPIO_SLPM_INPUT << PIN_SLPM_SHIFT) -#define PIN_SLPM_NOCHANGE (DB8500_GPIO_SLPM_NOCHANGE << PIN_SLPM_SHIFT) -/* These two replace the above in DB8500v2+ */ -#define PIN_SLPM_WAKEUP_ENABLE \ - (DB8500_GPIO_SLPM_WAKEUP_ENABLE << PIN_SLPM_SHIFT) -#define PIN_SLPM_WAKEUP_DISABLE \ - (DB8500_GPIO_SLPM_WAKEUP_DISABLE << PIN_SLPM_SHIFT) - -#define PIN_DIR_SHIFT 14 -#define PIN_DIR_MASK (0x1 << PIN_DIR_SHIFT) -#define PIN_DIR(x) (((x) & PIN_DIR_MASK) >> PIN_DIR_SHIFT) -#define PIN_DIR_INPUT (0 << PIN_DIR_SHIFT) -#define PIN_DIR_OUTPUT (1 << PIN_DIR_SHIFT) - -#define PIN_VAL_SHIFT 15 -#define PIN_VAL_MASK (0x1 << PIN_VAL_SHIFT) -#define PIN_VAL(x) (((x) & PIN_VAL_MASK) >> PIN_VAL_SHIFT) -#define PIN_VAL_LOW (0 << PIN_VAL_SHIFT) -#define PIN_VAL_HIGH (1 << PIN_VAL_SHIFT) - -#define PIN_SLPM_PULL_SHIFT 16 -#define PIN_SLPM_PULL_MASK (0x7 << PIN_SLPM_PULL_SHIFT) -#define PIN_SLPM_PULL(x) \ - (((x) & PIN_SLPM_PULL_MASK) >> PIN_SLPM_PULL_SHIFT) -#define PIN_SLPM_PULL_NONE \ - ((1 + DB8500_GPIO_PULL_NONE) << PIN_SLPM_PULL_SHIFT) -#define PIN_SLPM_PULL_UP \ - ((1 + DB8500_GPIO_PULL_UP) << PIN_SLPM_PULL_SHIFT) -#define PIN_SLPM_PULL_DOWN \ - ((1 + DB8500_GPIO_PULL_DOWN) << PIN_SLPM_PULL_SHIFT) - -#define PIN_SLPM_DIR_SHIFT 19 -#define PIN_SLPM_DIR_MASK (0x3 << PIN_SLPM_DIR_SHIFT) -#define PIN_SLPM_DIR(x) \ - (((x) & PIN_SLPM_DIR_MASK) >> PIN_SLPM_DIR_SHIFT) -#define PIN_SLPM_DIR_INPUT ((1 + 0) << PIN_SLPM_DIR_SHIFT) -#define PIN_SLPM_DIR_OUTPUT ((1 + 1) << PIN_SLPM_DIR_SHIFT) - -#define PIN_SLPM_VAL_SHIFT 21 -#define PIN_SLPM_VAL_MASK (0x3 << PIN_SLPM_VAL_SHIFT) -#define PIN_SLPM_VAL(x) \ - (((x) & PIN_SLPM_VAL_MASK) >> PIN_SLPM_VAL_SHIFT) -#define PIN_SLPM_VAL_LOW ((1 + 0) << PIN_SLPM_VAL_SHIFT) -#define PIN_SLPM_VAL_HIGH ((1 + 1) << PIN_SLPM_VAL_SHIFT) - -/* Shortcuts. Use these instead of separate DIR, PULL, and VAL. */ -#define PIN_INPUT_PULLDOWN (PIN_DIR_INPUT | PIN_PULL_DOWN) -#define PIN_INPUT_PULLUP (PIN_DIR_INPUT | PIN_PULL_UP) -#define PIN_INPUT_NOPULL (PIN_DIR_INPUT | PIN_PULL_NONE) -#define PIN_OUTPUT_LOW (PIN_DIR_OUTPUT | PIN_VAL_LOW) -#define PIN_OUTPUT_HIGH (PIN_DIR_OUTPUT | PIN_VAL_HIGH) - -#define PIN_SLPM_INPUT_PULLDOWN (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_DOWN) -#define PIN_SLPM_INPUT_PULLUP (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_UP) -#define PIN_SLPM_INPUT_NOPULL (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_NONE) -#define PIN_SLPM_OUTPUT_LOW (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_LOW) -#define PIN_SLPM_OUTPUT_HIGH (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_HIGH) - -#define PIN_CFG_DEFAULT (0) - -#define PIN_CFG(num, alt) \ - (PIN_CFG_DEFAULT |\ - (PIN_NUM(num) | PIN_##alt)) - -#define PIN_CFG_INPUT(num, alt, pull) \ - (PIN_CFG_DEFAULT |\ - (PIN_NUM(num) | PIN_##alt | PIN_INPUT_##pull)) - -#define PIN_CFG_OUTPUT(num, alt, val) \ - (PIN_CFG_DEFAULT |\ - (PIN_NUM(num) | PIN_##alt | PIN_OUTPUT_##val)) - -#define PIN_CFG_PULL(num, alt, pull) \ - ((PIN_CFG_DEFAULT & ~PIN_PULL_MASK) |\ - (PIN_NUM(num) | PIN_##alt | PIN_PULL_##pull)) - -/** - * db8500_gpio_config_pins - configure several pins at once - * @cfgs: array of pin configurations - * @num: number of elments in the array - * - * Configures several GPIO pins. - */ -void db8500_gpio_config_pins(unsigned long *cfgs, size_t num); - -#endif diff --git a/arch/arm/include/asm/arch-u8500/gpio.h b/arch/arm/include/asm/arch-u8500/gpio.h deleted file mode 100644 index afa5942c99..0000000000 --- a/arch/arm/include/asm/arch-u8500/gpio.h +++ /dev/null @@ -1,231 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2009 - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _UX500_GPIO_h -#define _UX500_GPIO_h - -#include <asm/types.h> -#include <asm/io.h> -#include <asm/errno.h> - -#include <asm/arch/sys_proto.h> -#include <asm/arch/u8500.h> - -#define GPIO_TOTAL_PINS 268 - -#define GPIO_PINS_PER_BLOCK 32 -#define GPIO_BLOCKS_COUNT (GPIO_TOTAL_PINS/GPIO_PINS_PER_BLOCK + 1) -#define GPIO_BLOCK(pin) (((pin + GPIO_PINS_PER_BLOCK) >> 5) - 1) - - -struct gpio_register { - u32 gpio_dat; /* data register : 0x000 */ - u32 gpio_dats; /* data Set register : 0x004 */ - u32 gpio_datc; /* data Clear register : 0x008 */ - u32 gpio_pdis; /* Pull disable register : 0x00C */ - u32 gpio_dir; /* data direction register : 0x010 */ - u32 gpio_dirs; /* data dir Set register : 0x014 */ - u32 gpio_dirc; /* data dir Clear register : 0x018 */ - u32 gpio_slpm; /* Sleep mode register : 0x01C */ - u32 gpio_afsa; /* AltFun A Select reg : 0x020 */ - u32 gpio_afsb; /* AltFun B Select reg : 0x024 */ - u32 gpio_lowemi;/* low EMI Select reg : 0x028 */ - u32 reserved_1[(0x040 - 0x02C) >> 2]; /*0x028-0x3C Reserved*/ - u32 gpio_rimsc; /* rising edge intr set/clear : 0x040 */ - u32 gpio_fimsc; /* falling edge intr set/clear register : 0x044 */ - u32 gpio_mis; /* masked interrupt status register : 0x048 */ - u32 gpio_ic; /* Interrupt Clear register : 0x04C */ - u32 gpio_rwimsc;/* Rising-edge Wakeup IMSC register : 0x050 */ - u32 gpio_fwimsc;/* Falling-edge Wakeup IMSC register : 0x054 */ - u32 gpio_wks; /* Wakeup Status register : 0x058 */ -}; - -/* Error values returned by functions */ -enum gpio_error { - GPIO_OK = 0, - GPIO_UNSUPPORTED_HW = -2, - GPIO_UNSUPPORTED_FEATURE = -3, - GPIO_INVALID_PARAMETER = -4, - GPIO_REQUEST_NOT_APPLICABLE = -5, - GPIO_REQUEST_PENDING = -6, - GPIO_NOT_CONFIGURED = -7, - GPIO_INTERNAL_ERROR = -8, - GPIO_INTERNAL_EVENT = 1, - GPIO_REMAINING_EVENT = 2, - GPIO_NO_MORE_PENDING_EVENT = 3, - GPIO_INVALID_CLIENT = -25, - GPIO_INVALID_PIN = -26, - GPIO_PIN_BUSY = -27, - GPIO_PIN_NOT_ALLOCATED = -28, - GPIO_WRONG_CLIENT = -29, - GPIO_UNSUPPORTED_ALTFUNC = -30, -}; - -/*GPIO DEVICE ID */ -enum gpio_device_id { - GPIO_DEVICE_ID_0, - GPIO_DEVICE_ID_1, - GPIO_DEVICE_ID_2, - GPIO_DEVICE_ID_3, - GPIO_DEVICE_ID_INVALID -}; - -/* - * Alternate Function: - * refered in altfun_table to pointout particular altfun to be enabled - * when using GPIO_ALT_FUNCTION A/B/C enable/disable operation - */ -enum gpio_alt_function { - GPIO_ALT_UART_0_MODEM, - GPIO_ALT_UART_0_NO_MODEM, - GPIO_ALT_UART_1, - GPIO_ALT_UART_2, - GPIO_ALT_I2C_0, - GPIO_ALT_I2C_1, - GPIO_ALT_I2C_2, - GPIO_ALT_I2C_3, - GPIO_ALT_MSP_0, - GPIO_ALT_MSP_1, - GPIO_ALT_MSP_2, - GPIO_ALT_MSP_3, - GPIO_ALT_MSP_4, - GPIO_ALT_MSP_5, - GPIO_ALT_SSP_0, - GPIO_ALT_SSP_1, - GPIO_ALT_MM_CARD0, - GPIO_ALT_SD_CARD0, - GPIO_ALT_DMA_0, - GPIO_ALT_DMA_1, - GPIO_ALT_HSI0, - GPIO_ALT_CCIR656_INPUT, - GPIO_ALT_CCIR656_OUTPUT, - GPIO_ALT_LCD_PANEL, - GPIO_ALT_MDIF, - GPIO_ALT_SDRAM, - GPIO_ALT_HAMAC_AUDIO_DBG, - GPIO_ALT_HAMAC_VIDEO_DBG, - GPIO_ALT_CLOCK_RESET, - GPIO_ALT_TSP, - GPIO_ALT_IRDA, - GPIO_ALT_USB_MINIMUM, - GPIO_ALT_USB_I2C, - GPIO_ALT_OWM, - GPIO_ALT_PWL, - GPIO_ALT_FSMC, - GPIO_ALT_COMP_FLASH, - GPIO_ALT_SRAM_NOR_FLASH, - GPIO_ALT_FSMC_ADDLINE_0_TO_15, - GPIO_ALT_SCROLL_KEY, - GPIO_ALT_MSHC, - GPIO_ALT_HPI, - GPIO_ALT_USB_OTG, - GPIO_ALT_SDIO, - GPIO_ALT_HSMMC, - GPIO_ALT_FSMC_ADD_DATA_0_TO_25, - GPIO_ALT_HSI1, - GPIO_ALT_NOR, - GPIO_ALT_NAND, - GPIO_ALT_KEYPAD, - GPIO_ALT_VPIP, - GPIO_ALT_CAM, - GPIO_ALT_CCP1, - GPIO_ALT_EMMC, - GPIO_ALT_POP_EMMC, - GPIO_ALT_FUNMAX /* Add new alt func before this */ -}; - -/* Defines pin assignment(Software mode or Alternate mode) */ -enum gpio_mode { - GPIO_MODE_LEAVE_UNCHANGED, /* Parameter will be ignored */ - GPIO_MODE_SOFTWARE, /* Pin connected to GPIO (SW controlled) */ - GPIO_ALTF_A, /* Pin connected to altfunc 1 (HW periph 1) */ - GPIO_ALTF_B, /* Pin connected to altfunc 2 (HW periph 2) */ - GPIO_ALTF_C, /* Pin connected to altfunc 3 (HW periph 3) */ - GPIO_ALTF_FIND, /* Pin connected to altfunc 3 (HW periph 3) */ - GPIO_ALTF_DISABLE /* Pin connected to altfunc 3 (HW periph 3) */ -}; - -/* Defines GPIO pin direction */ -enum gpio_direction { - GPIO_DIR_LEAVE_UNCHANGED, /* Parameter will be ignored */ - GPIO_DIR_INPUT, /* GPIO set as input */ - GPIO_DIR_OUTPUT /* GPIO set as output */ -}; - -/* Interrupt trigger mode */ -enum gpio_trig { - GPIO_TRIG_LEAVE_UNCHANGED, /* Parameter will be ignored */ - GPIO_TRIG_DISABLE, /* Trigger no IT */ - GPIO_TRIG_RISING_EDGE, /* Trigger an IT on rising edge */ - GPIO_TRIG_FALLING_EDGE, /* Trigger an IT on falling edge */ - GPIO_TRIG_BOTH_EDGES, /* Trigger an IT on rising and falling edge */ - GPIO_TRIG_HIGH_LEVEL, /* Trigger an IT on high level */ - GPIO_TRIG_LOW_LEVEL /* Trigger an IT on low level */ -}; - -/* Configuration parameters for one GPIO pin.*/ -struct gpio_config { - enum gpio_mode mode; - enum gpio_direction direction; - enum gpio_trig trig; - char *dev_name; /* Who owns the gpio pin */ -}; - -/* GPIO pin data*/ -enum gpio_data { - GPIO_DATA_LOW, - GPIO_DATA_HIGH -}; - -/* GPIO behaviour in sleep mode */ -enum gpio_sleep_mode { - GPIO_SLEEP_MODE_LEAVE_UNCHANGED, /* Parameter will be ignored */ - GPIO_SLEEP_MODE_INPUT_DEFAULTVOLT, /* GPIO is an input with pull - up/down enabled when in sleep - mode. */ - GPIO_SLEEP_MODE_CONTROLLED_BY_GPIO /* GPIO pin is controlled by - GPIO IP. So mode, direction - and data values for GPIO pin - in sleep mode are determined - by configuration set to GPIO - pin before entering to sleep - mode. */ -}; - -/* GPIO ability to wake the system up from sleep mode.*/ -enum gpio_wake { - GPIO_WAKE_LEAVE_UNCHANGED, /* Parameter will be ignored */ - GPIO_WAKE_DISABLE, /* No wake of system from sleep mode. */ - GPIO_WAKE_LOW_LEVEL, /* Wake the system up on a LOW level. */ - GPIO_WAKE_HIGH_LEVEL, /* Wake the system up on a HIGH level. */ - GPIO_WAKE_RISING_EDGE, /* Wake the system up on a RISING edge. */ - GPIO_WAKE_FALLING_EDGE, /* Wake the system up on a FALLING edge. */ - GPIO_WAKE_BOTH_EDGES /* Wake the system up on both RISE and FALL. */ -}; - -/* Configuration parameters for one GPIO pin in sleep mode.*/ -struct gpio_sleep_config { - enum gpio_sleep_mode sleep_mode;/* GPIO behaviour in sleep mode. */ - enum gpio_wake wake; /* GPIO ability to wake up system. */ -}; - -extern int gpio_setpinconfig(int pin_id, struct gpio_config *pin_config); -extern int gpio_resetpinconfig(int pin_id, char *dev_name); -extern int gpio_writepin(int pin_id, enum gpio_data value, char *dev_name); -extern int gpio_readpin(int pin_id, enum gpio_data *value); -extern int gpio_altfuncenable(enum gpio_alt_function altfunc, - char *dev_name); -extern int gpio_altfuncdisable(enum gpio_alt_function altfunc, - char *dev_name); - -struct gpio_altfun_data { - u16 altfun; - u16 start; - u16 end; - u16 cont; - u8 type; -}; -#endif diff --git a/arch/arm/include/asm/arch-u8500/hardware.h b/arch/arm/include/asm/arch-u8500/hardware.h deleted file mode 100644 index e6a899dac1..0000000000 --- a/arch/arm/include/asm/arch-u8500/hardware.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2009 - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -/* Peripheral clusters */ - -#define U8500_PER3_BASE 0x80000000 -#define U8500_PER2_BASE 0x80110000 -#define U8500_PER1_BASE 0x80120000 -#define U8500_PER4_BASE 0x80150000 - -#define U8500_PER6_BASE 0xa03c0000 -#define U8500_PER7_BASE 0xa03d0000 -#define U8500_PER5_BASE 0xa03e0000 - -/* GPIO */ - -#define U8500_GPIO0_BASE (U8500_PER1_BASE + 0xE000) -#define U8500_GPIO1_BASE (U8500_PER1_BASE + 0xE000 + 0x80) - -#define U8500_GPIO2_BASE (U8500_PER3_BASE + 0xE000) -#define U8500_GPIO3_BASE (U8500_PER3_BASE + 0xE000 + 0x80) -#define U8500_GPIO4_BASE (U8500_PER3_BASE + 0xE000 + 0x100) -#define U8500_GPIO5_BASE (U8500_PER3_BASE + 0xE000 + 0x180) - -#define U8500_GPIO6_BASE (U8500_PER2_BASE + 0xE000) -#define U8500_GPIO7_BASE (U8500_PER2_BASE + 0xE000 + 0x80) - -#define U8500_GPIO8_BASE (U8500_PER5_BASE + 0x1E000) - -/* Per7 */ -#define U8500_CLKRST7_BASE (U8500_PER7_BASE + 0xf000) - -/* Per6 */ -#define U8500_MTU0_BASE_V1 (U8500_PER6_BASE + 0x6000) -#define U8500_MTU1_BASE_V1 (U8500_PER6_BASE + 0x7000) -#define U8500_CLKRST6_BASE (U8500_PER6_BASE + 0xf000) - -/* Per5 */ -#define U8500_CLKRST5_BASE (U8500_PER5_BASE + 0x1f000) - -/* Per4 */ -#define U8500_PRCMU_BASE (U8500_PER4_BASE + 0x07000) -#define U8500_PRCMU_TCDM_BASE (U8500_PER4_BASE + 0x68000) - -/* Per3 */ -#define U8500_UART2_BASE (U8500_PER3_BASE + 0x7000) -#define U8500_CLKRST3_BASE (U8500_PER3_BASE + 0xf000) - -/* Per2 */ -#define U8500_CLKRST2_BASE (U8500_PER2_BASE + 0xf000) - -/* Per1 */ -#define U8500_UART0_BASE (U8500_PER1_BASE + 0x0000) -#define U8500_UART1_BASE (U8500_PER1_BASE + 0x1000) -#define U8500_CLKRST1_BASE (U8500_PER1_BASE + 0xf000) - -/* Last page of Boot ROM */ -#define U8500_BOOTROM_BASE 0x90000000 -#define U8500_ASIC_ID_LOC_ED_V1 (U8500_BOOTROM_BASE + 0x1FFF4) -#define U8500_ASIC_ID_LOC_V2 (U8500_BOOTROM_BASE + 0x1DBF4) - -/* AB8500 specifics */ - -/* address bank */ -#define AB8500_REGU_CTRL2 0x0004 -#define AB8500_MISC 0x0010 - -/* registers */ -#define AB8500_REGU_VRF1VAUX3_REGU_REG 0x040A -#define AB8500_REGU_VRF1VAUX3_SEL_REG 0x0421 -#define AB8500_REV_REG 0x1080 - -#define AB8500_GPIO_SEL2_REG 0x1001 -#define AB8500_GPIO_DIR2_REG 0x1011 -#define AB8500_GPIO_DIR4_REG 0x1013 -#define AB8500_GPIO_SEL4_REG 0x1003 -#define AB8500_GPIO_OUT2_REG 0x1021 -#define AB8500_GPIO_OUT4_REG 0x1023 - -#define LDO_VAUX3_ENABLE_MASK 0x3 -#define LDO_VAUX3_ENABLE_VAL 0x1 -#define LDO_VAUX3_SEL_MASK 0xf -#define LDO_VAUX3_SEL_2V9 0xd -#define LDO_VAUX3_V2_SEL_MASK 0x7 -#define LDO_VAUX3_V2_SEL_2V91 0x7 - - -#endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-u8500/prcmu.h b/arch/arm/include/asm/arch-u8500/prcmu.h deleted file mode 100644 index e7f0450079..0000000000 --- a/arch/arm/include/asm/arch-u8500/prcmu.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright (C) 2009 ST-Ericsson SA - * - * Copied from the Linux version: - * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __MACH_PRCMU_FW_V1_H -#define __MACH_PRCMU_FW_V1_H - -#define AP_EXECUTE 2 -#define I2CREAD 1 -#define I2C_WR_OK 1 -#define I2C_RD_OK 2 -#define I2CWRITE 0 - -#define PRCMU_BASE U8500_PRCMU_BASE -#define PRCMU_BASE_TCDM U8500_PRCMU_TCDM_BASE -#define PRCM_UARTCLK_MGT_REG (PRCMU_BASE + 0x018) -#define PRCM_MSPCLK_MGT_REG (PRCMU_BASE + 0x01C) -#define PRCM_I2CCLK_MGT_REG (PRCMU_BASE + 0x020) -#define PRCM_SDMMCCLK_MGT_REG (PRCMU_BASE + 0x024) -#define PRCM_PER1CLK_MGT_REG (PRCMU_BASE + 0x02C) -#define PRCM_PER2CLK_MGT_REG (PRCMU_BASE + 0x030) -#define PRCM_PER3CLK_MGT_REG (PRCMU_BASE + 0x034) -#define PRCM_PER5CLK_MGT_REG (PRCMU_BASE + 0x038) -#define PRCM_PER6CLK_MGT_REG (PRCMU_BASE + 0x03C) -#define PRCM_PER7CLK_MGT_REG (PRCMU_BASE + 0x040) -#define PRCM_MBOX_CPU_VAL (PRCMU_BASE + 0x0FC) -#define PRCM_MBOX_CPU_SET (PRCMU_BASE + 0x100) - -#define PRCM_ARM_IT1_CLEAR (PRCMU_BASE + 0x48C) -#define PRCM_ARM_IT1_VAL (PRCMU_BASE + 0x494) -#define PRCM_TCR (PRCMU_BASE + 0x1C8) -#define PRCM_REQ_MB5 (PRCMU_BASE_TCDM + 0xE44) -#define PRCM_ACK_MB5 (PRCMU_BASE_TCDM + 0xDF4) -#define PRCM_XP70_CUR_PWR_STATE (PRCMU_BASE_TCDM + 0xFFC) -/* Mailbox 5 Requests */ -#define PRCM_REQ_MB5_I2COPTYPE_REG (PRCM_REQ_MB5 + 0x0) -#define PRCM_REQ_MB5_BIT_FIELDS (PRCM_REQ_MB5 + 0x1) -#define PRCM_REQ_MB5_I2CSLAVE (PRCM_REQ_MB5 + 0x2) -#define PRCM_REQ_MB5_I2CVAL (PRCM_REQ_MB5 + 0x3) - -/* Mailbox 5 ACKs */ -#define PRCM_ACK_MB5_STATUS (PRCM_ACK_MB5 + 0x1) -#define PRCM_ACK_MB5_SLAVE (PRCM_ACK_MB5 + 0x2) -#define PRCM_ACK_MB5_VAL (PRCM_ACK_MB5 + 0x3) - -#define LOW_POWER_WAKEUP 1 -#define EXE_WAKEUP 0 - -#define REQ_MB5 5 - -#define ab8500_read prcmu_i2c_read -#define ab8500_write prcmu_i2c_write - -int prcmu_i2c_read(u8 reg, u16 slave); -int prcmu_i2c_write(u8 reg, u16 slave, u8 reg_data); - -void u8500_prcmu_enable(u32 *reg); -void db8500_prcmu_init(void); - -#endif /* __MACH_PRCMU_FW_V1_H */ diff --git a/arch/arm/include/asm/arch-u8500/sys_proto.h b/arch/arm/include/asm/arch-u8500/sys_proto.h deleted file mode 100644 index 03a3cd35bc..0000000000 --- a/arch/arm/include/asm/arch-u8500/sys_proto.h +++ /dev/null @@ -1,12 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2010 - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _SYS_PROTO_H_ -#define _SYS_PROTO_H_ - -void gpio_init(void); -int u8500_mmc_power_init(void); - -#endif /* _SYS_PROTO_H_ */ diff --git a/arch/arm/include/asm/arch-u8500/u8500.h b/arch/arm/include/asm/arch-u8500/u8500.h deleted file mode 100644 index 16ad081bc1..0000000000 --- a/arch/arm/include/asm/arch-u8500/u8500.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright (C) ST-Ericsson SA 2009 - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __U8500_H -#define __U8500_H - -/* - * base register values for U8500 - */ -#define CFG_PRCMU_BASE 0x80157000 /* Power, reset and clock - Management Unit */ -#define CFG_SDRAMC_BASE 0x903CF000 /* SDRAMC cnf registers */ -#define CFG_FSMC_BASE 0x80000000 /* FSMC Controller */ - -/* - * U8500 GPIO register base for 9 banks - */ -#define U8500_GPIO_0_BASE 0x8012E000 -#define U8500_GPIO_1_BASE 0x8012E080 -#define U8500_GPIO_2_BASE 0x8000E000 -#define U8500_GPIO_3_BASE 0x8000E080 -#define U8500_GPIO_4_BASE 0x8000E100 -#define U8500_GPIO_5_BASE 0x8000E180 -#define U8500_GPIO_6_BASE 0x8011E000 -#define U8500_GPIO_7_BASE 0x8011E080 -#define U8500_GPIO_8_BASE 0xA03FE000 - -#endif /* __U8500_H */ |
