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-rw-r--r--arch/x86/cpu/cpu.c4
-rw-r--r--arch/x86/cpu/intel_common/cpu.c4
2 files changed, 4 insertions, 4 deletions
diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index afc3ecd7a8..7dfe0713ba 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -469,14 +469,14 @@ void flush_cache(unsigned long dummy1, unsigned long dummy2)
__weak void reset_cpu(ulong addr)
{
/* Do a hard reset through the chipset's reset control register */
- outb(SYS_RST | RST_CPU, PORT_RESET);
+ outb(SYS_RST | RST_CPU, IO_PORT_RESET);
for (;;)
cpu_hlt();
}
void x86_full_reset(void)
{
- outb(FULL_RST | SYS_RST | RST_CPU, PORT_RESET);
+ outb(FULL_RST | SYS_RST | RST_CPU, IO_PORT_RESET);
}
int dcache_status(void)
diff --git a/arch/x86/cpu/intel_common/cpu.c b/arch/x86/cpu/intel_common/cpu.c
index 1210943802..93e4505e4d 100644
--- a/arch/x86/cpu/intel_common/cpu.c
+++ b/arch/x86/cpu/intel_common/cpu.c
@@ -102,8 +102,8 @@ int cpu_set_flex_ratio_to_tdp_nominal(void)
setbits_le32(RCB_REG(SOFT_RESET_CTRL), 1);
/* Issue warm reset, will be "CPU only" due to soft reset data */
- outb(0x0, PORT_RESET);
- outb(SYS_RST | RST_CPU, PORT_RESET);
+ outb(0x0, IO_PORT_RESET);
+ outb(SYS_RST | RST_CPU, IO_PORT_RESET);
cpu_hlt();
/* Not reached */
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