3 files changed, 3 insertions, 6 deletions

diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
index cefabe769f..ee7ef0f214 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -236,7 +236,7 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
 	 * tAXPD=1, need design to confirm.
 	 */
 	int tXP = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */
-	unsigned int data_rate = fsl_ddr_get_mem_data_rate();
+	unsigned int data_rate = get_ddr_freq(0);
 	tmrd_mclk = 4;
 	/* set the turnaround time */
 	trwt_mclk = 1;
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
index c7c12c1c2f..1e866fe035 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
@@ -80,5 +80,4 @@ extern void check_interleaving_options(fsl_ddr_info_t *pinfo);
 extern unsigned int mclk_to_picos(unsigned int mclk);
 extern unsigned int get_memory_clk_period_ps(void);
 extern unsigned int picos_to_mclk(unsigned int picos);
-extern unsigned int fsl_ddr_get_mem_data_rate(void);
 #endif
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/util.c b/arch/powerpc/cpu/mpc8xxx/ddr/util.c
index 1e2d921286..815c5e3a9e 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/util.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/util.c
@@ -11,8 +11,6 @@
 
 #include "ddr.h"
 
-unsigned int fsl_ddr_get_mem_data_rate(void);
-
 /*
  * Round mclk_ps to nearest 10 ps in memory controller code.
  *
@@ -24,7 +22,7 @@ unsigned int get_memory_clk_period_ps(void)
 {
 	unsigned int mclk_ps;
 
-	mclk_ps = 2000000000000ULL / fsl_ddr_get_mem_data_rate();
+	mclk_ps = 2000000000000ULL / get_ddr_freq(0);
 	/* round to nearest 10 ps */
 	return 10 * ((mclk_ps + 5) / 10);
 }
@@ -40,7 +38,7 @@ unsigned int picos_to_mclk(unsigned int picos)
 	if (!picos)
 		return 0;
 
-	clks = fsl_ddr_get_mem_data_rate() * (unsigned long long) picos;
+	clks = get_ddr_freq(0) * (unsigned long long) picos;
 	clks_temp = clks;
 	clks = clks / ULL_2e12;
 	if (clks_temp % ULL_2e12) {