diff options
Diffstat (limited to 'arch/m68k/cpu/mcf547x_8x/cpu_init.c')
| -rw-r--r-- | arch/m68k/cpu/mcf547x_8x/cpu_init.c | 84 |
1 files changed, 43 insertions, 41 deletions
diff --git a/arch/m68k/cpu/mcf547x_8x/cpu_init.c b/arch/m68k/cpu/mcf547x_8x/cpu_init.c index 60c91267a7..4eb8a7c182 100644 --- a/arch/m68k/cpu/mcf547x_8x/cpu_init.c +++ b/arch/m68k/cpu/mcf547x_8x/cpu_init.c @@ -3,7 +3,7 @@ * (C) Copyright 2000-2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * (C) Copyright 2007 Freescale Semiconductor, Inc. + * (C) Copyright 2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -28,6 +28,7 @@ #include <common.h> #include <MCD_dma.h> #include <asm/immap.h> +#include <asm/io.h> #if defined(CONFIG_CMD_NET) #include <config.h> @@ -44,58 +45,59 @@ */ void cpu_init_f(void) { - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; - volatile xlbarb_t *xlbarb = (volatile xlbarb_t *) MMAP_XARB; + gpio_t *gpio = (gpio_t *) MMAP_GPIO; + fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; + xlbarb_t *xlbarb = (xlbarb_t *) MMAP_XARB; - xlbarb->adrto = 0x2000; - xlbarb->datto = 0x2500; - xlbarb->busto = 0x3000; + out_be32(&xlbarb->adrto, 0x2000); + out_be32(&xlbarb->datto, 0x2500); + out_be32(&xlbarb->busto, 0x3000); - xlbarb->cfg = XARB_CFG_AT | XARB_CFG_DT; + out_be32(&xlbarb->cfg, XARB_CFG_AT | XARB_CFG_DT); /* Master Priority Enable */ - xlbarb->prien = 0xff; - xlbarb->pri = 0; + out_be32(&xlbarb->prien, 0xff); + out_be32(&xlbarb->pri, 0); #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL)) - fbcs->csar0 = CONFIG_SYS_CS0_BASE; - fbcs->cscr0 = CONFIG_SYS_CS0_CTRL; - fbcs->csmr0 = CONFIG_SYS_CS0_MASK; + out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE); + out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL); + out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK); #endif #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL)) - fbcs->csar1 = CONFIG_SYS_CS1_BASE; - fbcs->cscr1 = CONFIG_SYS_CS1_CTRL; - fbcs->csmr1 = CONFIG_SYS_CS1_MASK; + out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE); + out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL); + out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK); #endif #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL)) - fbcs->csar2 = CONFIG_SYS_CS2_BASE; - fbcs->cscr2 = CONFIG_SYS_CS2_CTRL; - fbcs->csmr2 = CONFIG_SYS_CS2_MASK; + out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE); + out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL); + out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK); #endif #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL)) - fbcs->csar3 = CONFIG_SYS_CS3_BASE; - fbcs->cscr3 = CONFIG_SYS_CS3_CTRL; - fbcs->csmr3 = CONFIG_SYS_CS3_MASK; + out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE); + out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL); + out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK); #endif #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL)) - fbcs->csar4 = CONFIG_SYS_CS4_BASE; - fbcs->cscr4 = CONFIG_SYS_CS4_CTRL; - fbcs->csmr4 = CONFIG_SYS_CS4_MASK; + out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE); + out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL); + out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK); #endif #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL)) - fbcs->csar5 = CONFIG_SYS_CS5_BASE; - fbcs->cscr5 = CONFIG_SYS_CS5_CTRL; - fbcs->csmr5 = CONFIG_SYS_CS5_MASK; + out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE); + out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL); + out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK); #endif #ifdef CONFIG_FSL_I2C - gpio->par_feci2cirq = GPIO_PAR_FECI2CIRQ_SCL | GPIO_PAR_FECI2CIRQ_SDA; + out_be16(&gpio->par_feci2cirq, + GPIO_PAR_FECI2CIRQ_SCL | GPIO_PAR_FECI2CIRQ_SDA); #endif icache_enable(); @@ -115,44 +117,44 @@ int cpu_init_r(void) void uart_port_conf(int port) { - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - volatile u8 *pscsicr = (u8 *) (CONFIG_SYS_UART_BASE + 0x40); + gpio_t *gpio = (gpio_t *) MMAP_GPIO; + u8 *pscsicr = (u8 *) (CONFIG_SYS_UART_BASE + 0x40); /* Setup Ports: */ switch (port) { case 0: - gpio->par_psc0 = (GPIO_PAR_PSC0_TXD0 | GPIO_PAR_PSC0_RXD0); + out_8(&gpio->par_psc0, GPIO_PAR_PSC0_TXD0 | GPIO_PAR_PSC0_RXD0); break; case 1: - gpio->par_psc1 = (GPIO_PAR_PSC1_TXD1 | GPIO_PAR_PSC1_RXD1); + out_8(&gpio->par_psc1, GPIO_PAR_PSC1_TXD1 | GPIO_PAR_PSC1_RXD1); break; case 2: - gpio->par_psc2 = (GPIO_PAR_PSC2_TXD2 | GPIO_PAR_PSC2_RXD2); + out_8(&gpio->par_psc2, GPIO_PAR_PSC2_TXD2 | GPIO_PAR_PSC2_RXD2); break; case 3: - gpio->par_psc3 = (GPIO_PAR_PSC3_TXD3 | GPIO_PAR_PSC3_RXD3); + out_8(&gpio->par_psc3, GPIO_PAR_PSC3_TXD3 | GPIO_PAR_PSC3_RXD3); break; } - *pscsicr &= 0xF8; + clrbits_8(pscsicr, 0x07); } #if defined(CONFIG_CMD_NET) int fecpin_setclear(struct eth_device *dev, int setclear) { - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + gpio_t *gpio = (gpio_t *) MMAP_GPIO; struct fec_info_dma *info = (struct fec_info_dma *)dev->priv; if (setclear) { if (info->iobase == CONFIG_SYS_FEC0_IOBASE) - gpio->par_feci2cirq |= 0xF000; + setbits_be16(&gpio->par_feci2cirq, 0xf000); else - gpio->par_feci2cirq |= 0x0FC0; + setbits_be16(&gpio->par_feci2cirq, 0x0fc0); } else { if (info->iobase == CONFIG_SYS_FEC0_IOBASE) - gpio->par_feci2cirq &= 0x0FFF; + clrbits_be16(&gpio->par_feci2cirq, 0xf000); else - gpio->par_feci2cirq &= 0xF03F; + clrbits_be16(&gpio->par_feci2cirq, 0x0fc0); } return 0; } |
