diff options
Diffstat (limited to 'arch/arm')
62 files changed, 9051 insertions, 27 deletions
diff --git a/arch/arm/config.mk b/arch/arm/config.mk index 3f4453a234..24b9d7c802 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -87,3 +87,21 @@ endif ifndef CONFIG_NAND_SPL LDFLAGS_u-boot += -pie endif + +# +# FIXME: binutils versions < 2.22 have a bug in the assembler where +# branches to weak symbols can be incorrectly optimized in thumb mode +# to a short branch (b.n instruction) that won't reach when the symbol +# gets preempted +# +# http://sourceware.org/bugzilla/show_bug.cgi?id=12532 +# +ifeq ($(CONFIG_SYS_THUMB_BUILD),y) +ifeq ($(GAS_BUG_12532),) +export GAS_BUG_12532:=$(shell if [ $(call binutils-version) -lt 0222 ] ; \ + then echo y; else echo n; fi) +endif +ifeq ($(GAS_BUG_12532),y) +PLATFORM_RELFLAGS += -fno-optimize-sibling-calls +endif +endif diff --git a/arch/arm/cpu/arm1136/start.S b/arch/arm/cpu/arm1136/start.S index 2483c63efb..3752af9ddd 100644 --- a/arch/arm/cpu/arm1136/start.S +++ b/arch/arm/cpu/arm1136/start.S @@ -190,6 +190,7 @@ stack_setup: adr r0, _start cmp r0, r6 + moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ beq clear_bss /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ ldr r3, _bss_start_ofs diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S index d61364109e..667a0e0c48 100644 --- a/arch/arm/cpu/arm1176/start.S +++ b/arch/arm/cpu/arm1176/start.S @@ -252,6 +252,7 @@ stack_setup: adr r0, _start cmp r0, r6 + moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ beq clear_bss /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ ldr r3, _bss_start_ofs diff --git a/arch/arm/cpu/arm920t/start.S b/arch/arm/cpu/arm920t/start.S index 9b8604e907..14c9156c08 100644 --- a/arch/arm/cpu/arm920t/start.S +++ b/arch/arm/cpu/arm920t/start.S @@ -210,6 +210,7 @@ stack_setup: adr r0, _start cmp r0, r6 + moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ beq clear_bss /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ ldr r3, _bss_start_ofs diff --git a/arch/arm/cpu/arm925t/start.S b/arch/arm/cpu/arm925t/start.S index 1a54416866..3a483f6cae 100644 --- a/arch/arm/cpu/arm925t/start.S +++ b/arch/arm/cpu/arm925t/start.S @@ -204,6 +204,7 @@ stack_setup: adr r0, _start cmp r0, r6 + moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ beq clear_bss /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ ldr r3, _bss_start_ofs diff --git a/arch/arm/cpu/arm926ejs/kirkwood/dram.c b/arch/arm/cpu/arm926ejs/kirkwood/dram.c index 181b3e7bd3..807894fff1 100644 --- a/arch/arm/cpu/arm926ejs/kirkwood/dram.c +++ b/arch/arm/cpu/arm926ejs/kirkwood/dram.c @@ -30,38 +30,84 @@ DECLARE_GLOBAL_DATA_PTR; -#define KW_REG_CPUCS_WIN_BAR(x) (KW_REGISTER(0x1500) + (x * 0x08)) -#define KW_REG_CPUCS_WIN_SZ(x) (KW_REGISTER(0x1504) + (x * 0x08)) +struct kw_sdram_bank { + u32 win_bar; + u32 win_sz; +}; + +struct kw_sdram_addr_dec { + struct kw_sdram_bank sdram_bank[4]; +}; + +#define KW_REG_CPUCS_WIN_ENABLE (1 << 0) +#define KW_REG_CPUCS_WIN_WR_PROTECT (1 << 1) +#define KW_REG_CPUCS_WIN_WIN0_CS(x) (((x) & 0x3) << 2) +#define KW_REG_CPUCS_WIN_SIZE(x) (((x) & 0xff) << 24) + /* * kw_sdram_bar - reads SDRAM Base Address Register */ u32 kw_sdram_bar(enum memory_bank bank) { + struct kw_sdram_addr_dec *base = + (struct kw_sdram_addr_dec *)KW_REGISTER(0x1500); u32 result = 0; - u32 enable = 0x01 & readl(KW_REG_CPUCS_WIN_SZ(bank)); + u32 enable = 0x01 & readl(&base->sdram_bank[bank].win_sz); if ((!enable) || (bank > BANK3)) return 0; - result = readl(KW_REG_CPUCS_WIN_BAR(bank)); + result = readl(&base->sdram_bank[bank].win_bar); return result; } /* + * kw_sdram_bs_set - writes SDRAM Bank size + */ +static void kw_sdram_bs_set(enum memory_bank bank, u32 size) +{ + struct kw_sdram_addr_dec *base = + (struct kw_sdram_addr_dec *)KW_REGISTER(0x1500); + /* Read current register value */ + u32 reg = readl(&base->sdram_bank[bank].win_sz); + + /* Clear window size */ + reg &= ~KW_REG_CPUCS_WIN_SIZE(0xFF); + + /* Set new window size */ + reg |= KW_REG_CPUCS_WIN_SIZE((size - 1) >> 24); + + writel(reg, &base->sdram_bank[bank].win_sz); +} + +/* * kw_sdram_bs - reads SDRAM Bank size */ u32 kw_sdram_bs(enum memory_bank bank) { + struct kw_sdram_addr_dec *base = + (struct kw_sdram_addr_dec *)KW_REGISTER(0x1500); u32 result = 0; - u32 enable = 0x01 & readl(KW_REG_CPUCS_WIN_SZ(bank)); + u32 enable = 0x01 & readl(&base->sdram_bank[bank].win_sz); if ((!enable) || (bank > BANK3)) return 0; - result = 0xff000000 & readl(KW_REG_CPUCS_WIN_SZ(bank)); + result = 0xff000000 & readl(&base->sdram_bank[bank].win_sz); result += 0x01000000; return result; } +void kw_sdram_size_adjust(enum memory_bank bank) +{ + u32 size; + + /* probe currently equipped RAM size */ + size = get_ram_size((void *)kw_sdram_bar(bank), kw_sdram_bs(bank)); + + /* adjust SDRAM window size accordingly */ + kw_sdram_bs_set(bank, size); +} + #ifndef CONFIG_SYS_BOARD_DRAM_INIT int dram_init(void) { diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S index 521d46290c..2188f7e35d 100644 --- a/arch/arm/cpu/arm926ejs/start.S +++ b/arch/arm/cpu/arm926ejs/start.S @@ -236,6 +236,7 @@ stack_setup: adr r0, _start sub r9, r6, r0 /* r9 <- relocation offset */ cmp r0, r6 + moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ beq clear_bss /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy loop */ ldr r3, _bss_start_ofs diff --git a/arch/arm/cpu/arm946es/start.S b/arch/arm/cpu/arm946es/start.S index b4d1d2dd1c..30e21835cc 100644 --- a/arch/arm/cpu/arm946es/start.S +++ b/arch/arm/cpu/arm946es/start.S @@ -175,6 +175,7 @@ stack_setup: adr r0, _start cmp r0, r6 + moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ beq clear_bss /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ ldr r3, _bss_start_ofs diff --git a/arch/arm/cpu/arm_intcm/start.S b/arch/arm/cpu/arm_intcm/start.S index b85e7d4427..a133d19bc8 100644 --- a/arch/arm/cpu/arm_intcm/start.S +++ b/arch/arm/cpu/arm_intcm/start.S @@ -171,6 +171,7 @@ stack_setup: adr r0, _start cmp r0, r6 + moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ beq clear_bss /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ ldr r3, _bss_start_ofs diff --git a/arch/arm/cpu/armv7/highbank/config.mk b/arch/arm/cpu/armv7/highbank/config.mk deleted file mode 100644 index 935a147c59..0000000000 --- a/arch/arm/cpu/armv7/highbank/config.mk +++ /dev/null @@ -1 +0,0 @@ -PLATFORM_CPPFLAGS += -march=armv7-a diff --git a/arch/arm/cpu/armv7/omap-common/config.mk b/arch/arm/cpu/armv7/omap-common/config.mk index c400dccba8..217fc14447 100644 --- a/arch/arm/cpu/armv7/omap-common/config.mk +++ b/arch/arm/cpu/armv7/omap-common/config.mk @@ -20,15 +20,6 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float # Make ARMv5 to allow more compilers to work, even though its v7a. PLATFORM_CPPFLAGS += -march=armv5 -# ========================================================================= -# -# Supply options according to compiler version -# -# ========================================================================= -PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,\ - $(call cc-option,-malignment-traps,)) -PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) diff --git a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S index 9766563d02..358107776d 100644 --- a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S +++ b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S @@ -27,6 +27,7 @@ */ #include <asm/arch/omap.h> +#include <asm/arch/spl.h> #include <linux/linkage.h> ENTRY(save_boot_params) @@ -59,9 +60,9 @@ ENTRY(save_boot_params) strb r2, [r3, #BOOT_DEVICE_OFFSET] @ spl_boot_device <- r1 /* boot mode is passed only for devices that can raw/fat mode */ - cmp r2, #2 + cmp r2, #BOOT_DEVICE_XIP blt 2f - cmp r2, #7 + cmp r2, #BOOT_DEVICE_MMC2 bgt 2f /* Store the boot mode (raw/FAT) in omap_bootmode */ ldr r2, [r0, #DEV_DESC_PTR_OFFSET] @ get the device descriptor ptr diff --git a/arch/arm/cpu/armv7/rmobile/Makefile b/arch/arm/cpu/armv7/rmobile/Makefile new file mode 100644 index 0000000000..c8999bb300 --- /dev/null +++ b/arch/arm/cpu/armv7/rmobile/Makefile @@ -0,0 +1,65 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).o + +SOBJS = lowlevel_init.o +COBJS-y += cpu_info.o +COBJS-y += emac.o + +COBJS-$(CONFIG_DISPLAY_BOARDINFO) += board.o +COBJS-$(CONFIG_GLOBAL_TIMER) += timer.o +COBJS-$(CONFIG_R8A7740) += cpu_info-r8a7740.o +COBJS-$(CONFIG_R8A7740) += pfc-r8a7740.o +COBJS-$(CONFIG_SH73A0) += cpu_info-sh73a0.o +COBJS-$(CONFIG_SH73A0) += pfc-sh73a0.o +COBJS_LN-$(CONFIG_TMU_TIMER) += sh_timer.o + +COBJS := $(COBJS-y) +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) $(addprefix $(obj),$(COBJS_LN-y:.o=.c)) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS) $(COBJS_LN-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +# from arch/sh/lib/ directory +$(obj)sh_timer.c: + @rm -f $(obj)sh_timer.c + ln -s $(SRCTREE)/arch/sh/lib/time.c $(obj)sh_timer.c + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### + diff --git a/arch/arm/cpu/armv7/rmobile/board.c b/arch/arm/cpu/armv7/rmobile/board.c new file mode 100644 index 0000000000..26225903a6 --- /dev/null +++ b/arch/arm/cpu/armv7/rmobile/board.c @@ -0,0 +1,31 @@ +/* + * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> + * (C) Copyright 2012 Renesas Solutions Corp. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <asm/io.h> +#include <asm/arch/sys_proto.h> + +int checkboard(void) +{ + printf("Board: %s\n", sysinfo.board_string); + return 0; +} diff --git a/arch/arm/cpu/armv7/rmobile/config.mk b/arch/arm/cpu/armv7/rmobile/config.mk new file mode 100644 index 0000000000..1da0227e7c --- /dev/null +++ b/arch/arm/cpu/armv7/rmobile/config.mk @@ -0,0 +1,26 @@ +# +# (C) Copyright 2002 +# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float + +# Make ARMv5 to allow more compilers to work, even though its v7a. +PLATFORM_CPPFLAGS += -march=armv5 diff --git a/arch/arm/cpu/armv7/rmobile/cpu_info-r8a7740.c b/arch/arm/cpu/armv7/rmobile/cpu_info-r8a7740.c new file mode 100644 index 0000000000..223140213f --- /dev/null +++ b/arch/arm/cpu/armv7/rmobile/cpu_info-r8a7740.c @@ -0,0 +1,48 @@ +/* + * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> + * (C) Copyright 2012 Renesas Solutions Corp. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <asm/io.h> + +u32 rmobile_get_cpu_type(void) +{ + u32 id; + u32 type; + struct r8a7740_hpb *hpb = (struct r8a7740_hpb *)HPB_BASE; + + id = readl(hpb->cccr); + type = (id >> 8) & 0xFF; + + return type; +} + +u32 rmobile_get_cpu_rev(void) +{ + u32 id; + u32 rev; + struct r8a7740_hpb *hpb = (struct r8a7740_hpb *)HPB_BASE; + + id = readl(hpb->cccr); + rev = (id >> 4) & 0xF; + + return rev; +} diff --git a/arch/arm/cpu/armv7/rmobile/cpu_info-sh73a0.c b/arch/arm/cpu/armv7/rmobile/cpu_info-sh73a0.c new file mode 100644 index 0000000000..2e7ed4931f --- /dev/null +++ b/arch/arm/cpu/armv7/rmobile/cpu_info-sh73a0.c @@ -0,0 +1,60 @@ +/* + * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> + * (C) Copyright 2012 Renesas Solutions Corp. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <asm/io.h> + +u32 rmobile_get_cpu_type(void) +{ + u32 id; + u32 type; + struct sh73a0_hpb *hpb = (struct sh73a0_hpb *)HPB_BASE; + + id = readl(&hpb->cccr); + type = (id >> 8) & 0xFF; + + return type; +} + +u32 rmobile_get_cpu_rev_integer(void) +{ + u32 id; + u32 rev; + struct sh73a0_hpb *hpb = (struct sh73a0_hpb *)HPB_BASE; + + id = readl(&hpb->cccr); + rev = ((id >> 4) & 0xF) + 1; + + return rev; +} + +u32 rmobile_get_cpu_rev_fraction(void) +{ + u32 id; + u32 rev; + struct sh73a0_hpb *hpb = (struct sh73a0_hpb *)HPB_BASE; + + id = readl(&hpb->cccr); + rev = id & 0xF; + + return rev; +} diff --git a/arch/arm/cpu/armv7/rmobile/cpu_info.c b/arch/arm/cpu/armv7/rmobile/cpu_info.c new file mode 100644 index 0000000000..0e2b82ec58 --- /dev/null +++ b/arch/arm/cpu/armv7/rmobile/cpu_info.c @@ -0,0 +1,85 @@ +/* + * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> + * (C) Copyright 2012 Renesas Solutions Corp. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <asm/io.h> + +#ifdef CONFIG_ARCH_CPU_INIT +int arch_cpu_init(void) +{ + icache_enable(); + return 0; +} +#endif + +#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches(void) +{ + dcache_enable(); +} +#endif + +#ifdef CONFIG_DISPLAY_CPUINFO +static u32 __rmobile_get_cpu_type(void) +{ + return 0x0; +} +u32 rmobile_get_cpu_type(void) + __attribute__((weak, alias("__rmobile_get_cpu_type"))); + +static u32 __rmobile_get_cpu_rev_integer(void) +{ + return 0; +} +u32 rmobile_get_cpu_rev_integer(void) + __attribute__((weak, alias("__rmobile_get_cpu_rev_integer"))); + +static u32 __rmobile_get_cpu_rev_fraction(void) +{ + return 0; +} +u32 rmobile_get_cpu_rev_fraction(void) + __attribute__((weak, alias("__rmobile_get_cpu_rev_fraction"))); + +int print_cpuinfo(void) +{ + switch (rmobile_get_cpu_type()) { + case 0x37: + printf("CPU: Renesas Electronics SH73A0 rev %d.%d\n", + rmobile_get_cpu_rev_integer(), + rmobile_get_cpu_rev_fraction()); + break; + case 0x40: + printf("CPU: Renesas Electronics R8A7740 rev %d.%d\n", + rmobile_get_cpu_rev_integer(), + rmobile_get_cpu_rev_fraction()); + break; + + default: + printf("CPU: Renesas Electronics CPU rev %d.%d\n", + rmobile_get_cpu_rev_integer(), + rmobile_get_cpu_rev_fraction()); + break; + } + return 0; +} +#endif /* CONFIG_DISPLAY_CPUINFO */ diff --git a/arch/arm/cpu/armv7/rmobile/emac.c b/arch/arm/cpu/armv7/rmobile/emac.c new file mode 100644 index 0000000000..da5269e328 --- /dev/null +++ b/arch/arm/cpu/armv7/rmobile/emac.c @@ -0,0 +1,36 @@ +/* + * RMOBILE EtherMAC initialization. + * + * Copyright (C) 2012 Renesas Solutions Corp. + * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <common.h> +#include <asm/errno.h> +#include <netdev.h> + +int cpu_eth_init(bd_t *bis) +{ + int ret = -ENODEV; +#ifdef CONFIG_SH_ETHER + ret = sh_eth_initialize(bis); +#endif + return ret; +} diff --git a/arch/arm/cpu/armv7/rmobile/lowlevel_init.S b/arch/arm/cpu/armv7/rmobile/lowlevel_init.S new file mode 100644 index 0000000000..1bd391e840 --- /dev/null +++ b/arch/arm/cpu/armv7/rmobile/lowlevel_init.S @@ -0,0 +1,98 @@ +/* + * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.Iwamatsu.yj@renesas.com> + * Copyright (C) 2012 Renesas Solutions Corp. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <linux/linkage.h> + +ENTRY(lowlevel_init) + ldr r0, =MERAM_BASE + mov r1, #0x0 + str r1, [r0] + + mrc p15, 0, r0, c0, c0, 5 + ands r0, r0, #0xF + beq lowlevel_init__ + b wait_interrupt + + .pool + .align 4 + +wait_interrupt: +#ifdef ICCICR + ldr r1, =ICCICR + mov r2, #0x0 + str r2, [r1] + mov r2, #0xF0 + adds r1, r1, #4 /* ICCPMR */ + str r2, [r1] + ldr r1, =ICCICR + mov r2, #0x1 + str r2, [r1] +#endif + +wait_loop: + .long 0xE320F003 /* wfi */ + + ldr r2, [r1, #0xC] + str r2, [r1, #0x10] + + ldr r0, =MERAM_BASE + ldr r2, [r0] + cmp r2, #0 + movne pc, r2 + + b wait_loop + +wait_loop_end: + .pool + .align 4 + +lowlevel_init__: + + mov r0, #0x200000 + +loop0: + subs r0, r0, #1 + bne loop0 + + ldr sp, MERAM_STACK + + str ip, [sp] /* stash old link register */ + mov ip, lr /* save link reg across call */ + + bl s_init + + ldr ip, [sp] /* restore save ip */ + mov lr, ip /* restore link reg */ + + /* back to arch calling code */ + mov pc, lr + + .pool + .align 4 + +ENDPROC(lowlevel_init) + .ltorg + +MERAM_STACK: + .word LOW_LEVEL_MERAM_STACK diff --git a/arch/arm/cpu/armv7/rmobile/pfc-r8a7740.c b/arch/arm/cpu/armv7/rmobile/pfc-r8a7740.c new file mode 100644 index 0000000000..5d42a68266 --- /dev/null +++ b/arch/arm/cpu/armv7/rmobile/pfc-r8a7740.c @@ -0,0 +1,2612 @@ +/* + * R8A7740 processor support + * + * Copyright (C) 2011 Renesas Solutions Corp. + * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the + * License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <common.h> +#include <sh_pfc.h> +#include <asm/gpio.h> +#include <asm/arch/irqs.h> + +#define CPU_ALL_PORT(fn, pfx, sfx) \ + PORT_10(fn, pfx, sfx), PORT_90(fn, pfx, sfx), \ + PORT_10(fn, pfx##10, sfx), PORT_90(fn, pfx##1, sfx), \ + PORT_10(fn, pfx##20, sfx), \ + PORT_1(fn, pfx##210, sfx), PORT_1(fn, pfx##211, sfx) + +enum { + PINMUX_RESERVED = 0, + + /* PORT0_DATA -> PORT211_DATA */ + PINMUX_DATA_BEGIN, + PORT_ALL(DATA), + PINMUX_DATA_END, + + /* PORT0_IN -> PORT211_IN */ + PINMUX_INPUT_BEGIN, + PORT_ALL(IN), + PINMUX_INPUT_END, + + /* PORT0_IN_PU -> PORT211_IN_PU */ + PINMUX_INPUT_PULLUP_BEGIN, + PORT_ALL(IN_PU), + PINMUX_INPUT_PULLUP_END, + + /* PORT0_IN_PD -> PORT211_IN_PD */ + PINMUX_INPUT_PULLDOWN_BEGIN, + PORT_ALL(IN_PD), + PINMUX_INPUT_PULLDOWN_END, + + /* PORT0_OUT -> PORT211_OUT */ + PINMUX_OUTPUT_BEGIN, + PORT_ALL(OUT), + PINMUX_OUTPUT_END, + + PINMUX_FUNCTION_BEGIN, + PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT211_FN_IN */ + PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT211_FN_OUT */ + PORT_ALL(FN0), /* PORT0_FN0 -> PORT211_FN0 */ + PORT_ALL(FN1), /* PORT0_FN1 -> PORT211_FN1 */ + PORT_ALL(FN2), /* PORT0_FN2 -> PORT211_FN2 */ + PORT_ALL(FN3), /* PORT0_FN3 -> PORT211_FN3 */ + PORT_ALL(FN4), /* PORT0_FN4 -> PORT211_FN4 */ + PORT_ALL(FN5), /* PORT0_FN5 -> PORT211_FN5 */ + PORT_ALL(FN6), /* PORT0_FN6 -> PORT211_FN6 */ + PORT_ALL(FN7), /* PORT0_FN7 -> PORT211_FN7 */ + + MSEL1CR_31_0, MSEL1CR_31_1, + MSEL1CR_30_0, MSEL1CR_30_1, + MSEL1CR_29_0, MSEL1CR_29_1, + MSEL1CR_28_0, MSEL1CR_28_1, + MSEL1CR_27_0, MSEL1CR_27_1, + MSEL1CR_26_0, MSEL1CR_26_1, + MSEL1CR_16_0, MSEL1CR_16_1, + MSEL1CR_15_0, MSEL1CR_15_1, + MSEL1CR_14_0, MSEL1CR_14_1, + MSEL1CR_13_0, MSEL1CR_13_1, + MSEL1CR_12_0, MSEL1CR_12_1, + MSEL1CR_9_0, MSEL1CR_9_1, + MSEL1CR_7_0, MSEL1CR_7_1, + MSEL1CR_6_0, MSEL1CR_6_1, + MSEL1CR_5_0, MSEL1CR_5_1, + MSEL1CR_4_0, MSEL1CR_4_1, + MSEL1CR_3_0, MSEL1CR_3_1, + MSEL1CR_2_0, MSEL1CR_2_1, + MSEL1CR_0_0, MSEL1CR_0_1, + + MSEL3CR_15_0, MSEL3CR_15_1, /* Trace / Debug ? */ + MSEL3CR_6_0, MSEL3CR_6_1, + + MSEL4CR_19_0, MSEL4CR_19_1, + MSEL4CR_18_0, MSEL4CR_18_1, + MSEL4CR_15_0, MSEL4CR_15_1, + MSEL4CR_10_0, MSEL4CR_10_1, + MSEL4CR_6_0, MSEL4CR_6_1, + MSEL4CR_4_0, MSEL4CR_4_1, + MSEL4CR_1_0, MSEL4CR_1_1, + + MSEL5CR_31_0, MSEL5CR_31_1, /* irq/fiq output */ + MSEL5CR_30_0, MSEL5CR_30_1, + MSEL5CR_29_0, MSEL5CR_29_1, + MSEL5CR_27_0, MSEL5CR_27_1, + MSEL5CR_25_0, MSEL5CR_25_1, + MSEL5CR_23_0, MSEL5CR_23_1, + MSEL5CR_21_0, MSEL5CR_21_1, + MSEL5CR_19_0, MSEL5CR_19_1, + MSEL5CR_17_0, MSEL5CR_17_1, + MSEL5CR_15_0, MSEL5CR_15_1, + MSEL5CR_14_0, MSEL5CR_14_1, + MSEL5CR_13_0, MSEL5CR_13_1, + MSEL5CR_12_0, MSEL5CR_12_1, + MSEL5CR_11_0, MSEL5CR_11_1, + MSEL5CR_10_0, MSEL5CR_10_1, + MSEL5CR_8_0, MSEL5CR_8_1, + MSEL5CR_7_0, MSEL5CR_7_1, + MSEL5CR_6_0, MSEL5CR_6_1, + MSEL5CR_5_0, MSEL5CR_5_1, + MSEL5CR_4_0, MSEL5CR_4_1, + MSEL5CR_3_0, MSEL5CR_3_1, + MSEL5CR_2_0, MSEL5CR_2_1, + MSEL5CR_0_0, MSEL5CR_0_1, + PINMUX_FUNCTION_END, + + PINMUX_MARK_BEGIN, + + /* IRQ */ + IRQ0_PORT2_MARK, IRQ0_PORT13_MARK, + IRQ1_MARK, + IRQ2_PORT11_MARK, IRQ2_PORT12_MARK, + IRQ3_PORT10_MARK, IRQ3_PORT14_MARK, + IRQ4_PORT15_MARK, IRQ4_PORT172_MARK, + IRQ5_PORT0_MARK, IRQ5_PORT1_MARK, + IRQ6_PORT121_MARK, IRQ6_PORT173_MARK, + IRQ7_PORT120_MARK, IRQ7_PORT209_MARK, + IRQ8_MARK, + IRQ9_PORT118_MARK, IRQ9_PORT210_MARK, + IRQ10_MARK, + IRQ11_MARK, + IRQ12_PORT42_MARK, IRQ12_PORT97_MARK, + IRQ13_PORT64_MARK, IRQ13_PORT98_MARK, + IRQ14_PORT63_MARK, IRQ14_PORT99_MARK, + IRQ15_PORT62_MARK, IRQ15_PORT100_MARK, + IRQ16_PORT68_MARK, IRQ16_PORT211_MARK, + IRQ17_MARK, + IRQ18_MARK, + IRQ19_MARK, + IRQ20_MARK, + IRQ21_MARK, + IRQ22_MARK, + IRQ23_MARK, + IRQ24_MARK, + IRQ25_MARK, + IRQ26_PORT58_MARK, IRQ26_PORT81_MARK, + IRQ27_PORT57_MARK, IRQ27_PORT168_MARK, + IRQ28_PORT56_MARK, IRQ28_PORT169_MARK, + IRQ29_PORT50_MARK, IRQ29_PORT170_MARK, + IRQ30_PORT49_MARK, IRQ30_PORT171_MARK, + IRQ31_PORT41_MARK, IRQ31_PORT167_MARK, + + /* Function */ + + /* DBGT */ + DBGMDT2_MARK, DBGMDT1_MARK, DBGMDT0_MARK, + DBGMD10_MARK, DBGMD11_MARK, DBGMD20_MARK, + DBGMD21_MARK, + + /* FSI */ + FSIAISLD_PORT0_MARK, /* FSIAISLD Port 0/5 */ + FSIAISLD_PORT5_MARK, + FSIASPDIF_PORT9_MARK, /* FSIASPDIF Port 9/18 */ + FSIASPDIF_PORT18_MARK, + FSIAOSLD1_MARK, FSIAOSLD2_MARK, FSIAOLR_MARK, + FSIAOBT_MARK, FSIAOSLD_MARK, FSIAOMC_MARK, + FSIACK_MARK, FSIAILR_MARK, FSIAIBT_MARK, + + /* FMSI */ + FMSISLD_PORT1_MARK, /* FMSISLD Port 1/6 */ + FMSISLD_PORT6_MARK, + FMSIILR_MARK, FMSIIBT_MARK, FMSIOLR_MARK, FMSIOBT_MARK, + FMSICK_MARK, FMSOILR_MARK, FMSOIBT_MARK, FMSOOLR_MARK, + FMSOOBT_MARK, FMSOSLD_MARK, FMSOCK_MARK, + + /* SCIFA0 */ + SCIFA0_SCK_MARK, SCIFA0_CTS_MARK, SCIFA0_RTS_MARK, + SCIFA0_RXD_MARK, SCIFA0_TXD_MARK, + + /* SCIFA1 */ + SCIFA1_CTS_MARK, SCIFA1_SCK_MARK, SCIFA1_RXD_MARK, + SCIFA1_TXD_MARK, SCIFA1_RTS_MARK, + + /* SCIFA2 */ + SCIFA2_SCK_PORT22_MARK, /* SCIFA2_SCK Port 22/199 */ + SCIFA2_SCK_PORT199_MARK, + SCIFA2_RXD_MARK, SCIFA2_TXD_MARK, + SCIFA2_CTS_MARK, SCIFA2_RTS_MARK, + + /* SCIFA3 */ + SCIFA3_RTS_PORT105_MARK, /* MSEL5CR_8_0 */ + SCIFA3_SCK_PORT116_MARK, + SCIFA3_CTS_PORT117_MARK, + SCIFA3_RXD_PORT174_MARK, + SCIFA3_TXD_PORT175_MARK, + + SCIFA3_RTS_PORT161_MARK, /* MSEL5CR_8_1 */ + SCIFA3_SCK_PORT158_MARK, + SCIFA3_CTS_PORT162_MARK, + SCIFA3_RXD_PORT159_MARK, + SCIFA3_TXD_PORT160_MARK, + + /* SCIFA4 */ + SCIFA4_RXD_PORT12_MARK, /* MSEL5CR[12:11] = 00 */ + SCIFA4_TXD_PORT13_MARK, + + SCIFA4_RXD_PORT204_MARK, /* MSEL5CR[12:11] = 01 */ + SCIFA4_TXD_PORT203_MARK, + + SCIFA4_RXD_PORT94_MARK, /* MSEL5CR[12:11] = 10 */ + SCIFA4_TXD_PORT93_MARK, + + SCIFA4_SCK_PORT21_MARK, /* SCIFA4_SCK Port 21/205 */ + SCIFA4_SCK_PORT205_MARK, + + /* SCIFA5 */ + SCIFA5_TXD_PORT20_MARK, /* MSEL5CR[15:14] = 00 */ + SCIFA5_RXD_PORT10_MARK, + + SCIFA5_RXD_PORT207_MARK, /* MSEL5CR[15:14] = 01 */ + SCIFA5_TXD_PORT208_MARK, + + SCIFA5_TXD_PORT91_MARK, /* MSEL5CR[15:14] = 10 */ + SCIFA5_RXD_PORT92_MARK, + + SCIFA5_SCK_PORT23_MARK, /* SCIFA5_SCK Port 23/206 */ + SCIFA5_SCK_PORT206_MARK, + + /* SCIFA6 */ + SCIFA6_SCK_MARK, SCIFA6_RXD_MARK, SCIFA6_TXD_MARK, + + /* SCIFA7 */ + SCIFA7_TXD_MARK, SCIFA7_RXD_MARK, + + /* SCIFAB */ + SCIFB_SCK_PORT190_MARK, /* MSEL5CR_17_0 */ + SCIFB_RXD_PORT191_MARK, + SCIFB_TXD_PORT192_MARK, + SCIFB_RTS_PORT186_MARK, + SCIFB_CTS_PORT187_MARK, + + SCIFB_SCK_PORT2_MARK, /* MSEL5CR_17_1 */ + SCIFB_RXD_PORT3_MARK, + SCIFB_TXD_PORT4_MARK, + SCIFB_RTS_PORT172_MARK, + SCIFB_CTS_PORT173_MARK, + + /* LCD0 */ + LCDC0_SELECT_MARK, + + LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK, + LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK, + LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK, + LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK, + LCD0_D16_MARK, LCD0_D17_MARK, + LCD0_DON_MARK, LCD0_VCPWC_MARK, LCD0_VEPWC_MARK, + LCD0_DCK_MARK, LCD0_VSYN_MARK, /* for RGB */ + LCD0_HSYN_MARK, LCD0_DISP_MARK, /* for RGB */ + LCD0_WR_MARK, LCD0_RD_MARK, /* for SYS */ + LCD0_CS_MARK, LCD0_RS_MARK, /* for SYS */ + + LCD0_D21_PORT158_MARK, LCD0_D23_PORT159_MARK, /* MSEL5CR_6_1 */ + LCD0_D22_PORT160_MARK, LCD0_D20_PORT161_MARK, + LCD0_D19_PORT162_MARK, LCD0_D18_PORT163_MARK, + LCD0_LCLK_PORT165_MARK, + + LCD0_D18_PORT40_MARK, LCD0_D22_PORT0_MARK, /* MSEL5CR_6_0 */ + LCD0_D23_PORT1_MARK, LCD0_D21_PORT2_MARK, + LCD0_D20_PORT3_MARK, LCD0_D19_PORT4_MARK, + LCD0_LCLK_PORT102_MARK, + + /* LCD1 */ + LCDC1_SELECT_MARK, + + LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK, + LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK, + LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK, + LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK, + LCD1_D16_MARK, LCD1_D17_MARK, LCD1_D18_MARK, LCD1_D19_MARK, + LCD1_D20_MARK, LCD1_D21_MARK, LCD1_D22_MARK, LCD1_D23_MARK, + LCD1_DON_MARK, LCD1_VCPWC_MARK, + LCD1_LCLK_MARK, LCD1_VEPWC_MARK, + + LCD1_DCK_MARK, LCD1_VSYN_MARK, /* for RGB */ + LCD1_HSYN_MARK, LCD1_DISP_MARK, /* for RGB */ + LCD1_RS_MARK, LCD1_CS_MARK, /* for SYS */ + LCD1_RD_MARK, LCD1_WR_MARK, /* for SYS */ + + /* RSPI */ + RSPI_SSL0_A_MARK, RSPI_SSL1_A_MARK, RSPI_SSL2_A_MARK, + RSPI_SSL3_A_MARK, RSPI_CK_A_MARK, RSPI_MOSI_A_MARK, + RSPI_MISO_A_MARK, + + /* VIO CKO */ + VIO_CKO1_MARK, /* needs fixup */ + VIO_CKO2_MARK, + VIO_CKO_1_MARK, + VIO_CKO_MARK, + + /* VIO0 */ + VIO0_D0_MARK, VIO0_D1_MARK, VIO0_D2_MARK, VIO0_D3_MARK, + VIO0_D4_MARK, VIO0_D5_MARK, VIO0_D6_MARK, VIO0_D7_MARK, + VIO0_D8_MARK, VIO0_D9_MARK, VIO0_D10_MARK, VIO0_D11_MARK, + VIO0_D12_MARK, VIO0_VD_MARK, VIO0_HD_MARK, VIO0_CLK_MARK, + VIO0_FIELD_MARK, + + VIO0_D13_PORT26_MARK, /* MSEL5CR_27_0 */ + VIO0_D14_PORT25_MARK, + VIO0_D15_PORT24_MARK, + + VIO0_D13_PORT22_MARK, /* MSEL5CR_27_1 */ + VIO0_D14_PORT95_MARK, + VIO0_D15_PORT96_MARK, + + /* VIO1 */ + VIO1_D0_MARK, VIO1_D1_MARK, VIO1_D2_MARK, VIO1_D3_MARK, + VIO1_D4_MARK, VIO1_D5_MARK, VIO1_D6_MARK, VIO1_D7_MARK, + VIO1_VD_MARK, VIO1_HD_MARK, VIO1_CLK_MARK, VIO1_FIELD_MARK, + + /* TPU0 */ + TPU0TO0_MARK, TPU0TO1_MARK, TPU0TO3_MARK, + TPU0TO2_PORT66_MARK, /* TPU0TO2 Port 66/202 */ + TPU0TO2_PORT202_MARK, + + /* SSP1 0 */ + STP0_IPD0_MARK, STP0_IPD1_MARK, STP0_IPD2_MARK, STP0_IPD3_MARK, + STP0_IPD4_MARK, STP0_IPD5_MARK, STP0_IPD6_MARK, STP0_IPD7_MARK, + STP0_IPEN_MARK, STP0_IPCLK_MARK, STP0_IPSYNC_MARK, + + /* SSP1 1 */ + STP1_IPD1_MARK, STP1_IPD2_MARK, STP1_IPD3_MARK, STP1_IPD4_MARK, + STP1_IPD5_MARK, STP1_IPD6_MARK, STP1_IPD7_MARK, STP1_IPCLK_MARK, + STP1_IPSYNC_MARK, + + STP1_IPD0_PORT186_MARK, /* MSEL5CR_23_0 */ + STP1_IPEN_PORT187_MARK, + + STP1_IPD0_PORT194_MARK, /* MSEL5CR_23_1 */ + STP1_IPEN_PORT193_MARK, + + /* SIM */ + SIM_RST_MARK, SIM_CLK_MARK, + SIM_D_PORT22_MARK, /* SIM_D Port 22/199 */ + SIM_D_PORT199_MARK, + + /* SDHI0 */ + SDHI0_D0_MARK, SDHI0_D1_MARK, SDHI0_D2_MARK, SDHI0_D3_MARK, + SDHI0_CD_MARK, SDHI0_WP_MARK, SDHI0_CMD_MARK, SDHI0_CLK_MARK, + + /* SDHI1 */ + SDHI1_D0_MARK, SDHI1_D1_MARK, SDHI1_D2_MARK, SDHI1_D3_MARK, + SDHI1_CD_MARK, SDHI1_WP_MARK, SDHI1_CMD_MARK, SDHI1_CLK_MARK, + + /* SDHI2 */ + SDHI2_D0_MARK, SDHI2_D1_MARK, SDHI2_D2_MARK, SDHI2_D3_MARK, + SDHI2_CLK_MARK, SDHI2_CMD_MARK, + + SDHI2_CD_PORT24_MARK, /* MSEL5CR_19_0 */ + SDHI2_WP_PORT25_MARK, + + SDHI2_WP_PORT177_MARK, /* MSEL5CR_19_1 */ + SDHI2_CD_PORT202_MARK, + + /* MSIOF2 */ + MSIOF2_TXD_MARK, MSIOF2_RXD_MARK, MSIOF2_TSCK_MARK, + MSIOF2_SS2_MARK, MSIOF2_TSYNC_MARK, MSIOF2_SS1_MARK, + MSIOF2_MCK1_MARK, MSIOF2_MCK0_MARK, MSIOF2_RSYNC_MARK, + MSIOF2_RSCK_MARK, + + /* KEYSC */ + KEYIN4_MARK, KEYIN5_MARK, KEYIN6_MARK, KEYIN7_MARK, + KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK, + KEYOUT4_MARK, KEYOUT5_MARK, KEYOUT6_MARK, KEYOUT7_MARK, + + KEYIN0_PORT43_MARK, /* MSEL4CR_18_0 */ + KEYIN1_PORT44_MARK, + KEYIN2_PORT45_MARK, + KEYIN3_PORT46_MARK, + + KEYIN0_PORT58_MARK, /* MSEL4CR_18_1 */ + KEYIN1_PORT57_MARK, + KEYIN2_PORT56_MARK, + KEYIN3_PORT55_MARK, + + /* VOU */ + DV_D0_MARK, DV_D1_MARK, DV_D2_MARK, DV_D3_MARK, + DV_D4_MARK, DV_D5_MARK, DV_D6_MARK, DV_D7_MARK, + DV_D8_MARK, DV_D9_MARK, DV_D10_MARK, DV_D11_MARK, + DV_D12_MARK, DV_D13_MARK, DV_D14_MARK, DV_D15_MARK, + DV_CLK_MARK, DV_VSYNC_MARK, DV_HSYNC_MARK, + + /* MEMC */ + MEMC_AD0_MARK, MEMC_AD1_MARK, MEMC_AD2_MARK, MEMC_AD3_MARK, + MEMC_AD4_MARK, MEMC_AD5_MARK, MEMC_AD6_MARK, MEMC_AD7_MARK, + MEMC_AD8_MARK, MEMC_AD9_MARK, MEMC_AD10_MARK, MEMC_AD11_MARK, + MEMC_AD12_MARK, MEMC_AD13_MARK, MEMC_AD14_MARK, MEMC_AD15_MARK, + MEMC_CS0_MARK, MEMC_INT_MARK, MEMC_NWE_MARK, MEMC_NOE_MARK, + + MEMC_CS1_MARK, /* MSEL4CR_6_0 */ + MEMC_ADV_MARK, + MEMC_WAIT_MARK, + MEMC_BUSCLK_MARK, + + MEMC_A1_MARK, /* MSEL4CR_6_1 */ + MEMC_DREQ0_MARK, + MEMC_DREQ1_MARK, + MEMC_A0_MARK, + + /* MMC */ + MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK, + MMC0_D3_PORT71_MARK, MMC0_D4_PORT72_MARK, MMC0_D5_PORT73_MARK, + MMC0_D6_PORT74_MARK, MMC0_D7_PORT75_MARK, MMC0_CLK_PORT66_MARK, + MMC0_CMD_PORT67_MARK, /* MSEL4CR_15_0 */ + + MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK, + MMC1_D3_PORT146_MARK, MMC1_D4_PORT145_MARK, MMC1_D5_PORT144_MARK, + MMC1_D6_PORT143_MARK, MMC1_D7_PORT142_MARK, MMC1_CLK_PORT103_MARK, + MMC1_CMD_PORT104_MARK, /* MSEL4CR_15_1 */ + + /* MSIOF0 */ + MSIOF0_SS1_MARK, MSIOF0_SS2_MARK, MSIOF0_RXD_MARK, + MSIOF0_TXD_MARK, MSIOF0_MCK0_MARK, MSIOF0_MCK1_MARK, + MSIOF0_RSYNC_MARK, MSIOF0_RSCK_MARK, MSIOF0_TSCK_MARK, + MSIOF0_TSYNC_MARK, + + /* MSIOF1 */ + MSIOF1_RSCK_MARK, MSIOF1_RSYNC_MARK, + MSIOF1_MCK0_MARK, MSIOF1_MCK1_MARK, + + MSIOF1_SS2_PORT116_MARK, MSIOF1_SS1_PORT117_MARK, + MSIOF1_RXD_PORT118_MARK, MSIOF1_TXD_PORT119_MARK, + MSIOF1_TSYNC_PORT120_MARK, + MSIOF1_TSCK_PORT121_MARK, /* MSEL4CR_10_0 */ + + MSIOF1_SS1_PORT67_MARK, MSIOF1_TSCK_PORT72_MARK, + MSIOF1_TSYNC_PORT73_MARK, MSIOF1_TXD_PORT74_MARK, + MSIOF1_RXD_PORT75_MARK, + MSIOF1_SS2_PORT202_MARK, /* MSEL4CR_10_1 */ + + /* GPIO */ + GPO0_MARK, GPI0_MARK, GPO1_MARK, GPI1_MARK, + + /* USB0 */ + USB0_OCI_MARK, USB0_PPON_MARK, VBUS_MARK, + + /* USB1 */ + USB1_OCI_MARK, USB1_PPON_MARK, + + /* BBIF1 */ + BBIF1_RXD_MARK, BBIF1_TXD_MARK, BBIF1_TSYNC_MARK, + BBIF1_TSCK_MARK, BBIF1_RSCK_MARK, BBIF1_RSYNC_MARK, + BBIF1_FLOW_MARK, BBIF1_RX_FLOW_N_MARK, + + /* BBIF2 */ + BBIF2_TXD2_PORT5_MARK, /* MSEL5CR_0_0 */ + BBIF2_RXD2_PORT60_MARK, + BBIF2_TSYNC2_PORT6_MARK, + BBIF2_TSCK2_PORT59_MARK, + + BBIF2_RXD2_PORT90_MARK, /* MSEL5CR_0_1 */ + BBIF2_TXD2_PORT183_MARK, + BBIF2_TSCK2_PORT89_MARK, + BBIF2_TSYNC2_PORT184_MARK, + + /* BSC / FLCTL / PCMCIA */ + CS0_MARK, CS2_MARK, CS4_MARK, + CS5B_MARK, CS6A_MARK, + CS5A_PORT105_MARK, /* CS5A PORT 19/105 */ + CS5A_PORT19_MARK, + IOIS16_MARK, /* ? */ + + A0_MARK, A1_MARK, A2_MARK, A3_MARK, + A4_FOE_MARK, /* share with FLCTL */ + A5_FCDE_MARK, /* share with FLCTL */ + A6_MARK, A7_MARK, A8_MARK, A9_MARK, + A10_MARK, A11_MARK, A12_MARK, A13_MARK, + A14_MARK, A15_MARK, A16_MARK, A17_MARK, + A18_MARK, A19_MARK, A20_MARK, A21_MARK, + A22_MARK, A23_MARK, A24_MARK, A25_MARK, + A26_MARK, + + D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, /* share with FLCTL */ + D3_NAF3_MARK, D4_NAF4_MARK, D5_NAF5_MARK, /* share with FLCTL */ + D6_NAF6_MARK, D7_NAF7_MARK, D8_NAF8_MARK, /* share with FLCTL */ + D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK, /* share with FLCTL */ + D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, /* share with FLCTL */ + D15_NAF15_MARK, /* share with FLCTL */ + D16_MARK, D17_MARK, D18_MARK, D19_MARK, + D20_MARK, D21_MARK, D22_MARK, D23_MARK, + D24_MARK, D25_MARK, D26_MARK, D27_MARK, + D28_MARK, D29_MARK, D30_MARK, D31_MARK, + + WE0_FWE_MARK, /* share with FLCTL */ + WE1_MARK, + WE2_ICIORD_MARK, /* share with PCMCIA */ + WE3_ICIOWR_MARK, /* share with PCMCIA */ + CKO_MARK, BS_MARK, RDWR_MARK, + RD_FSC_MARK, /* share with FLCTL */ + WAIT_PORT177_MARK, /* WAIT Port 90/177 */ + WAIT_PORT90_MARK, + + FCE0_MARK, FCE1_MARK, FRB_MARK, /* FLCTL */ + + /* IRDA */ + IRDA_FIRSEL_MARK, IRDA_IN_MARK, IRDA_OUT_MARK, + + /* ATAPI */ + IDE_D0_MARK, IDE_D1_MARK, IDE_D2_MARK, IDE_D3_MARK, + IDE_D4_MARK, IDE_D5_MARK, IDE_D6_MARK, IDE_D7_MARK, + IDE_D8_MARK, IDE_D9_MARK, IDE_D10_MARK, IDE_D11_MARK, + IDE_D12_MARK, IDE_D13_MARK, IDE_D14_MARK, IDE_D15_MARK, + IDE_A0_MARK, IDE_A1_MARK, IDE_A2_MARK, IDE_CS0_MARK, + IDE_CS1_MARK, IDE_IOWR_MARK, IDE_IORD_MARK, IDE_IORDY_MARK, + IDE_INT_MARK, IDE_RST_MARK, IDE_DIRECTION_MARK, + IDE_EXBUF_ENB_MARK, IDE_IODACK_MARK, IDE_IODREQ_MARK, + + /* RMII */ + RMII_CRS_DV_MARK, RMII_RX_ER_MARK, RMII_RXD0_MARK, + RMII_RXD1_MARK, RMII_TX_EN_MARK, RMII_TXD0_MARK, + RMII_MDC_MARK, RMII_TXD1_MARK, RMII_MDIO_MARK, + RMII_REF50CK_MARK, /* for RMII */ + RMII_REF125CK_MARK, /* for GMII */ + + /* GEther */ + ET_TX_CLK_MARK, ET_TX_EN_MARK, ET_ETXD0_MARK, ET_ETXD1_MARK, + ET_ETXD2_MARK, ET_ETXD3_MARK, + ET_ETXD4_MARK, ET_ETXD5_MARK, /* for GEther */ + ET_ETXD6_MARK, ET_ETXD7_MARK, /* for GEther */ + ET_COL_MARK, ET_TX_ER_MARK, ET_RX_CLK_MARK, ET_RX_DV_MARK, + ET_ERXD0_MARK, ET_ERXD1_MARK, ET_ERXD2_MARK, ET_ERXD3_MARK, + ET_ERXD4_MARK, ET_ERXD5_MARK, /* for GEther */ + ET_ERXD6_MARK, ET_ERXD7_MARK, /* for GEther */ + ET_RX_ER_MARK, ET_CRS_MARK, ET_MDC_MARK, ET_MDIO_MARK, + ET_LINK_MARK, ET_PHY_INT_MARK, ET_WOL_MARK, ET_GTX_CLK_MARK, + + /* DMA0 */ + DREQ0_MARK, DACK0_MARK, + + /* DMA1 */ + DREQ1_MARK, DACK1_MARK, + + /* SYSC */ + RESETOUTS_MARK, RESETP_PULLUP_MARK, RESETP_PLAIN_MARK, + + /* IRREM */ + IROUT_MARK, + + /* SDENC */ + SDENC_CPG_MARK, SDENC_DV_CLKI_MARK, + + /* DEBUG */ + EDEBGREQ_PULLUP_MARK, /* for JTAG */ + EDEBGREQ_PULLDOWN_MARK, + + TRACEAUD_FROM_VIO_MARK, /* for TRACE/AUD */ + TRACEAUD_FROM_LCDC0_MARK, + TRACEAUD_FROM_MEMC_MARK, + + PINMUX_MARK_END, +}; + +static unsigned short pinmux_data[] = { + /* specify valid pin states for each pin in GPIO mode */ + + /* I/O and Pull U/D */ + PORT_DATA_IO_PD(0), PORT_DATA_IO_PD(1), + PORT_DATA_IO_PD(2), PORT_DATA_IO_PD(3), + PORT_DATA_IO_PD(4), PORT_DATA_IO_PD(5), + PORT_DATA_IO_PD(6), PORT_DATA_IO(7), + PORT_DATA_IO(8), PORT_DATA_IO(9), + + PORT_DATA_IO_PD(10), PORT_DATA_IO_PD(11), + PORT_DATA_IO_PD(12), PORT_DATA_IO_PU_PD(13), + PORT_DATA_IO_PD(14), PORT_DATA_IO_PD(15), + PORT_DATA_IO_PD(16), PORT_DATA_IO_PD(17), + PORT_DATA_IO(18), PORT_DATA_IO_PU(19), + + PORT_DATA_IO_PU_PD(20), PORT_DATA_IO_PD(21), + PORT_DATA_IO_PU_PD(22), PORT_DATA_IO(23), + PORT_DATA_IO_PU(24), PORT_DATA_IO_PU(25), + PORT_DATA_IO_PU(26), PORT_DATA_IO_PU(27), + PORT_DATA_IO_PU(28), PORT_DATA_IO_PU(29), + + PORT_DATA_IO_PU(30), PORT_DATA_IO_PD(31), + PORT_DATA_IO_PD(32), PORT_DATA_IO_PD(33), + PORT_DATA_IO_PD(34), PORT_DATA_IO_PU(35), + PORT_DATA_IO_PU(36), PORT_DATA_IO_PD(37), + PORT_DATA_IO_PU(38), PORT_DATA_IO_PD(39), + + PORT_DATA_IO_PU_PD(40), PORT_DATA_IO_PD(41), + PORT_DATA_IO_PD(42), PORT_DATA_IO_PU_PD(43), + PORT_DATA_IO_PU_PD(44), PORT_DATA_IO_PU_PD(45), + PORT_DATA_IO_PU_PD(46), PORT_DATA_IO_PU_PD(47), + PORT_DATA_IO_PU_PD(48), PORT_DATA_IO_PU_PD(49), + + PORT_DATA_IO_PU_PD(50), PORT_DATA_IO_PD(51), + PORT_DATA_IO_PD(52), PORT_DATA_IO_PD(53), + PORT_DATA_IO_PD(54), PORT_DATA_IO_PU_PD(55), + PORT_DATA_IO_PU_PD(56), PORT_DATA_IO_PU_PD(57), + PORT_DATA_IO_PU_PD(58), PORT_DATA_IO_PU_PD(59), + + PORT_DATA_IO_PU_PD(60), PORT_DATA_IO_PD(61), + PORT_DATA_IO_PD(62), PORT_DATA_IO_PD(63), + PORT_DATA_IO_PD(64), PORT_DATA_IO_PD(65), + PORT_DATA_IO_PU_PD(66), PORT_DATA_IO_PU_PD(67), + PORT_DATA_IO_PU_PD(68), PORT_DATA_IO_PU_PD(69), + + PORT_DATA_IO_PU_PD(70), PORT_DATA_IO_PU_PD(71), + PORT_DATA_IO_PU_PD(72), PORT_DATA_IO_PU_PD(73), + PORT_DATA_IO_PU_PD(74), PORT_DATA_IO_PU_PD(75), + PORT_DATA_IO_PU_PD(76), PORT_DATA_IO_PU_PD(77), + PORT_DATA_IO_PU_PD(78), PORT_DATA_IO_PU_PD(79), + + PORT_DATA_IO_PU_PD(80), PORT_DATA_IO_PU_PD(81), + PORT_DATA_IO(82), PORT_DATA_IO_PU_PD(83), + PORT_DATA_IO(84), PORT_DATA_IO_PD(85), + PORT_DATA_IO_PD(86), PORT_DATA_IO_PD(87), + PORT_DATA_IO_PD(88), PORT_DATA_IO_PD(89), + + PORT_DATA_IO_PD(90), PORT_DATA_IO_PU_PD(91), + PORT_DATA_IO_PU_PD(92), PORT_DATA_IO_PU_PD(93), + PORT_DATA_IO_PU_PD(94), PORT_DATA_IO_PU_PD(95), + PORT_DATA_IO_PU_PD(96), PORT_DATA_IO_PU_PD(97), + PORT_DATA_IO_PU_PD(98), PORT_DATA_IO_PU_PD(99), + + PORT_DATA_IO_PU_PD(100), PORT_DATA_IO(101), + PORT_DATA_IO_PU(102), PORT_DATA_IO_PU_PD(103), + PORT_DATA_IO_PU(104), PORT_DATA_IO_PU(105), + PORT_DATA_IO_PU_PD(106), PORT_DATA_IO(107), + PORT_DATA_IO(108), PORT_DATA_IO(109), + + PORT_DATA_IO(110), PORT_DATA_IO(111), + PORT_DATA_IO(112), PORT_DATA_IO(113), + PORT_DATA_IO_PU_PD(114), PORT_DATA_IO(115), + PORT_DATA_IO_PD(116), PORT_DATA_IO_PD(117), + PORT_DATA_IO_PD(118), PORT_DATA_IO_PD(119), + + PORT_DATA_IO_PD(120), PORT_DATA_IO_PD(121), + PORT_DATA_IO_PD(122), PORT_DATA_IO_PD(123), + PORT_DATA_IO_PD(124), PORT_DATA_IO(125), + PORT_DATA_IO(126), PORT_DATA_IO(127), + PORT_DATA_IO(128), PORT_DATA_IO(129), + + PORT_DATA_IO(130), PORT_DATA_IO(131), + PORT_DATA_IO(132), PORT_DATA_IO(133), + PORT_DATA_IO(134), PORT_DATA_IO(135), + PORT_DATA_IO(136), PORT_DATA_IO(137), + PORT_DATA_IO(138), PORT_DATA_IO(139), + + PORT_DATA_IO(140), PORT_DATA_IO(141), + PORT_DATA_IO_PU(142), PORT_DATA_IO_PU(143), + PORT_DATA_IO_PU(144), PORT_DATA_IO_PU(145), + PORT_DATA_IO_PU(146), PORT_DATA_IO_PU(147), + PORT_DATA_IO_PU(148), PORT_DATA_IO_PU(149), + + PORT_DATA_IO_PU(150), PORT_DATA_IO_PU(151), + PORT_DATA_IO_PU(152), PORT_DATA_IO_PU(153), + PORT_DATA_IO_PU(154), PORT_DATA_IO_PU(155), + PORT_DATA_IO_PU(156), PORT_DATA_IO_PU(157), + PORT_DATA_IO_PD(158), PORT_DATA_IO_PD(159), + + PORT_DATA_IO_PU_PD(160), PORT_DATA_IO_PD(161), + PORT_DATA_IO_PD(162), PORT_DATA_IO_PD(163), + PORT_DATA_IO_PD(164), PORT_DATA_IO_PD(165), + PORT_DATA_IO_PU(166), PORT_DATA_IO_PU(167), + PORT_DATA_IO_PU(168), PORT_DATA_IO_PU(169), + + PORT_DATA_IO_PU(170), PORT_DATA_IO_PU(171), + PORT_DATA_IO_PD(172), PORT_DATA_IO_PD(173), + PORT_DATA_IO_PD(174), PORT_DATA_IO_PD(175), + PORT_DATA_IO_PU(176), PORT_DATA_IO_PU_PD(177), + PORT_DATA_IO_PU(178), PORT_DATA_IO_PD(179), + + PORT_DATA_IO_PD(180), PORT_DATA_IO_PU(181), + PORT_DATA_IO_PU(182), PORT_DATA_IO(183), + PORT_DATA_IO_PD(184), PORT_DATA_IO_PD(185), + PORT_DATA_IO_PD(186), PORT_DATA_IO_PD(187), + PORT_DATA_IO_PD(188), PORT_DATA_IO_PD(189), + + PORT_DATA_IO_PD(190), PORT_DATA_IO_PD(191), + PORT_DATA_IO_PD(192), PORT_DATA_IO_PU_PD(193), + PORT_DATA_IO_PU_PD(194), PORT_DATA_IO_PD(195), + PORT_DATA_IO_PU_PD(196), PORT_DATA_IO_PD(197), + PORT_DATA_IO_PU_PD(198), PORT_DATA_IO_PU_PD(199), + + PORT_DATA_IO_PU_PD(200), PORT_DATA_IO_PU(201), + PORT_DATA_IO_PU_PD(202), PORT_DATA_IO(203), + PORT_DATA_IO_PU_PD(204), PORT_DATA_IO_PU_PD(205), + PORT_DATA_IO_PU_PD(206), PORT_DATA_IO_PU_PD(207), + PORT_DATA_IO_PU_PD(208), PORT_DATA_IO_PD(209), + + PORT_DATA_IO_PD(210), PORT_DATA_IO_PD(211), + + /* Port0 */ + PINMUX_DATA(DBGMDT2_MARK, PORT0_FN1), + PINMUX_DATA(FSIAISLD_PORT0_MARK, PORT0_FN2, MSEL5CR_3_0), + PINMUX_DATA(FSIAOSLD1_MARK, PORT0_FN3), + PINMUX_DATA(LCD0_D22_PORT0_MARK, PORT0_FN4, MSEL5CR_6_0), + PINMUX_DATA(SCIFA7_RXD_MARK, PORT0_FN6), + PINMUX_DATA(LCD1_D4_MARK, PORT0_FN7), + PINMUX_DATA(IRQ5_PORT0_MARK, PORT0_FN0, MSEL1CR_5_0), + + /* Port1 */ + PINMUX_DATA(DBGMDT1_MARK, PORT1_FN1), + PINMUX_DATA(FMSISLD_PORT1_MARK, PORT1_FN2, MSEL5CR_5_0), + PINMUX_DATA(FSIAOSLD2_MARK, PORT1_FN3), + PINMUX_DATA(LCD0_D23_PORT1_MARK, PORT1_FN4, MSEL5CR_6_0), + PINMUX_DATA(SCIFA7_TXD_MARK, PORT1_FN6), + PINMUX_DATA(LCD1_D3_MARK, PORT1_FN7), + PINMUX_DATA(IRQ5_PORT1_MARK, PORT1_FN0, MSEL1CR_5_1), + + /* Port2 */ + PINMUX_DATA(DBGMDT0_MARK, PORT2_FN1), + PINMUX_DATA(SCIFB_SCK_PORT2_MARK, PORT2_FN2, MSEL5CR_17_1), + PINMUX_DATA(LCD0_D21_PORT2_MARK, PORT2_FN4, MSEL5CR_6_0), + PINMUX_DATA(LCD1_D2_MARK, PORT2_FN7), + PINMUX_DATA(IRQ0_PORT2_MARK, PORT2_FN0, MSEL1CR_0_1), + + /* Port3 */ + PINMUX_DATA(DBGMD21_MARK, PORT3_FN1), + PINMUX_DATA(SCIFB_RXD_PORT3_MARK, PORT3_FN2, MSEL5CR_17_1), + PINMUX_DATA(LCD0_D20_PORT3_MARK, PORT3_FN4, MSEL5CR_6_0), + PINMUX_DATA(LCD1_D1_MARK, PORT3_FN7), + + /* Port4 */ + PINMUX_DATA(DBGMD20_MARK, PORT4_FN1), + PINMUX_DATA(SCIFB_TXD_PORT4_MARK, PORT4_FN2, MSEL5CR_17_1), + PINMUX_DATA(LCD0_D19_PORT4_MARK, PORT4_FN4, MSEL5CR_6_0), + PINMUX_DATA(LCD1_D0_MARK, PORT4_FN7), + + /* Port5 */ + PINMUX_DATA(DBGMD11_MARK, PORT5_FN1), + PINMUX_DATA(BBIF2_TXD2_PORT5_MARK, PORT5_FN2, MSEL5CR_0_0), + PINMUX_DATA(FSIAISLD_PORT5_MARK, PORT5_FN4, MSEL5CR_3_1), + PINMUX_DATA(RSPI_SSL0_A_MARK, PORT5_FN6), + PINMUX_DATA(LCD1_VCPWC_MARK, PORT5_FN7), + + /* Port6 */ + PINMUX_DATA(DBGMD10_MARK, PORT6_FN1), + PINMUX_DATA(BBIF2_TSYNC2_PORT6_MARK, PORT6_FN2, MSEL5CR_0_0), + PINMUX_DATA(FMSISLD_PORT6_MARK, PORT6_FN4, MSEL5CR_5_1), + PINMUX_DATA(RSPI_SSL1_A_MARK, PORT6_FN6), + PINMUX_DATA(LCD1_VEPWC_MARK, PORT6_FN7), + + /* Port7 */ + PINMUX_DATA(FSIAOLR_MARK, PORT7_FN1), + + /* Port8 */ + PINMUX_DATA(FSIAOBT_MARK, PORT8_FN1), + + /* Port9 */ + PINMUX_DATA(FSIAOSLD_MARK, PORT9_FN1), + PINMUX_DATA(FSIASPDIF_PORT9_MARK, PORT9_FN2, MSEL5CR_4_0), + + /* Port10 */ + PINMUX_DATA(FSIAOMC_MARK, PORT10_FN1), + PINMUX_DATA(SCIFA5_RXD_PORT10_MARK, PORT10_FN3, MSEL5CR_14_0, + MSEL5CR_15_0), + PINMUX_DATA(IRQ3_PORT10_MARK, PORT10_FN0, MSEL1CR_3_0), + + /* Port11 */ + PINMUX_DATA(FSIACK_MARK, PORT11_FN1), + PINMUX_DATA(IRQ2_PORT11_MARK, PORT11_FN0, MSEL1CR_2_0), + + /* Port12 */ + PINMUX_DATA(FSIAILR_MARK, PORT12_FN1), + PINMUX_DATA(SCIFA4_RXD_PORT12_MARK, PORT12_FN2, MSEL5CR_12_0, + MSEL5CR_11_0), + PINMUX_DATA(LCD1_RS_MARK, PORT12_FN6), + PINMUX_DATA(LCD1_DISP_MARK, PORT12_FN7), + PINMUX_DATA(IRQ2_PORT12_MARK, PORT12_FN0, MSEL1CR_2_1), + + /* Port13 */ + PINMUX_DATA(FSIAIBT_MARK, PORT13_FN1), + PINMUX_DATA(SCIFA4_TXD_PORT13_MARK, PORT13_FN2, MSEL5CR_12_0, + MSEL5CR_11_0), + PINMUX_DATA(LCD1_RD_MARK, PORT13_FN7), + PINMUX_DATA(IRQ0_PORT13_MARK, PORT13_FN0, MSEL1CR_0_0), + + /* Port14 */ + PINMUX_DATA(FMSOILR_MARK, PORT14_FN1), + PINMUX_DATA(FMSIILR_MARK, PORT14_FN2), + PINMUX_DATA(VIO_CKO1_MARK, PORT14_FN3), + PINMUX_DATA(LCD1_D23_MARK, PORT14_FN7), + PINMUX_DATA(IRQ3_PORT14_MARK, PORT14_FN0, MSEL1CR_3_1), + + /* Port15 */ + PINMUX_DATA(FMSOIBT_MARK, PORT15_FN1), + PINMUX_DATA(FMSIIBT_MARK, PORT15_FN2), + PINMUX_DATA(VIO_CKO2_MARK, PORT15_FN3), + PINMUX_DATA(LCD1_D22_MARK, PORT15_FN7), + PINMUX_DATA(IRQ4_PORT15_MARK, PORT15_FN0, MSEL1CR_4_0), + + /* Port16 */ + PINMUX_DATA(FMSOOLR_MARK, PORT16_FN1), + PINMUX_DATA(FMSIOLR_MARK, PORT16_FN2), + + /* Port17 */ + PINMUX_DATA(FMSOOBT_MARK, PORT17_FN1), + PINMUX_DATA(FMSIOBT_MARK, PORT17_FN2), + + /* Port18 */ + PINMUX_DATA(FMSOSLD_MARK, PORT18_FN1), + PINMUX_DATA(FSIASPDIF_PORT18_MARK, PORT18_FN2, MSEL5CR_4_1), + + /* Port19 */ + PINMUX_DATA(FMSICK_MARK, PORT19_FN1), + PINMUX_DATA(CS5A_PORT19_MARK, PORT19_FN7, MSEL5CR_2_1), + PINMUX_DATA(IRQ10_MARK, PORT19_FN0), + + /* Port20 */ + PINMUX_DATA(FMSOCK_MARK, PORT20_FN1), + PINMUX_DATA(SCIFA5_TXD_PORT20_MARK, PORT20_FN3, MSEL5CR_15_0, + MSEL5CR_14_0), + PINMUX_DATA(IRQ1_MARK, PORT20_FN0), + + /* Port21 */ + PINMUX_DATA(SCIFA1_CTS_MARK, PORT21_FN1), + PINMUX_DATA(SCIFA4_SCK_PORT21_MARK, PORT21_FN2, MSEL5CR_10_0), + PINMUX_DATA(TPU0TO1_MARK, PORT21_FN4), + PINMUX_DATA(VIO1_FIELD_MARK, PORT21_FN5), + PINMUX_DATA(STP0_IPD5_MARK, PORT21_FN6), + PINMUX_DATA(LCD1_D10_MARK, PORT21_FN7), + + /* Port22 */ + PINMUX_DATA(SCIFA2_SCK_PORT22_MARK, PORT22_FN1, MSEL5CR_7_0), + PINMUX_DATA(SIM_D_PORT22_MARK, PORT22_FN4, MSEL5CR_21_0), + PINMUX_DATA(VIO0_D13_PORT22_MARK, PORT22_FN7, MSEL5CR_27_1), + + /* Port23 */ + PINMUX_DATA(SCIFA1_RTS_MARK, PORT23_FN1), + PINMUX_DATA(SCIFA5_SCK_PORT23_MARK, PORT23_FN3, MSEL5CR_13_0), + PINMUX_DATA(TPU0TO0_MARK, PORT23_FN4), + PINMUX_DATA(VIO_CKO_1_MARK, PORT23_FN5), + PINMUX_DATA(STP0_IPD2_MARK, PORT23_FN6), + PINMUX_DATA(LCD1_D7_MARK, PORT23_FN7), + + /* Port24 */ + PINMUX_DATA(VIO0_D15_PORT24_MARK, PORT24_FN1, MSEL5CR_27_0), + PINMUX_DATA(VIO1_D7_MARK, PORT24_FN5), + PINMUX_DATA(SCIFA6_SCK_MARK, PORT24_FN6), + PINMUX_DATA(SDHI2_CD_PORT24_MARK, PORT24_FN7, MSEL5CR_19_0), + + /* Port25 */ + PINMUX_DATA(VIO0_D14_PORT25_MARK, PORT25_FN1, MSEL5CR_27_0), + PINMUX_DATA(VIO1_D6_MARK, PORT25_FN5), + PINMUX_DATA(SCIFA6_RXD_MARK, PORT25_FN6), + PINMUX_DATA(SDHI2_WP_PORT25_MARK, PORT25_FN7, MSEL5CR_19_0), + + /* Port26 */ + PINMUX_DATA(VIO0_D13_PORT26_MARK, PORT26_FN1, MSEL5CR_27_0), + PINMUX_DATA(VIO1_D5_MARK, PORT26_FN5), + PINMUX_DATA(SCIFA6_TXD_MARK, PORT26_FN6), + + /* Port27 - Port39 Function */ + PINMUX_DATA(VIO0_D7_MARK, PORT27_FN1), + PINMUX_DATA(VIO0_D6_MARK, PORT28_FN1), + PINMUX_DATA(VIO0_D5_MARK, PORT29_FN1), + PINMUX_DATA(VIO0_D4_MARK, PORT30_FN1), + PINMUX_DATA(VIO0_D3_MARK, PORT31_FN1), + PINMUX_DATA(VIO0_D2_MARK, PORT32_FN1), + PINMUX_DATA(VIO0_D1_MARK, PORT33_FN1), + PINMUX_DATA(VIO0_D0_MARK, PORT34_FN1), + PINMUX_DATA(VIO0_CLK_MARK, PORT35_FN1), + PINMUX_DATA(VIO_CKO_MARK, PORT36_FN1), + PINMUX_DATA(VIO0_HD_MARK, PORT37_FN1), + PINMUX_DATA(VIO0_FIELD_MARK, PORT38_FN1), + PINMUX_DATA(VIO0_VD_MARK, PORT39_FN1), + + /* Port38 IRQ */ + PINMUX_DATA(IRQ25_MARK, PORT38_FN0), + + /* Port40 */ + PINMUX_DATA(LCD0_D18_PORT40_MARK, PORT40_FN4, MSEL5CR_6_0), + PINMUX_DATA(RSPI_CK_A_MARK, PORT40_FN6), + PINMUX_DATA(LCD1_LCLK_MARK, PORT40_FN7), + + /* Port41 */ + PINMUX_DATA(LCD0_D17_MARK, PORT41_FN1), + PINMUX_DATA(MSIOF2_SS1_MARK, PORT41_FN2), + PINMUX_DATA(IRQ31_PORT41_MARK, PORT41_FN0, MSEL1CR_31_1), + + /* Port42 */ + PINMUX_DATA(LCD0_D16_MARK, PORT42_FN1), + PINMUX_DATA(MSIOF2_MCK1_MARK, PORT42_FN2), + PINMUX_DATA(IRQ12_PORT42_MARK, PORT42_FN0, MSEL1CR_12_1), + + /* Port43 */ + PINMUX_DATA(LCD0_D15_MARK, PORT43_FN1), + PINMUX_DATA(MSIOF2_MCK0_MARK, PORT43_FN2), + PINMUX_DATA(KEYIN0_PORT43_MARK, PORT43_FN3, MSEL4CR_18_0), + PINMUX_DATA(DV_D15_MARK, PORT43_FN6), + + /* Port44 */ + PINMUX_DATA(LCD0_D14_MARK, PORT44_FN1), + PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT44_FN2), + PINMUX_DATA(KEYIN1_PORT44_MARK, PORT44_FN3, MSEL4CR_18_0), + PINMUX_DATA(DV_D14_MARK, PORT44_FN6), + + /* Port45 */ + PINMUX_DATA(LCD0_D13_MARK, PORT45_FN1), + PINMUX_DATA(MSIOF2_RSCK_MARK, PORT45_FN2), + PINMUX_DATA(KEYIN2_PORT45_MARK, PORT45_FN3, MSEL4CR_18_0), + PINMUX_DATA(DV_D13_MARK, PORT45_FN6), + + /* Port46 */ + PINMUX_DATA(LCD0_D12_MARK, PORT46_FN1), + PINMUX_DATA(KEYIN3_PORT46_MARK, PORT46_FN3, MSEL4CR_18_0), + PINMUX_DATA(DV_D12_MARK, PORT46_FN6), + + /* Port47 */ + PINMUX_DATA(LCD0_D11_MARK, PORT47_FN1), + PINMUX_DATA(KEYIN4_MARK, PORT47_FN3), + PINMUX_DATA(DV_D11_MARK, PORT47_FN6), + + /* Port48 */ + PINMUX_DATA(LCD0_D10_MARK, PORT48_FN1), + PINMUX_DATA(KEYIN5_MARK, PORT48_FN3), + PINMUX_DATA(DV_D10_MARK, PORT48_FN6), + + /* Port49 */ + PINMUX_DATA(LCD0_D9_MARK, PORT49_FN1), + PINMUX_DATA(KEYIN6_MARK, PORT49_FN3), + PINMUX_DATA(DV_D9_MARK, PORT49_FN6), + PINMUX_DATA(IRQ30_PORT49_MARK, PORT49_FN0, MSEL1CR_30_1), + + /* Port50 */ + PINMUX_DATA(LCD0_D8_MARK, PORT50_FN1), + PINMUX_DATA(KEYIN7_MARK, PORT50_FN3), + PINMUX_DATA(DV_D8_MARK, PORT50_FN6), + PINMUX_DATA(IRQ29_PORT50_MARK, PORT50_FN0, MSEL1CR_29_1), + + /* Port51 */ + PINMUX_DATA(LCD0_D7_MARK, PORT51_FN1), + PINMUX_DATA(KEYOUT0_MARK, PORT51_FN3), + PINMUX_DATA(DV_D7_MARK, PORT51_FN6), + + /* Port52 */ + PINMUX_DATA(LCD0_D6_MARK, PORT52_FN1), + PINMUX_DATA(KEYOUT1_MARK, PORT52_FN3), + PINMUX_DATA(DV_D6_MARK, PORT52_FN6), + + /* Port53 */ + PINMUX_DATA(LCD0_D5_MARK, PORT53_FN1), + PINMUX_DATA(KEYOUT2_MARK, PORT53_FN3), + PINMUX_DATA(DV_D5_MARK, PORT53_FN6), + + /* Port54 */ + PINMUX_DATA(LCD0_D4_MARK, PORT54_FN1), + PINMUX_DATA(KEYOUT3_MARK, PORT54_FN3), + PINMUX_DATA(DV_D4_MARK, PORT54_FN6), + + /* Port55 */ + PINMUX_DATA(LCD0_D3_MARK, PORT55_FN1), + PINMUX_DATA(KEYOUT4_MARK, PORT55_FN3), + PINMUX_DATA(KEYIN3_PORT55_MARK, PORT55_FN4, MSEL4CR_18_1), + PINMUX_DATA(DV_D3_MARK, PORT55_FN6), + + /* Port56 */ + PINMUX_DATA(LCD0_D2_MARK, PORT56_FN1), + PINMUX_DATA(KEYOUT5_MARK, PORT56_FN3), + PINMUX_DATA(KEYIN2_PORT56_MARK, PORT56_FN4, MSEL4CR_18_1), + PINMUX_DATA(DV_D2_MARK, PORT56_FN6), + PINMUX_DATA(IRQ28_PORT56_MARK, PORT56_FN0, MSEL1CR_28_1), + + /* Port57 */ + PINMUX_DATA(LCD0_D1_MARK, PORT57_FN1), + PINMUX_DATA(KEYOUT6_MARK, PORT57_FN3), + PINMUX_DATA(KEYIN1_PORT57_MARK, PORT57_FN4, MSEL4CR_18_1), + PINMUX_DATA(DV_D1_MARK, PORT57_FN6), + PINMUX_DATA(IRQ27_PORT57_MARK, PORT57_FN0, MSEL1CR_27_1), + + /* Port58 */ + PINMUX_DATA(LCD0_D0_MARK, PORT58_FN1), + PINMUX_DATA(KEYOUT7_MARK, PORT58_FN3), + PINMUX_DATA(KEYIN0_PORT58_MARK, PORT58_FN4, MSEL4CR_18_1), + PINMUX_DATA(DV_D0_MARK, PORT58_FN6), + PINMUX_DATA(IRQ26_PORT58_MARK, PORT58_FN0, MSEL1CR_26_1), + + /* Port59 */ + PINMUX_DATA(LCD0_VCPWC_MARK, PORT59_FN1), + PINMUX_DATA(BBIF2_TSCK2_PORT59_MARK, PORT59_FN2, MSEL5CR_0_0), + PINMUX_DATA(RSPI_MOSI_A_MARK, PORT59_FN6), + + /* Port60 */ + PINMUX_DATA(LCD0_VEPWC_MARK, PORT60_FN1), + PINMUX_DATA(BBIF2_RXD2_PORT60_MARK, PORT60_FN2, MSEL5CR_0_0), + PINMUX_DATA(RSPI_MISO_A_MARK, PORT60_FN6), + + /* Port61 */ + PINMUX_DATA(LCD0_DON_MARK, PORT61_FN1), + PINMUX_DATA(MSIOF2_TXD_MARK, PORT61_FN2), + + /* Port62 */ + PINMUX_DATA(LCD0_DCK_MARK, PORT62_FN1), + PINMUX_DATA(LCD0_WR_MARK, PORT62_FN4), + PINMUX_DATA(DV_CLK_MARK, PORT62_FN6), + PINMUX_DATA(IRQ15_PORT62_MARK, PORT62_FN0, MSEL1CR_15_1), + + /* Port63 */ + PINMUX_DATA(LCD0_VSYN_MARK, PORT63_FN1), + PINMUX_DATA(DV_VSYNC_MARK, PORT63_FN6), + PINMUX_DATA(IRQ14_PORT63_MARK, PORT63_FN0, MSEL1CR_14_1), + + /* Port64 */ + PINMUX_DATA(LCD0_HSYN_MARK, PORT64_FN1), + PINMUX_DATA(LCD0_CS_MARK, PORT64_FN4), + PINMUX_DATA(DV_HSYNC_MARK, PORT64_FN6), + PINMUX_DATA(IRQ13_PORT64_MARK, PORT64_FN0, MSEL1CR_13_1), + + /* Port65 */ + PINMUX_DATA(LCD0_DISP_MARK, PORT65_FN1), + PINMUX_DATA(MSIOF2_TSCK_MARK, PORT65_FN2), + PINMUX_DATA(LCD0_RS_MARK, PORT65_FN4), + + /* Port66 */ + PINMUX_DATA(MEMC_INT_MARK, PORT66_FN1), + PINMUX_DATA(TPU0TO2_PORT66_MARK, PORT66_FN3, MSEL5CR_25_0), + PINMUX_DATA(MMC0_CLK_PORT66_MARK, PORT66_FN4, MSEL4CR_15_0), + PINMUX_DATA(SDHI1_CLK_MARK, PORT66_FN6), + + /* Port67 - Port73 Function1 */ + PINMUX_DATA(MEMC_CS0_MARK, PORT67_FN1), + PINMUX_DATA(MEMC_AD8_MARK, PORT68_FN1), + PINMUX_DATA(MEMC_AD9_MARK, PORT69_FN1), + PINMUX_DATA(MEMC_AD10_MARK, PORT70_FN1), + PINMUX_DATA(MEMC_AD11_MARK, PORT71_FN1), + PINMUX_DATA(MEMC_AD12_MARK, PORT72_FN1), + PINMUX_DATA(MEMC_AD13_MARK, PORT73_FN1), + + /* Port67 - Port73 Function2 */ + PINMUX_DATA(MSIOF1_SS1_PORT67_MARK, PORT67_FN2, MSEL4CR_10_1), + PINMUX_DATA(MSIOF1_RSCK_MARK, PORT68_FN2), + PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT69_FN2), + PINMUX_DATA(MSIOF1_MCK0_MARK, PORT70_FN2), + PINMUX_DATA(MSIOF1_MCK1_MARK, PORT71_FN2), + PINMUX_DATA(MSIOF1_TSCK_PORT72_MARK, PORT72_FN2, MSEL4CR_10_1), + PINMUX_DATA(MSIOF1_TSYNC_PORT73_MARK, PORT73_FN2, MSEL4CR_10_1), + + /* Port67 - Port73 Function4 */ + PINMUX_DATA(MMC0_CMD_PORT67_MARK, PORT67_FN4, MSEL4CR_15_0), + PINMUX_DATA(MMC0_D0_PORT68_MARK, PORT68_FN4, MSEL4CR_15_0), + PINMUX_DATA(MMC0_D1_PORT69_MARK, PORT69_FN4, MSEL4CR_15_0), + PINMUX_DATA(MMC0_D2_PORT70_MARK, PORT70_FN4, MSEL4CR_15_0), + PINMUX_DATA(MMC0_D3_PORT71_MARK, PORT71_FN4, MSEL4CR_15_0), + PINMUX_DATA(MMC0_D4_PORT72_MARK, PORT72_FN4, MSEL4CR_15_0), + PINMUX_DATA(MMC0_D5_PORT73_MARK, PORT73_FN4, MSEL4CR_15_0), + + /* Port67 - Port73 Function6 */ + PINMUX_DATA(SDHI1_CMD_MARK, PORT67_FN6), + PINMUX_DATA(SDHI1_D0_MARK, PORT68_FN6), + PINMUX_DATA(SDHI1_D1_MARK, PORT69_FN6), + PINMUX_DATA(SDHI1_D2_MARK, PORT70_FN6), + PINMUX_DATA(SDHI1_D3_MARK, PORT71_FN6), + PINMUX_DATA(SDHI1_CD_MARK, PORT72_FN6), + PINMUX_DATA(SDHI1_WP_MARK, PORT73_FN6), + + /* Port67 - Port71 IRQ */ + PINMUX_DATA(IRQ20_MARK, PORT67_FN0), + PINMUX_DATA(IRQ16_PORT68_MARK, PORT68_FN0, MSEL1CR_16_0), + PINMUX_DATA(IRQ17_MARK, PORT69_FN0), + PINMUX_DATA(IRQ18_MARK, PORT70_FN0), + PINMUX_DATA(IRQ19_MARK, PORT71_FN0), + + /* Port74 */ + PINMUX_DATA(MEMC_AD14_MARK, PORT74_FN1), + PINMUX_DATA(MSIOF1_TXD_PORT74_MARK, PORT74_FN2, MSEL4CR_10_1), + PINMUX_DATA(MMC0_D6_PORT74_MARK, PORT74_FN4, MSEL4CR_15_0), + PINMUX_DATA(STP1_IPD7_MARK, PORT74_FN6), + PINMUX_DATA(LCD1_D21_MARK, PORT74_FN7), + + /* Port75 */ + PINMUX_DATA(MEMC_AD15_MARK, PORT75_FN1), + PINMUX_DATA(MSIOF1_RXD_PORT75_MARK, PORT75_FN2, MSEL4CR_10_1), + PINMUX_DATA(MMC0_D7_PORT75_MARK, PORT75_FN4, MSEL4CR_15_0), + PINMUX_DATA(STP1_IPD6_MARK, PORT75_FN6), + PINMUX_DATA(LCD1_D20_MARK, PORT75_FN7), + + /* Port76 - Port80 Function */ + PINMUX_DATA(SDHI0_CMD_MARK, PORT76_FN1), + PINMUX_DATA(SDHI0_D0_MARK, PORT77_FN1), + PINMUX_DATA(SDHI0_D1_MARK, PORT78_FN1), + PINMUX_DATA(SDHI0_D2_MARK, PORT79_FN1), + PINMUX_DATA(SDHI0_D3_MARK, PORT80_FN1), + + /* Port81 */ + PINMUX_DATA(SDHI0_CD_MARK, PORT81_FN1), + PINMUX_DATA(IRQ26_PORT81_MARK, PORT81_FN0, MSEL1CR_26_0), + + /* Port82 - Port88 Function */ + PINMUX_DATA(SDHI0_CLK_MARK, PORT82_FN1), + PINMUX_DATA(SDHI0_WP_MARK, PORT83_FN1), + PINMUX_DATA(RESETOUTS_MARK, PORT84_FN1), + PINMUX_DATA(USB0_PPON_MARK, PORT85_FN1), + PINMUX_DATA(USB0_OCI_MARK, PORT86_FN1), + PINMUX_DATA(USB1_PPON_MARK, PORT87_FN1), + PINMUX_DATA(USB1_OCI_MARK, PORT88_FN1), + + /* Port89 */ + PINMUX_DATA(DREQ0_MARK, PORT89_FN1), + PINMUX_DATA(BBIF2_TSCK2_PORT89_MARK, PORT89_FN2, MSEL5CR_0_1), + PINMUX_DATA(RSPI_SSL3_A_MARK, PORT89_FN6), + + /* Port90 */ + PINMUX_DATA(DACK0_MARK, PORT90_FN1), + PINMUX_DATA(BBIF2_RXD2_PORT90_MARK, PORT90_FN2, MSEL5CR_0_1), + PINMUX_DATA(RSPI_SSL2_A_MARK, PORT90_FN6), + PINMUX_DATA(WAIT_PORT90_MARK, PORT90_FN7, MSEL5CR_2_1), + + /* Port91 */ + PINMUX_DATA(MEMC_AD0_MARK, PORT91_FN1), + PINMUX_DATA(BBIF1_RXD_MARK, PORT91_FN2), + PINMUX_DATA(SCIFA5_TXD_PORT91_MARK, PORT91_FN3, MSEL5CR_15_1, + MSEL5CR_14_0), + PINMUX_DATA(LCD1_D5_MARK, PORT91_FN7), + + /* Port92 */ + PINMUX_DATA(MEMC_AD1_MARK, PORT92_FN1), + PINMUX_DATA(BBIF1_TSYNC_MARK, PORT92_FN2), + PINMUX_DATA(SCIFA5_RXD_PORT92_MARK, PORT92_FN3, MSEL5CR_15_1, + MSEL5CR_14_0), + PINMUX_DATA(STP0_IPD1_MARK, PORT92_FN6), + PINMUX_DATA(LCD1_D6_MARK, PORT92_FN7), + + /* Port93 */ + PINMUX_DATA(MEMC_AD2_MARK, PORT93_FN1), + PINMUX_DATA(BBIF1_TSCK_MARK, PORT93_FN2), + PINMUX_DATA(SCIFA4_TXD_PORT93_MARK, PORT93_FN3, MSEL5CR_12_1, + MSEL5CR_11_0), + PINMUX_DATA(STP0_IPD3_MARK, PORT93_FN6), + PINMUX_DATA(LCD1_D8_MARK, PORT93_FN7), + + /* Port94 */ + PINMUX_DATA(MEMC_AD3_MARK, PORT94_FN1), + PINMUX_DATA(BBIF1_TXD_MARK, PORT94_FN2), + PINMUX_DATA(SCIFA4_RXD_PORT94_MARK, PORT94_FN3, MSEL5CR_12_1, + MSEL5CR_11_0), + PINMUX_DATA(STP0_IPD4_MARK, PORT94_FN6), + PINMUX_DATA(LCD1_D9_MARK, PORT94_FN7), + + /* Port95 */ + PINMUX_DATA(MEMC_CS1_MARK, PORT95_FN1, MSEL4CR_6_0), + PINMUX_DATA(MEMC_A1_MARK, PORT95_FN1, MSEL4CR_6_1), + + PINMUX_DATA(SCIFA2_CTS_MARK, PORT95_FN2), + PINMUX_DATA(SIM_RST_MARK, PORT95_FN4), + PINMUX_DATA(VIO0_D14_PORT95_MARK, PORT95_FN7, MSEL5CR_27_1), + PINMUX_DATA(IRQ22_MARK, PORT95_FN0), + + /* Port96 */ + PINMUX_DATA(MEMC_ADV_MARK, PORT96_FN1, MSEL4CR_6_0), + PINMUX_DATA(MEMC_DREQ0_MARK, PORT96_FN1, MSEL4CR_6_1), + + PINMUX_DATA(SCIFA2_RTS_MARK, PORT96_FN2), + PINMUX_DATA(SIM_CLK_MARK, PORT96_FN4), + PINMUX_DATA(VIO0_D15_PORT96_MARK, PORT96_FN7, MSEL5CR_27_1), + PINMUX_DATA(IRQ23_MARK, PORT96_FN0), + + /* Port97 */ + PINMUX_DATA(MEMC_AD4_MARK, PORT97_FN1), + PINMUX_DATA(BBIF1_RSCK_MARK, PORT97_FN2), + PINMUX_DATA(LCD1_CS_MARK, PORT97_FN6), + PINMUX_DATA(LCD1_HSYN_MARK, PORT97_FN7), + PINMUX_DATA(IRQ12_PORT97_MARK, PORT97_FN0, MSEL1CR_12_0), + + /* Port98 */ + PINMUX_DATA(MEMC_AD5_MARK, PORT98_FN1), + PINMUX_DATA(BBIF1_RSYNC_MARK, PORT98_FN2), + PINMUX_DATA(LCD1_VSYN_MARK, PORT98_FN7), + PINMUX_DATA(IRQ13_PORT98_MARK, PORT98_FN0, MSEL1CR_13_0), + + /* Port99 */ + PINMUX_DATA(MEMC_AD6_MARK, PORT99_FN1), + PINMUX_DATA(BBIF1_FLOW_MARK, PORT99_FN2), + PINMUX_DATA(LCD1_WR_MARK, PORT99_FN6), + PINMUX_DATA(LCD1_DCK_MARK, PORT99_FN7), + PINMUX_DATA(IRQ14_PORT99_MARK, PORT99_FN0, MSEL1CR_14_0), + + /* Port100 */ + PINMUX_DATA(MEMC_AD7_MARK, PORT100_FN1), + PINMUX_DATA(BBIF1_RX_FLOW_N_MARK, PORT100_FN2), + PINMUX_DATA(LCD1_DON_MARK, PORT100_FN7), + PINMUX_DATA(IRQ15_PORT100_MARK, PORT100_FN0, MSEL1CR_15_0), + + /* Port101 */ + PINMUX_DATA(FCE0_MARK, PORT101_FN1), + + /* Port102 */ + PINMUX_DATA(FRB_MARK, PORT102_FN1), + PINMUX_DATA(LCD0_LCLK_PORT102_MARK, PORT102_FN4, MSEL5CR_6_0), + + /* Port103 */ + PINMUX_DATA(CS5B_MARK, PORT103_FN1), + PINMUX_DATA(FCE1_MARK, PORT103_FN2), + PINMUX_DATA(MMC1_CLK_PORT103_MARK, PORT103_FN3, MSEL4CR_15_1), + + /* Port104 */ + PINMUX_DATA(CS6A_MARK, PORT104_FN1), + PINMUX_DATA(MMC1_CMD_PORT104_MARK, PORT104_FN3, MSEL4CR_15_1), + PINMUX_DATA(IRQ11_MARK, PORT104_FN0), + + /* Port105 */ + PINMUX_DATA(CS5A_PORT105_MARK, PORT105_FN1, MSEL5CR_2_0), + PINMUX_DATA(SCIFA3_RTS_PORT105_MARK, PORT105_FN4, MSEL5CR_8_0), + + /* Port106 */ + PINMUX_DATA(IOIS16_MARK, PORT106_FN1), + PINMUX_DATA(IDE_EXBUF_ENB_MARK, PORT106_FN6), + + /* Port107 - Port115 Function */ + PINMUX_DATA(WE3_ICIOWR_MARK, PORT107_FN1), + PINMUX_DATA(WE2_ICIORD_MARK, PORT108_FN1), + PINMUX_DATA(CS0_MARK, PORT109_FN1), + PINMUX_DATA(CS2_MARK, PORT110_FN1), + PINMUX_DATA(CS4_MARK, PORT111_FN1), + PINMUX_DATA(WE1_MARK, PORT112_FN1), + PINMUX_DATA(WE0_FWE_MARK, PORT113_FN1), + PINMUX_DATA(RDWR_MARK, PORT114_FN1), + PINMUX_DATA(RD_FSC_MARK, PORT115_FN1), + + /* Port116 */ + PINMUX_DATA(A25_MARK, PORT116_FN1), + PINMUX_DATA(MSIOF0_SS2_MARK, PORT116_FN2), + PINMUX_DATA(MSIOF1_SS2_PORT116_MARK, PORT116_FN3, MSEL4CR_10_0), + PINMUX_DATA(SCIFA3_SCK_PORT116_MARK, PORT116_FN4, MSEL5CR_8_0), + PINMUX_DATA(GPO1_MARK, PORT116_FN5), + + /* Port117 */ + PINMUX_DATA(A24_MARK, PORT117_FN1), + PINMUX_DATA(MSIOF0_SS1_MARK, PORT117_FN2), + PINMUX_DATA(MSIOF1_SS1_PORT117_MARK, PORT117_FN3, MSEL4CR_10_0), + PINMUX_DATA(SCIFA3_CTS_PORT117_MARK, PORT117_FN4, MSEL5CR_8_0), + PINMUX_DATA(GPO0_MARK, PORT117_FN5), + + /* Port118 */ + PINMUX_DATA(A23_MARK, PORT118_FN1), + PINMUX_DATA(MSIOF0_MCK1_MARK, PORT118_FN2), + PINMUX_DATA(MSIOF1_RXD_PORT118_MARK, PORT118_FN3, MSEL4CR_10_0), + PINMUX_DATA(GPI1_MARK, PORT118_FN5), + PINMUX_DATA(IRQ9_PORT118_MARK, PORT118_FN0, MSEL1CR_9_0), + + /* Port119 */ + PINMUX_DATA(A22_MARK, PORT119_FN1), + PINMUX_DATA(MSIOF0_MCK0_MARK, PORT119_FN2), + PINMUX_DATA(MSIOF1_TXD_PORT119_MARK, PORT119_FN3, MSEL4CR_10_0), + PINMUX_DATA(GPI0_MARK, PORT119_FN5), + PINMUX_DATA(IRQ8_MARK, PORT119_FN0), + + /* Port120 */ + PINMUX_DATA(A21_MARK, PORT120_FN1), + PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT120_FN2), + PINMUX_DATA(MSIOF1_TSYNC_PORT120_MARK, PORT120_FN3, MSEL4CR_10_0), + PINMUX_DATA(IRQ7_PORT120_MARK, PORT120_FN0, MSEL1CR_7_0), + + /* Port121 */ + PINMUX_DATA(A20_MARK, PORT121_FN1), + PINMUX_DATA(MSIOF0_RSCK_MARK, PORT121_FN2), + PINMUX_DATA(MSIOF1_TSCK_PORT121_MARK, PORT121_FN3, MSEL4CR_10_0), + PINMUX_DATA(IRQ6_PORT121_MARK, PORT121_FN0, MSEL1CR_6_0), + + /* Port122 */ + PINMUX_DATA(A19_MARK, PORT122_FN1), + PINMUX_DATA(MSIOF0_RXD_MARK, PORT122_FN2), + + /* Port123 */ + PINMUX_DATA(A18_MARK, PORT123_FN1), + PINMUX_DATA(MSIOF0_TSCK_MARK, PORT123_FN2), + + /* Port124 */ + PINMUX_DATA(A17_MARK, PORT124_FN1), + PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT124_FN2), + + /* Port125 - Port141 Function */ + PINMUX_DATA(A16_MARK, PORT125_FN1), + PINMUX_DATA(A15_MARK, PORT126_FN1), + PINMUX_DATA(A14_MARK, PORT127_FN1), + PINMUX_DATA(A13_MARK, PORT128_FN1), + PINMUX_DATA(A12_MARK, PORT129_FN1), + PINMUX_DATA(A11_MARK, PORT130_FN1), + PINMUX_DATA(A10_MARK, PORT131_FN1), + PINMUX_DATA(A9_MARK, PORT132_FN1), + PINMUX_DATA(A8_MARK, PORT133_FN1), + PINMUX_DATA(A7_MARK, PORT134_FN1), + PINMUX_DATA(A6_MARK, PORT135_FN1), + PINMUX_DATA(A5_FCDE_MARK, PORT136_FN1), + PINMUX_DATA(A4_FOE_MARK, PORT137_FN1), + PINMUX_DATA(A3_MARK, PORT138_FN1), + PINMUX_DATA(A2_MARK, PORT139_FN1), + PINMUX_DATA(A1_MARK, PORT140_FN1), + PINMUX_DATA(CKO_MARK, PORT141_FN1), + + /* Port142 - Port157 Function1 */ + PINMUX_DATA(D15_NAF15_MARK, PORT142_FN1), + PINMUX_DATA(D14_NAF14_MARK, PORT143_FN1), + PINMUX_DATA(D13_NAF13_MARK, PORT144_FN1), + PINMUX_DATA(D12_NAF12_MARK, PORT145_FN1), + PINMUX_DATA(D11_NAF11_MARK, PORT146_FN1), + PINMUX_DATA(D10_NAF10_MARK, PORT147_FN1), + PINMUX_DATA(D9_NAF9_MARK, PORT148_FN1), + PINMUX_DATA(D8_NAF8_MARK, PORT149_FN1), + PINMUX_DATA(D7_NAF7_MARK, PORT150_FN1), + PINMUX_DATA(D6_NAF6_MARK, PORT151_FN1), + PINMUX_DATA(D5_NAF5_MARK, PORT152_FN1), + PINMUX_DATA(D4_NAF4_MARK, PORT153_FN1), + PINMUX_DATA(D3_NAF3_MARK, PORT154_FN1), + PINMUX_DATA(D2_NAF2_MARK, PORT155_FN1), + PINMUX_DATA(D1_NAF1_MARK, PORT156_FN1), + PINMUX_DATA(D0_NAF0_MARK, PORT157_FN1), + + /* Port142 - Port149 Function3 */ + PINMUX_DATA(MMC1_D7_PORT142_MARK, PORT142_FN3, MSEL4CR_15_1), + PINMUX_DATA(MMC1_D6_PORT143_MARK, PORT143_FN3, MSEL4CR_15_1), + PINMUX_DATA(MMC1_D5_PORT144_MARK, PORT144_FN3, MSEL4CR_15_1), + PINMUX_DATA(MMC1_D4_PORT145_MARK, PORT145_FN3, MSEL4CR_15_1), + PINMUX_DATA(MMC1_D3_PORT146_MARK, PORT146_FN3, MSEL4CR_15_1), + PINMUX_DATA(MMC1_D2_PORT147_MARK, PORT147_FN3, MSEL4CR_15_1), + PINMUX_DATA(MMC1_D1_PORT148_MARK, PORT148_FN3, MSEL4CR_15_1), + PINMUX_DATA(MMC1_D0_PORT149_MARK, PORT149_FN3, MSEL4CR_15_1), + + /* Port158 */ + PINMUX_DATA(D31_MARK, PORT158_FN1), + PINMUX_DATA(SCIFA3_SCK_PORT158_MARK, PORT158_FN2, MSEL5CR_8_1), + PINMUX_DATA(RMII_REF125CK_MARK, PORT158_FN3), + PINMUX_DATA(LCD0_D21_PORT158_MARK, PORT158_FN4, MSEL5CR_6_1), + PINMUX_DATA(IRDA_FIRSEL_MARK, PORT158_FN5), + PINMUX_DATA(IDE_D15_MARK, PORT158_FN6), + + /* Port159 */ + PINMUX_DATA(D30_MARK, PORT159_FN1), + PINMUX_DATA(SCIFA3_RXD_PORT159_MARK, PORT159_FN2, MSEL5CR_8_1), + PINMUX_DATA(RMII_REF50CK_MARK, PORT159_FN3), + PINMUX_DATA(LCD0_D23_PORT159_MARK, PORT159_FN4, MSEL5CR_6_1), + PINMUX_DATA(IDE_D14_MARK, PORT159_FN6), + + /* Port160 */ + PINMUX_DATA(D29_MARK, PORT160_FN1), + PINMUX_DATA(SCIFA3_TXD_PORT160_MARK, PORT160_FN2, MSEL5CR_8_1), + PINMUX_DATA(LCD0_D22_PORT160_MARK, PORT160_FN4, MSEL5CR_6_1), + PINMUX_DATA(VIO1_HD_MARK, PORT160_FN5), + PINMUX_DATA(IDE_D13_MARK, PORT160_FN6), + + /* Port161 */ + PINMUX_DATA(D28_MARK, PORT161_FN1), + PINMUX_DATA(SCIFA3_RTS_PORT161_MARK, PORT161_FN2, MSEL5CR_8_1), + PINMUX_DATA(ET_RX_DV_MARK, PORT161_FN3), + PINMUX_DATA(LCD0_D20_PORT161_MARK, PORT161_FN4, MSEL5CR_6_1), + PINMUX_DATA(IRDA_IN_MARK, PORT161_FN5), + PINMUX_DATA(IDE_D12_MARK, PORT161_FN6), + + /* Port162 */ + PINMUX_DATA(D27_MARK, PORT162_FN1), + PINMUX_DATA(SCIFA3_CTS_PORT162_MARK, PORT162_FN2, MSEL5CR_8_1), + PINMUX_DATA(LCD0_D19_PORT162_MARK, PORT162_FN4, MSEL5CR_6_1), + PINMUX_DATA(IRDA_OUT_MARK, PORT162_FN5), + PINMUX_DATA(IDE_D11_MARK, PORT162_FN6), + + /* Port163 */ + PINMUX_DATA(D26_MARK, PORT163_FN1), + PINMUX_DATA(MSIOF2_SS2_MARK, PORT163_FN2), + PINMUX_DATA(ET_COL_MARK, PORT163_FN3), + PINMUX_DATA(LCD0_D18_PORT163_MARK, PORT163_FN4, MSEL5CR_6_1), + PINMUX_DATA(IROUT_MARK, PORT163_FN5), + PINMUX_DATA(IDE_D10_MARK, PORT163_FN6), + + /* Port164 */ + PINMUX_DATA(D25_MARK, PORT164_FN1), + PINMUX_DATA(MSIOF2_TSYNC_MARK, PORT164_FN2), + PINMUX_DATA(ET_PHY_INT_MARK, PORT164_FN3), + PINMUX_DATA(LCD0_RD_MARK, PORT164_FN4), + PINMUX_DATA(IDE_D9_MARK, PORT164_FN6), + + /* Port165 */ + PINMUX_DATA(D24_MARK, PORT165_FN1), + PINMUX_DATA(MSIOF2_RXD_MARK, PORT165_FN2), + PINMUX_DATA(LCD0_LCLK_PORT165_MARK, PORT165_FN4, MSEL5CR_6_1), + PINMUX_DATA(IDE_D8_MARK, PORT165_FN6), + + /* Port166 - Port171 Function1 */ + PINMUX_DATA(D21_MARK, PORT166_FN1), + PINMUX_DATA(D20_MARK, PORT167_FN1), + PINMUX_DATA(D19_MARK, PORT168_FN1), + PINMUX_DATA(D18_MARK, PORT169_FN1), + PINMUX_DATA(D17_MARK, PORT170_FN1), + PINMUX_DATA(D16_MARK, PORT171_FN1), + + /* Port166 - Port171 Function3 */ + PINMUX_DATA(ET_ETXD5_MARK, PORT166_FN3), + PINMUX_DATA(ET_ETXD4_MARK, PORT167_FN3), + PINMUX_DATA(ET_ETXD3_MARK, PORT168_FN3), + PINMUX_DATA(ET_ETXD2_MARK, PORT169_FN3), + PINMUX_DATA(ET_ETXD1_MARK, PORT170_FN3), + PINMUX_DATA(ET_ETXD0_MARK, PORT171_FN3), + + /* Port166 - Port171 Function6 */ + PINMUX_DATA(IDE_D5_MARK, PORT166_FN6), + PINMUX_DATA(IDE_D4_MARK, PORT167_FN6), + PINMUX_DATA(IDE_D3_MARK, PORT168_FN6), + PINMUX_DATA(IDE_D2_MARK, PORT169_FN6), + PINMUX_DATA(IDE_D1_MARK, PORT170_FN6), + PINMUX_DATA(IDE_D0_MARK, PORT171_FN6), + + /* Port167 - Port171 IRQ */ + PINMUX_DATA(IRQ31_PORT167_MARK, PORT167_FN0, MSEL1CR_31_0), + PINMUX_DATA(IRQ27_PORT168_MARK, PORT168_FN0, MSEL1CR_27_0), + PINMUX_DATA(IRQ28_PORT169_MARK, PORT169_FN0, MSEL1CR_28_0), + PINMUX_DATA(IRQ29_PORT170_MARK, PORT170_FN0, MSEL1CR_29_0), + PINMUX_DATA(IRQ30_PORT171_MARK, PORT171_FN0, MSEL1CR_30_0), + + /* Port172 */ + PINMUX_DATA(D23_MARK, PORT172_FN1), + PINMUX_DATA(SCIFB_RTS_PORT172_MARK, PORT172_FN2, MSEL5CR_17_1), + PINMUX_DATA(ET_ETXD7_MARK, PORT172_FN3), + PINMUX_DATA(IDE_D7_MARK, PORT172_FN6), + PINMUX_DATA(IRQ4_PORT172_MARK, PORT172_FN0, MSEL1CR_4_1), + + /* Port173 */ + PINMUX_DATA(D22_MARK, PORT173_FN1), + PINMUX_DATA(SCIFB_CTS_PORT173_MARK, PORT173_FN2, MSEL5CR_17_1), + PINMUX_DATA(ET_ETXD6_MARK, PORT173_FN3), + PINMUX_DATA(IDE_D6_MARK, PORT173_FN6), + PINMUX_DATA(IRQ6_PORT173_MARK, PORT173_FN0, MSEL1CR_6_1), + + /* Port174 */ + PINMUX_DATA(A26_MARK, PORT174_FN1), + PINMUX_DATA(MSIOF0_TXD_MARK, PORT174_FN2), + PINMUX_DATA(ET_RX_CLK_MARK, PORT174_FN3), + PINMUX_DATA(SCIFA3_RXD_PORT174_MARK, PORT174_FN4, MSEL5CR_8_0), + + /* Port175 */ + PINMUX_DATA(A0_MARK, PORT175_FN1), + PINMUX_DATA(BS_MARK, PORT175_FN2), + PINMUX_DATA(ET_WOL_MARK, PORT175_FN3), + PINMUX_DATA(SCIFA3_TXD_PORT175_MARK, PORT175_FN4, MSEL5CR_8_0), + + /* Port176 */ + PINMUX_DATA(ET_GTX_CLK_MARK, PORT176_FN3), + + /* Port177 */ + PINMUX_DATA(WAIT_PORT177_MARK, PORT177_FN1, MSEL5CR_2_0), + PINMUX_DATA(ET_LINK_MARK, PORT177_FN3), + PINMUX_DATA(IDE_IOWR_MARK, PORT177_FN6), + PINMUX_DATA(SDHI2_WP_PORT177_MARK, PORT177_FN7, MSEL5CR_19_1), + + /* Port178 */ + PINMUX_DATA(VIO0_D12_MARK, PORT178_FN1), + PINMUX_DATA(VIO1_D4_MARK, PORT178_FN5), + PINMUX_DATA(IDE_IORD_MARK, PORT178_FN6), + + /* Port179 */ + PINMUX_DATA(VIO0_D11_MARK, PORT179_FN1), + PINMUX_DATA(VIO1_D3_MARK, PORT179_FN5), + PINMUX_DATA(IDE_IORDY_MARK, PORT179_FN6), + + /* Port180 */ + PINMUX_DATA(VIO0_D10_MARK, PORT180_FN1), + PINMUX_DATA(TPU0TO3_MARK, PORT180_FN4), + PINMUX_DATA(VIO1_D2_MARK, PORT180_FN5), + PINMUX_DATA(IDE_INT_MARK, PORT180_FN6), + PINMUX_DATA(IRQ24_MARK, PORT180_FN0), + + /* Port181 */ + PINMUX_DATA(VIO0_D9_MARK, PORT181_FN1), + PINMUX_DATA(VIO1_D1_MARK, PORT181_FN5), + PINMUX_DATA(IDE_RST_MARK, PORT181_FN6), + + /* Port182 */ + PINMUX_DATA(VIO0_D8_MARK, PORT182_FN1), + PINMUX_DATA(VIO1_D0_MARK, PORT182_FN5), + PINMUX_DATA(IDE_DIRECTION_MARK, PORT182_FN6), + + /* Port183 */ + PINMUX_DATA(DREQ1_MARK, PORT183_FN1), + PINMUX_DATA(BBIF2_TXD2_PORT183_MARK, PORT183_FN2, MSEL5CR_0_1), + PINMUX_DATA(ET_TX_EN_MARK, PORT183_FN3), + + /* Port184 */ + PINMUX_DATA(DACK1_MARK, PORT184_FN1), + PINMUX_DATA(BBIF2_TSYNC2_PORT184_MARK, PORT184_FN2, MSEL5CR_0_1), + PINMUX_DATA(ET_TX_CLK_MARK, PORT184_FN3), + + /* Port185 - Port192 Function1 */ + PINMUX_DATA(SCIFA1_SCK_MARK, PORT185_FN1), + PINMUX_DATA(SCIFB_RTS_PORT186_MARK, PORT186_FN1, MSEL5CR_17_0), + PINMUX_DATA(SCIFB_CTS_PORT187_MARK, PORT187_FN1, MSEL5CR_17_0), + PINMUX_DATA(SCIFA0_SCK_MARK, PORT188_FN1), + PINMUX_DATA(SCIFB_SCK_PORT190_MARK, PORT190_FN1, MSEL5CR_17_0), + PINMUX_DATA(SCIFB_RXD_PORT191_MARK, PORT191_FN1, MSEL5CR_17_0), + PINMUX_DATA(SCIFB_TXD_PORT192_MARK, PORT192_FN1, MSEL5CR_17_0), + + /* Port185 - Port192 Function3 */ + PINMUX_DATA(ET_ERXD0_MARK, PORT185_FN3), + PINMUX_DATA(ET_ERXD1_MARK, PORT186_FN3), + PINMUX_DATA(ET_ERXD2_MARK, PORT187_FN3), + PINMUX_DATA(ET_ERXD3_MARK, PORT188_FN3), + PINMUX_DATA(ET_ERXD4_MARK, PORT189_FN3), + PINMUX_DATA(ET_ERXD5_MARK, PORT190_FN3), + PINMUX_DATA(ET_ERXD6_MARK, PORT191_FN3), + PINMUX_DATA(ET_ERXD7_MARK, PORT192_FN3), + + /* Port185 - Port192 Function6 */ + PINMUX_DATA(STP1_IPCLK_MARK, PORT185_FN6), + PINMUX_DATA(STP1_IPD0_PORT186_MARK, PORT186_FN6, MSEL5CR_23_0), + PINMUX_DATA(STP1_IPEN_PORT187_MARK, PORT187_FN6, MSEL5CR_23_0), + PINMUX_DATA(STP1_IPSYNC_MARK, PORT188_FN6), + PINMUX_DATA(STP0_IPCLK_MARK, PORT189_FN6), + PINMUX_DATA(STP0_IPD0_MARK, PORT190_FN6), + PINMUX_DATA(STP0_IPEN_MARK, PORT191_FN6), + PINMUX_DATA(STP0_IPSYNC_MARK, PORT192_FN6), + + /* Port193 */ + PINMUX_DATA(SCIFA0_CTS_MARK, PORT193_FN1), + PINMUX_DATA(RMII_CRS_DV_MARK, PORT193_FN3), + PINMUX_DATA(STP1_IPEN_PORT193_MARK, PORT193_FN6, MSEL5CR_23_1), + PINMUX_DATA(LCD1_D17_MARK, PORT193_FN7), + + /* Port194 */ + PINMUX_DATA(SCIFA0_RTS_MARK, PORT194_FN1), + PINMUX_DATA(RMII_RX_ER_MARK, PORT194_FN3), + PINMUX_DATA(STP1_IPD0_PORT194_MARK, PORT194_FN6, MSEL5CR_23_1), + PINMUX_DATA(LCD1_D16_MARK, PORT194_FN7), + + /* Port195 */ + PINMUX_DATA(SCIFA1_RXD_MARK, PORT195_FN1), + PINMUX_DATA(RMII_RXD0_MARK, PORT195_FN3), + PINMUX_DATA(STP1_IPD3_MARK, PORT195_FN6), + PINMUX_DATA(LCD1_D15_MARK, PORT195_FN7), + + /* Port196 */ + PINMUX_DATA(SCIFA1_TXD_MARK, PORT196_FN1), + PINMUX_DATA(RMII_RXD1_MARK, PORT196_FN3), + PINMUX_DATA(STP1_IPD2_MARK, PORT196_FN6), + PINMUX_DATA(LCD1_D14_MARK, PORT196_FN7), + + /* Port197 */ + PINMUX_DATA(SCIFA0_RXD_MARK, PORT197_FN1), + PINMUX_DATA(VIO1_CLK_MARK, PORT197_FN5), + PINMUX_DATA(STP1_IPD5_MARK, PORT197_FN6), + PINMUX_DATA(LCD1_D19_MARK, PORT197_FN7), + + /* Port198 */ + PINMUX_DATA(SCIFA0_TXD_MARK, PORT198_FN1), + PINMUX_DATA(VIO1_VD_MARK, PORT198_FN5), + PINMUX_DATA(STP1_IPD4_MARK, PORT198_FN6), + PINMUX_DATA(LCD1_D18_MARK, PORT198_FN7), + + /* Port199 */ + PINMUX_DATA(MEMC_NWE_MARK, PORT199_FN1), + PINMUX_DATA(SCIFA2_SCK_PORT199_MARK, PORT199_FN2, MSEL5CR_7_1), + PINMUX_DATA(RMII_TX_EN_MARK, PORT199_FN3), + PINMUX_DATA(SIM_D_PORT199_MARK, PORT199_FN4, MSEL5CR_21_1), + PINMUX_DATA(STP1_IPD1_MARK, PORT199_FN6), + PINMUX_DATA(LCD1_D13_MARK, PORT199_FN7), + + /* Port200 */ + PINMUX_DATA(MEMC_NOE_MARK, PORT200_FN1), + PINMUX_DATA(SCIFA2_RXD_MARK, PORT200_FN2), + PINMUX_DATA(RMII_TXD0_MARK, PORT200_FN3), + PINMUX_DATA(STP0_IPD7_MARK, PORT200_FN6), + PINMUX_DATA(LCD1_D12_MARK, PORT200_FN7), + + /* Port201 */ + PINMUX_DATA(MEMC_WAIT_MARK, PORT201_FN1, MSEL4CR_6_0), + PINMUX_DATA(MEMC_DREQ1_MARK, PORT201_FN1, MSEL4CR_6_1), + + PINMUX_DATA(SCIFA2_TXD_MARK, PORT201_FN2), + PINMUX_DATA(RMII_TXD1_MARK, PORT201_FN3), + PINMUX_DATA(STP0_IPD6_MARK, PORT201_FN6), + PINMUX_DATA(LCD1_D11_MARK, PORT201_FN7), + + /* Port202 */ + PINMUX_DATA(MEMC_BUSCLK_MARK, PORT202_FN1, MSEL4CR_6_0), + PINMUX_DATA(MEMC_A0_MARK, PORT202_FN1, MSEL4CR_6_1), + + PINMUX_DATA(MSIOF1_SS2_PORT202_MARK, PORT202_FN2, MSEL4CR_10_1), + PINMUX_DATA(RMII_MDC_MARK, PORT202_FN3), + PINMUX_DATA(TPU0TO2_PORT202_MARK, PORT202_FN4, MSEL5CR_25_1), + PINMUX_DATA(IDE_CS0_MARK, PORT202_FN6), + PINMUX_DATA(SDHI2_CD_PORT202_MARK, PORT202_FN7, MSEL5CR_19_1), + PINMUX_DATA(IRQ21_MARK, PORT202_FN0), + + /* Port203 - Port208 Function1 */ + PINMUX_DATA(SDHI2_CLK_MARK, PORT203_FN1), + PINMUX_DATA(SDHI2_CMD_MARK, PORT204_FN1), + PINMUX_DATA(SDHI2_D0_MARK, PORT205_FN1), + PINMUX_DATA(SDHI2_D1_MARK, PORT206_FN1), + PINMUX_DATA(SDHI2_D2_MARK, PORT207_FN1), + PINMUX_DATA(SDHI2_D3_MARK, PORT208_FN1), + + /* Port203 - Port208 Function3 */ + PINMUX_DATA(ET_TX_ER_MARK, PORT203_FN3), + PINMUX_DATA(ET_RX_ER_MARK, PORT204_FN3), + PINMUX_DATA(ET_CRS_MARK, PORT205_FN3), + PINMUX_DATA(ET_MDC_MARK, PORT206_FN3), + PINMUX_DATA(ET_MDIO_MARK, PORT207_FN3), + PINMUX_DATA(RMII_MDIO_MARK, PORT208_FN3), + + /* Port203 - Port208 Function6 */ + PINMUX_DATA(IDE_A2_MARK, PORT203_FN6), + PINMUX_DATA(IDE_A1_MARK, PORT204_FN6), + PINMUX_DATA(IDE_A0_MARK, PORT205_FN6), + PINMUX_DATA(IDE_IODACK_MARK, PORT206_FN6), + PINMUX_DATA(IDE_IODREQ_MARK, PORT207_FN6), + PINMUX_DATA(IDE_CS1_MARK, PORT208_FN6), + + /* Port203 - Port208 Function7 */ + PINMUX_DATA(SCIFA4_TXD_PORT203_MARK, PORT203_FN7, MSEL5CR_12_0, + MSEL5CR_11_1), + PINMUX_DATA(SCIFA4_RXD_PORT204_MARK, PORT204_FN7, MSEL5CR_12_0, + MSEL5CR_11_1), + PINMUX_DATA(SCIFA4_SCK_PORT205_MARK, PORT205_FN7, MSEL5CR_10_1), + PINMUX_DATA(SCIFA5_SCK_PORT206_MARK, PORT206_FN7, MSEL5CR_13_1), + PINMUX_DATA(SCIFA5_RXD_PORT207_MARK, PORT207_FN7, MSEL5CR_15_0, + MSEL5CR_14_1), + PINMUX_DATA(SCIFA5_TXD_PORT208_MARK, PORT208_FN7, MSEL5CR_15_0, + MSEL5CR_14_1), + + /* Port209 */ + PINMUX_DATA(VBUS_MARK, PORT209_FN1), + PINMUX_DATA(IRQ7_PORT209_MARK, PORT209_FN0, MSEL1CR_7_1), + + /* Port210 */ + PINMUX_DATA(IRQ9_PORT210_MARK, PORT210_FN0, MSEL1CR_9_1), + + /* Port211 */ + PINMUX_DATA(IRQ16_PORT211_MARK, PORT211_FN0, MSEL1CR_16_1), + + /* LCDC select */ + PINMUX_DATA(LCDC0_SELECT_MARK, MSEL3CR_6_0), + PINMUX_DATA(LCDC1_SELECT_MARK, MSEL3CR_6_1), + + /* SDENC */ + PINMUX_DATA(SDENC_CPG_MARK, MSEL4CR_19_0), + PINMUX_DATA(SDENC_DV_CLKI_MARK, MSEL4CR_19_1), + + /* SYSC */ + PINMUX_DATA(RESETP_PULLUP_MARK, MSEL4CR_4_0), + PINMUX_DATA(RESETP_PLAIN_MARK, MSEL4CR_4_1), + + /* DEBUG */ + PINMUX_DATA(EDEBGREQ_PULLDOWN_MARK, MSEL4CR_1_0), + PINMUX_DATA(EDEBGREQ_PULLUP_MARK, MSEL4CR_1_1), + + PINMUX_DATA(TRACEAUD_FROM_VIO_MARK, MSEL5CR_30_0, MSEL5CR_29_0), + PINMUX_DATA(TRACEAUD_FROM_LCDC0_MARK, MSEL5CR_30_0, MSEL5CR_29_1), + PINMUX_DATA(TRACEAUD_FROM_MEMC_MARK, MSEL5CR_30_1, MSEL5CR_29_0), +}; + +static struct pinmux_gpio pinmux_gpios[] = { + + /* PORT */ + GPIO_PORT_ALL(), + + /* IRQ */ + GPIO_FN(IRQ0_PORT2), GPIO_FN(IRQ0_PORT13), + GPIO_FN(IRQ1), + GPIO_FN(IRQ2_PORT11), GPIO_FN(IRQ2_PORT12), + GPIO_FN(IRQ3_PORT10), GPIO_FN(IRQ3_PORT14), + GPIO_FN(IRQ4_PORT15), GPIO_FN(IRQ4_PORT172), + GPIO_FN(IRQ5_PORT0), GPIO_FN(IRQ5_PORT1), + GPIO_FN(IRQ6_PORT121), GPIO_FN(IRQ6_PORT173), + GPIO_FN(IRQ7_PORT120), GPIO_FN(IRQ7_PORT209), + GPIO_FN(IRQ8), + GPIO_FN(IRQ9_PORT118), GPIO_FN(IRQ9_PORT210), + GPIO_FN(IRQ10), + GPIO_FN(IRQ11), + GPIO_FN(IRQ12_PORT42), GPIO_FN(IRQ12_PORT97), + GPIO_FN(IRQ13_PORT64), GPIO_FN(IRQ13_PORT98), + GPIO_FN(IRQ14_PORT63), GPIO_FN(IRQ14_PORT99), + GPIO_FN(IRQ15_PORT62), GPIO_FN(IRQ15_PORT100), + GPIO_FN(IRQ16_PORT68), GPIO_FN(IRQ16_PORT211), + GPIO_FN(IRQ17), + GPIO_FN(IRQ18), + GPIO_FN(IRQ19), + GPIO_FN(IRQ20), + GPIO_FN(IRQ21), + GPIO_FN(IRQ22), + GPIO_FN(IRQ23), + GPIO_FN(IRQ24), + GPIO_FN(IRQ25), + GPIO_FN(IRQ26_PORT58), GPIO_FN(IRQ26_PORT81), + GPIO_FN(IRQ27_PORT57), GPIO_FN(IRQ27_PORT168), + GPIO_FN(IRQ28_PORT56), GPIO_FN(IRQ28_PORT169), + GPIO_FN(IRQ29_PORT50), GPIO_FN(IRQ29_PORT170), + GPIO_FN(IRQ30_PORT49), GPIO_FN(IRQ30_PORT171), + GPIO_FN(IRQ31_PORT41), GPIO_FN(IRQ31_PORT167), + + /* Function */ + + /* DBGT */ + GPIO_FN(DBGMDT2), GPIO_FN(DBGMDT1), GPIO_FN(DBGMDT0), + GPIO_FN(DBGMD10), GPIO_FN(DBGMD11), GPIO_FN(DBGMD20), + GPIO_FN(DBGMD21), + + /* FSI */ + GPIO_FN(FSIAISLD_PORT0), /* FSIAISLD Port 0/5 */ + GPIO_FN(FSIAISLD_PORT5), + GPIO_FN(FSIASPDIF_PORT9), /* FSIASPDIF Port 9/18 */ + GPIO_FN(FSIASPDIF_PORT18), + GPIO_FN(FSIAOSLD1), GPIO_FN(FSIAOSLD2), GPIO_FN(FSIAOLR), + GPIO_FN(FSIAOBT), GPIO_FN(FSIAOSLD), GPIO_FN(FSIAOMC), + GPIO_FN(FSIACK), GPIO_FN(FSIAILR), GPIO_FN(FSIAIBT), + + /* FMSI */ + GPIO_FN(FMSISLD_PORT1), /* FMSISLD Port 1/6 */ + GPIO_FN(FMSISLD_PORT6), + GPIO_FN(FMSIILR), GPIO_FN(FMSIIBT), GPIO_FN(FMSIOLR), + GPIO_FN(FMSIOBT), GPIO_FN(FMSICK), GPIO_FN(FMSOILR), + GPIO_FN(FMSOIBT), GPIO_FN(FMSOOLR), GPIO_FN(FMSOOBT), + GPIO_FN(FMSOSLD), GPIO_FN(FMSOCK), + + /* SCIFA0 */ + GPIO_FN(SCIFA0_SCK), GPIO_FN(SCIFA0_CTS), GPIO_FN(SCIFA0_RTS), + GPIO_FN(SCIFA0_RXD), GPIO_FN(SCIFA0_TXD), + + /* SCIFA1 */ + GPIO_FN(SCIFA1_CTS), GPIO_FN(SCIFA1_SCK), + GPIO_FN(SCIFA1_RXD), GPIO_FN(SCIFA1_TXD), GPIO_FN(SCIFA1_RTS), + + /* SCIFA2 */ + GPIO_FN(SCIFA2_SCK_PORT22), /* SCIFA2_SCK Port 22/199 */ + GPIO_FN(SCIFA2_SCK_PORT199), + GPIO_FN(SCIFA2_RXD), GPIO_FN(SCIFA2_TXD), + GPIO_FN(SCIFA2_CTS), GPIO_FN(SCIFA2_RTS), + + /* SCIFA3 */ + GPIO_FN(SCIFA3_RTS_PORT105), /* MSEL5CR_8_0 */ + GPIO_FN(SCIFA3_SCK_PORT116), + GPIO_FN(SCIFA3_CTS_PORT117), + GPIO_FN(SCIFA3_RXD_PORT174), + GPIO_FN(SCIFA3_TXD_PORT175), + + GPIO_FN(SCIFA3_RTS_PORT161), /* MSEL5CR_8_1 */ + GPIO_FN(SCIFA3_SCK_PORT158), + GPIO_FN(SCIFA3_CTS_PORT162), + GPIO_FN(SCIFA3_RXD_PORT159), + GPIO_FN(SCIFA3_TXD_PORT160), + + /* SCIFA4 */ + GPIO_FN(SCIFA4_RXD_PORT12), /* MSEL5CR[12:11] = 00 */ + GPIO_FN(SCIFA4_TXD_PORT13), + + GPIO_FN(SCIFA4_RXD_PORT204), /* MSEL5CR[12:11] = 01 */ + GPIO_FN(SCIFA4_TXD_PORT203), + + GPIO_FN(SCIFA4_RXD_PORT94), /* MSEL5CR[12:11] = 10 */ + GPIO_FN(SCIFA4_TXD_PORT93), + + GPIO_FN(SCIFA4_SCK_PORT21), /* SCIFA4_SCK Port 21/205 */ + GPIO_FN(SCIFA4_SCK_PORT205), + + /* SCIFA5 */ + GPIO_FN(SCIFA5_TXD_PORT20), /* MSEL5CR[15:14] = 00 */ + GPIO_FN(SCIFA5_RXD_PORT10), + + GPIO_FN(SCIFA5_RXD_PORT207), /* MSEL5CR[15:14] = 01 */ + GPIO_FN(SCIFA5_TXD_PORT208), + + GPIO_FN(SCIFA5_TXD_PORT91), /* MSEL5CR[15:14] = 10 */ + GPIO_FN(SCIFA5_RXD_PORT92), + + GPIO_FN(SCIFA5_SCK_PORT23), /* SCIFA5_SCK Port 23/206 */ + GPIO_FN(SCIFA5_SCK_PORT206), + + /* SCIFA6 */ + GPIO_FN(SCIFA6_SCK), GPIO_FN(SCIFA6_RXD), GPIO_FN(SCIFA6_TXD), + + /* SCIFA7 */ + GPIO_FN(SCIFA7_TXD), GPIO_FN(SCIFA7_RXD), + + /* SCIFAB */ + GPIO_FN(SCIFB_SCK_PORT190), /* MSEL5CR_17_0 */ + GPIO_FN(SCIFB_RXD_PORT191), + GPIO_FN(SCIFB_TXD_PORT192), + GPIO_FN(SCIFB_RTS_PORT186), + GPIO_FN(SCIFB_CTS_PORT187), + + GPIO_FN(SCIFB_SCK_PORT2), /* MSEL5CR_17_1 */ + GPIO_FN(SCIFB_RXD_PORT3), + GPIO_FN(SCIFB_TXD_PORT4), + GPIO_FN(SCIFB_RTS_PORT172), + GPIO_FN(SCIFB_CTS_PORT173), + + /* LCD0 */ + GPIO_FN(LCD0_D0), GPIO_FN(LCD0_D1), GPIO_FN(LCD0_D2), + GPIO_FN(LCD0_D3), GPIO_FN(LCD0_D4), GPIO_FN(LCD0_D5), + GPIO_FN(LCD0_D6), GPIO_FN(LCD0_D7), GPIO_FN(LCD0_D8), + GPIO_FN(LCD0_D9), GPIO_FN(LCD0_D10), GPIO_FN(LCD0_D11), + GPIO_FN(LCD0_D12), GPIO_FN(LCD0_D13), GPIO_FN(LCD0_D14), + GPIO_FN(LCD0_D15), GPIO_FN(LCD0_D16), GPIO_FN(LCD0_D17), + GPIO_FN(LCD0_DON), GPIO_FN(LCD0_VCPWC), GPIO_FN(LCD0_VEPWC), + GPIO_FN(LCD0_DCK), GPIO_FN(LCD0_VSYN), + GPIO_FN(LCD0_HSYN), GPIO_FN(LCD0_DISP), + GPIO_FN(LCD0_WR), GPIO_FN(LCD0_RD), + GPIO_FN(LCD0_CS), GPIO_FN(LCD0_RS), + + GPIO_FN(LCD0_D18_PORT163), GPIO_FN(LCD0_D19_PORT162), + GPIO_FN(LCD0_D20_PORT161), GPIO_FN(LCD0_D21_PORT158), + GPIO_FN(LCD0_D22_PORT160), GPIO_FN(LCD0_D23_PORT159), + GPIO_FN(LCD0_LCLK_PORT165), /* MSEL5CR_6_1 */ + + GPIO_FN(LCD0_D18_PORT40), GPIO_FN(LCD0_D19_PORT4), + GPIO_FN(LCD0_D20_PORT3), GPIO_FN(LCD0_D21_PORT2), + GPIO_FN(LCD0_D22_PORT0), GPIO_FN(LCD0_D23_PORT1), + GPIO_FN(LCD0_LCLK_PORT102), /* MSEL5CR_6_0 */ + + /* LCD1 */ + GPIO_FN(LCD1_D0), GPIO_FN(LCD1_D1), GPIO_FN(LCD1_D2), + GPIO_FN(LCD1_D3), GPIO_FN(LCD1_D4), GPIO_FN(LCD1_D5), + GPIO_FN(LCD1_D6), GPIO_FN(LCD1_D7), GPIO_FN(LCD1_D8), + GPIO_FN(LCD1_D9), GPIO_FN(LCD1_D10), GPIO_FN(LCD1_D11), + GPIO_FN(LCD1_D12), GPIO_FN(LCD1_D13), GPIO_FN(LCD1_D14), + GPIO_FN(LCD1_D15), GPIO_FN(LCD1_D16), GPIO_FN(LCD1_D17), + GPIO_FN(LCD1_D18), GPIO_FN(LCD1_D19), GPIO_FN(LCD1_D20), + GPIO_FN(LCD1_D21), GPIO_FN(LCD1_D22), GPIO_FN(LCD1_D23), + GPIO_FN(LCD1_RS), GPIO_FN(LCD1_RD), GPIO_FN(LCD1_CS), + GPIO_FN(LCD1_WR), GPIO_FN(LCD1_DCK), GPIO_FN(LCD1_DON), + GPIO_FN(LCD1_VCPWC), GPIO_FN(LCD1_LCLK), GPIO_FN(LCD1_HSYN), + GPIO_FN(LCD1_VSYN), GPIO_FN(LCD1_VEPWC), GPIO_FN(LCD1_DISP), + + /* RSPI */ + GPIO_FN(RSPI_SSL0_A), GPIO_FN(RSPI_SSL1_A), GPIO_FN(RSPI_SSL2_A), + GPIO_FN(RSPI_SSL3_A), GPIO_FN(RSPI_CK_A), GPIO_FN(RSPI_MOSI_A), + GPIO_FN(RSPI_MISO_A), + + /* VIO CKO */ + GPIO_FN(VIO_CKO1), + GPIO_FN(VIO_CKO2), + GPIO_FN(VIO_CKO_1), + GPIO_FN(VIO_CKO), + + /* VIO0 */ + GPIO_FN(VIO0_D0), GPIO_FN(VIO0_D1), GPIO_FN(VIO0_D2), + GPIO_FN(VIO0_D3), GPIO_FN(VIO0_D4), GPIO_FN(VIO0_D5), + GPIO_FN(VIO0_D6), GPIO_FN(VIO0_D7), GPIO_FN(VIO0_D8), + GPIO_FN(VIO0_D9), GPIO_FN(VIO0_D10), GPIO_FN(VIO0_D11), + GPIO_FN(VIO0_D12), GPIO_FN(VIO0_VD), GPIO_FN(VIO0_HD), + GPIO_FN(VIO0_CLK), GPIO_FN(VIO0_FIELD), + + GPIO_FN(VIO0_D13_PORT26), /* MSEL5CR_27_0 */ + GPIO_FN(VIO0_D14_PORT25), + GPIO_FN(VIO0_D15_PORT24), + + GPIO_FN(VIO0_D13_PORT22), /* MSEL5CR_27_1 */ + GPIO_FN(VIO0_D14_PORT95), + GPIO_FN(VIO0_D15_PORT96), + + /* VIO1 */ + GPIO_FN(VIO1_D0), GPIO_FN(VIO1_D1), GPIO_FN(VIO1_D2), + GPIO_FN(VIO1_D3), GPIO_FN(VIO1_D4), GPIO_FN(VIO1_D5), + GPIO_FN(VIO1_D6), GPIO_FN(VIO1_D7), GPIO_FN(VIO1_VD), + GPIO_FN(VIO1_HD), GPIO_FN(VIO1_CLK), GPIO_FN(VIO1_FIELD), + + /* TPU0 */ + GPIO_FN(TPU0TO0), GPIO_FN(TPU0TO1), GPIO_FN(TPU0TO3), + GPIO_FN(TPU0TO2_PORT66), /* TPU0TO2 Port 66/202 */ + GPIO_FN(TPU0TO2_PORT202), + + /* SSP1 0 */ + GPIO_FN(STP0_IPD0), GPIO_FN(STP0_IPD1), GPIO_FN(STP0_IPD2), + GPIO_FN(STP0_IPD3), GPIO_FN(STP0_IPD4), GPIO_FN(STP0_IPD5), + GPIO_FN(STP0_IPD6), GPIO_FN(STP0_IPD7), GPIO_FN(STP0_IPEN), + GPIO_FN(STP0_IPCLK), GPIO_FN(STP0_IPSYNC), + + /* SSP1 1 */ + GPIO_FN(STP1_IPD1), GPIO_FN(STP1_IPD2), GPIO_FN(STP1_IPD3), + GPIO_FN(STP1_IPD4), GPIO_FN(STP1_IPD5), GPIO_FN(STP1_IPD6), + GPIO_FN(STP1_IPD7), GPIO_FN(STP1_IPCLK), GPIO_FN(STP1_IPSYNC), + + GPIO_FN(STP1_IPD0_PORT186), /* MSEL5CR_23_0 */ + GPIO_FN(STP1_IPEN_PORT187), + + GPIO_FN(STP1_IPD0_PORT194), /* MSEL5CR_23_1 */ + GPIO_FN(STP1_IPEN_PORT193), + + /* SIM */ + GPIO_FN(SIM_RST), GPIO_FN(SIM_CLK), + GPIO_FN(SIM_D_PORT22), /* SIM_D Port 22/199 */ + GPIO_FN(SIM_D_PORT199), + + /* SDHI0 */ + GPIO_FN(SDHI0_D0), GPIO_FN(SDHI0_D1), GPIO_FN(SDHI0_D2), + GPIO_FN(SDHI0_D3), GPIO_FN(SDHI0_CD), GPIO_FN(SDHI0_WP), + GPIO_FN(SDHI0_CMD), GPIO_FN(SDHI0_CLK), + + /* SDHI1 */ + GPIO_FN(SDHI1_D0), GPIO_FN(SDHI1_D1), GPIO_FN(SDHI1_D2), + GPIO_FN(SDHI1_D3), GPIO_FN(SDHI1_CD), GPIO_FN(SDHI1_WP), + GPIO_FN(SDHI1_CMD), GPIO_FN(SDHI1_CLK), + + /* SDHI2 */ + GPIO_FN(SDHI2_D0), GPIO_FN(SDHI2_D1), GPIO_FN(SDHI2_D2), + GPIO_FN(SDHI2_D3), GPIO_FN(SDHI2_CLK), GPIO_FN(SDHI2_CMD), + + GPIO_FN(SDHI2_CD_PORT24), /* MSEL5CR_19_0 */ + GPIO_FN(SDHI2_WP_PORT25), + + GPIO_FN(SDHI2_WP_PORT177), /* MSEL5CR_19_1 */ + GPIO_FN(SDHI2_CD_PORT202), + + /* MSIOF2 */ + GPIO_FN(MSIOF2_TXD), GPIO_FN(MSIOF2_RXD), GPIO_FN(MSIOF2_TSCK), + GPIO_FN(MSIOF2_SS2), GPIO_FN(MSIOF2_TSYNC), GPIO_FN(MSIOF2_SS1), + GPIO_FN(MSIOF2_MCK1), GPIO_FN(MSIOF2_MCK0), GPIO_FN(MSIOF2_RSYNC), + GPIO_FN(MSIOF2_RSCK), + + /* KEYSC */ + GPIO_FN(KEYIN4), GPIO_FN(KEYIN5), + GPIO_FN(KEYIN6), GPIO_FN(KEYIN7), + GPIO_FN(KEYOUT0), GPIO_FN(KEYOUT1), GPIO_FN(KEYOUT2), + GPIO_FN(KEYOUT3), GPIO_FN(KEYOUT4), GPIO_FN(KEYOUT5), + GPIO_FN(KEYOUT6), GPIO_FN(KEYOUT7), + + GPIO_FN(KEYIN0_PORT43), /* MSEL4CR_18_0 */ + GPIO_FN(KEYIN1_PORT44), + GPIO_FN(KEYIN2_PORT45), + GPIO_FN(KEYIN3_PORT46), + + GPIO_FN(KEYIN0_PORT58), /* MSEL4CR_18_1 */ + GPIO_FN(KEYIN1_PORT57), + GPIO_FN(KEYIN2_PORT56), + GPIO_FN(KEYIN3_PORT55), + + /* VOU */ + GPIO_FN(DV_D0), GPIO_FN(DV_D1), GPIO_FN(DV_D2), + GPIO_FN(DV_D3), GPIO_FN(DV_D4), GPIO_FN(DV_D5), + GPIO_FN(DV_D6), GPIO_FN(DV_D7), GPIO_FN(DV_D8), + GPIO_FN(DV_D9), GPIO_FN(DV_D10), GPIO_FN(DV_D11), + GPIO_FN(DV_D12), GPIO_FN(DV_D13), GPIO_FN(DV_D14), + GPIO_FN(DV_D15), GPIO_FN(DV_CLK), + GPIO_FN(DV_VSYNC), GPIO_FN(DV_HSYNC), + + /* MEMC */ + GPIO_FN(MEMC_AD0), GPIO_FN(MEMC_AD1), GPIO_FN(MEMC_AD2), + GPIO_FN(MEMC_AD3), GPIO_FN(MEMC_AD4), GPIO_FN(MEMC_AD5), + GPIO_FN(MEMC_AD6), GPIO_FN(MEMC_AD7), GPIO_FN(MEMC_AD8), + GPIO_FN(MEMC_AD9), GPIO_FN(MEMC_AD10), GPIO_FN(MEMC_AD11), + GPIO_FN(MEMC_AD12), GPIO_FN(MEMC_AD13), GPIO_FN(MEMC_AD14), + GPIO_FN(MEMC_AD15), GPIO_FN(MEMC_CS0), GPIO_FN(MEMC_INT), + GPIO_FN(MEMC_NWE), GPIO_FN(MEMC_NOE), GPIO_FN(MEMC_CS1), + GPIO_FN(MEMC_A1), GPIO_FN(MEMC_ADV), GPIO_FN(MEMC_DREQ0), + GPIO_FN(MEMC_WAIT), GPIO_FN(MEMC_DREQ1), GPIO_FN(MEMC_BUSCLK), + GPIO_FN(MEMC_A0), + + /* MMC */ + GPIO_FN(MMC0_D0_PORT68), GPIO_FN(MMC0_D1_PORT69), + GPIO_FN(MMC0_D2_PORT70), GPIO_FN(MMC0_D3_PORT71), + GPIO_FN(MMC0_D4_PORT72), GPIO_FN(MMC0_D5_PORT73), + GPIO_FN(MMC0_D6_PORT74), GPIO_FN(MMC0_D7_PORT75), + GPIO_FN(MMC0_CLK_PORT66), + GPIO_FN(MMC0_CMD_PORT67), /* MSEL4CR_15_0 */ + + GPIO_FN(MMC1_D0_PORT149), GPIO_FN(MMC1_D1_PORT148), + GPIO_FN(MMC1_D2_PORT147), GPIO_FN(MMC1_D3_PORT146), + GPIO_FN(MMC1_D4_PORT145), GPIO_FN(MMC1_D5_PORT144), + GPIO_FN(MMC1_D6_PORT143), GPIO_FN(MMC1_D7_PORT142), + GPIO_FN(MMC1_CLK_PORT103), + GPIO_FN(MMC1_CMD_PORT104), /* MSEL4CR_15_1 */ + + /* MSIOF0 */ + GPIO_FN(MSIOF0_SS1), GPIO_FN(MSIOF0_SS2), GPIO_FN(MSIOF0_RXD), + GPIO_FN(MSIOF0_TXD), GPIO_FN(MSIOF0_MCK0), GPIO_FN(MSIOF0_MCK1), + GPIO_FN(MSIOF0_RSYNC), GPIO_FN(MSIOF0_RSCK), GPIO_FN(MSIOF0_TSCK), + GPIO_FN(MSIOF0_TSYNC), + + /* MSIOF1 */ + GPIO_FN(MSIOF1_RSCK), GPIO_FN(MSIOF1_RSYNC), + GPIO_FN(MSIOF1_MCK0), GPIO_FN(MSIOF1_MCK1), + + GPIO_FN(MSIOF1_SS2_PORT116), GPIO_FN(MSIOF1_SS1_PORT117), + GPIO_FN(MSIOF1_RXD_PORT118), GPIO_FN(MSIOF1_TXD_PORT119), + GPIO_FN(MSIOF1_TSYNC_PORT120), + GPIO_FN(MSIOF1_TSCK_PORT121), /* MSEL4CR_10_0 */ + + GPIO_FN(MSIOF1_SS1_PORT67), GPIO_FN(MSIOF1_TSCK_PORT72), + GPIO_FN(MSIOF1_TSYNC_PORT73), GPIO_FN(MSIOF1_TXD_PORT74), + GPIO_FN(MSIOF1_RXD_PORT75), + GPIO_FN(MSIOF1_SS2_PORT202), /* MSEL4CR_10_1 */ + + /* GPIO */ + GPIO_FN(GPO0), GPIO_FN(GPI0), + GPIO_FN(GPO1), GPIO_FN(GPI1), + + /* USB0 */ + GPIO_FN(USB0_OCI), GPIO_FN(USB0_PPON), GPIO_FN(VBUS), + + /* USB1 */ + GPIO_FN(USB1_OCI), GPIO_FN(USB1_PPON), + + /* BBIF1 */ + GPIO_FN(BBIF1_RXD), GPIO_FN(BBIF1_TXD), GPIO_FN(BBIF1_TSYNC), + GPIO_FN(BBIF1_TSCK), GPIO_FN(BBIF1_RSCK), GPIO_FN(BBIF1_RSYNC), + GPIO_FN(BBIF1_FLOW), GPIO_FN(BBIF1_RX_FLOW_N), + + /* BBIF2 */ + GPIO_FN(BBIF2_TXD2_PORT5), /* MSEL5CR_0_0 */ + GPIO_FN(BBIF2_RXD2_PORT60), + GPIO_FN(BBIF2_TSYNC2_PORT6), + GPIO_FN(BBIF2_TSCK2_PORT59), + + GPIO_FN(BBIF2_RXD2_PORT90), /* MSEL5CR_0_1 */ + GPIO_FN(BBIF2_TXD2_PORT183), + GPIO_FN(BBIF2_TSCK2_PORT89), + GPIO_FN(BBIF2_TSYNC2_PORT184), + + /* BSC / FLCTL / PCMCIA */ + GPIO_FN(CS0), GPIO_FN(CS2), GPIO_FN(CS4), + GPIO_FN(CS5B), GPIO_FN(CS6A), + GPIO_FN(CS5A_PORT105), /* CS5A PORT 19/105 */ + GPIO_FN(CS5A_PORT19), + GPIO_FN(IOIS16), /* ? */ + + GPIO_FN(A0), GPIO_FN(A1), GPIO_FN(A2), GPIO_FN(A3), + GPIO_FN(A4_FOE), GPIO_FN(A5_FCDE), /* share with FLCTL */ + GPIO_FN(A6), GPIO_FN(A7), GPIO_FN(A8), GPIO_FN(A9), + GPIO_FN(A10), GPIO_FN(A11), GPIO_FN(A12), GPIO_FN(A13), + GPIO_FN(A14), GPIO_FN(A15), GPIO_FN(A16), GPIO_FN(A17), + GPIO_FN(A18), GPIO_FN(A19), GPIO_FN(A20), GPIO_FN(A21), + GPIO_FN(A22), GPIO_FN(A23), GPIO_FN(A24), GPIO_FN(A25), + GPIO_FN(A26), + + GPIO_FN(D0_NAF0), GPIO_FN(D1_NAF1), /* share with FLCTL */ + GPIO_FN(D2_NAF2), GPIO_FN(D3_NAF3), /* share with FLCTL */ + GPIO_FN(D4_NAF4), GPIO_FN(D5_NAF5), /* share with FLCTL */ + GPIO_FN(D6_NAF6), GPIO_FN(D7_NAF7), /* share with FLCTL */ + GPIO_FN(D8_NAF8), GPIO_FN(D9_NAF9), /* share with FLCTL */ + GPIO_FN(D10_NAF10), GPIO_FN(D11_NAF11), /* share with FLCTL */ + GPIO_FN(D12_NAF12), GPIO_FN(D13_NAF13), /* share with FLCTL */ + GPIO_FN(D14_NAF14), GPIO_FN(D15_NAF15), /* share with FLCTL */ + GPIO_FN(D16), GPIO_FN(D17), GPIO_FN(D18), GPIO_FN(D19), + GPIO_FN(D20), GPIO_FN(D21), GPIO_FN(D22), GPIO_FN(D23), + GPIO_FN(D24), GPIO_FN(D25), GPIO_FN(D26), GPIO_FN(D27), + GPIO_FN(D28), GPIO_FN(D29), GPIO_FN(D30), GPIO_FN(D31), + + GPIO_FN(WE0_FWE), /* share with FLCTL */ + GPIO_FN(WE1), + GPIO_FN(WE2_ICIORD), /* share with PCMCIA */ + GPIO_FN(WE3_ICIOWR), /* share with PCMCIA */ + GPIO_FN(CKO), GPIO_FN(BS), GPIO_FN(RDWR), + GPIO_FN(RD_FSC), /* share with FLCTL */ + GPIO_FN(WAIT_PORT177), /* WAIT Port 90/177 */ + GPIO_FN(WAIT_PORT90), + + GPIO_FN(FCE0), GPIO_FN(FCE1), GPIO_FN(FRB), /* FLCTL */ + + /* IRDA */ + GPIO_FN(IRDA_FIRSEL), GPIO_FN(IRDA_IN), GPIO_FN(IRDA_OUT), + + /* ATAPI */ + GPIO_FN(IDE_D0), GPIO_FN(IDE_D1), GPIO_FN(IDE_D2), + GPIO_FN(IDE_D3), GPIO_FN(IDE_D4), GPIO_FN(IDE_D5), + GPIO_FN(IDE_D6), GPIO_FN(IDE_D7), GPIO_FN(IDE_D8), + GPIO_FN(IDE_D9), GPIO_FN(IDE_D10), GPIO_FN(IDE_D11), + GPIO_FN(IDE_D12), GPIO_FN(IDE_D13), GPIO_FN(IDE_D14), + GPIO_FN(IDE_D15), GPIO_FN(IDE_A0), GPIO_FN(IDE_A1), + GPIO_FN(IDE_A2), GPIO_FN(IDE_CS0), GPIO_FN(IDE_CS1), + GPIO_FN(IDE_IOWR), GPIO_FN(IDE_IORD), GPIO_FN(IDE_IORDY), + GPIO_FN(IDE_INT), GPIO_FN(IDE_RST), GPIO_FN(IDE_DIRECTION), + GPIO_FN(IDE_EXBUF_ENB), GPIO_FN(IDE_IODACK), GPIO_FN(IDE_IODREQ), + + /* RMII */ + GPIO_FN(RMII_CRS_DV), GPIO_FN(RMII_RX_ER), GPIO_FN(RMII_RXD0), + GPIO_FN(RMII_RXD1), GPIO_FN(RMII_TX_EN), GPIO_FN(RMII_TXD0), + GPIO_FN(RMII_MDC), GPIO_FN(RMII_TXD1), GPIO_FN(RMII_MDIO), + GPIO_FN(RMII_REF50CK), GPIO_FN(RMII_REF125CK), /* for GMII */ + + /* GEther */ + GPIO_FN(ET_TX_CLK), GPIO_FN(ET_TX_EN), GPIO_FN(ET_ETXD0), + GPIO_FN(ET_ETXD1), GPIO_FN(ET_ETXD2), GPIO_FN(ET_ETXD3), + GPIO_FN(ET_ETXD4), GPIO_FN(ET_ETXD5), /* for GEther */ + GPIO_FN(ET_ETXD6), GPIO_FN(ET_ETXD7), /* for GEther */ + GPIO_FN(ET_COL), GPIO_FN(ET_TX_ER), GPIO_FN(ET_RX_CLK), + GPIO_FN(ET_RX_DV), GPIO_FN(ET_ERXD0), GPIO_FN(ET_ERXD1), + GPIO_FN(ET_ERXD2), GPIO_FN(ET_ERXD3), + GPIO_FN(ET_ERXD4), GPIO_FN(ET_ERXD5), /* for GEther */ + GPIO_FN(ET_ERXD6), GPIO_FN(ET_ERXD7), /* for GEther */ + GPIO_FN(ET_RX_ER), GPIO_FN(ET_CRS), GPIO_FN(ET_MDC), + GPIO_FN(ET_MDIO), GPIO_FN(ET_LINK), GPIO_FN(ET_PHY_INT), + GPIO_FN(ET_WOL), GPIO_FN(ET_GTX_CLK), + + /* DMA0 */ + GPIO_FN(DREQ0), GPIO_FN(DACK0), + + /* DMA1 */ + GPIO_FN(DREQ1), GPIO_FN(DACK1), + + /* SYSC */ + GPIO_FN(RESETOUTS), + + /* IRREM */ + GPIO_FN(IROUT), + + /* LCDC */ + GPIO_FN(LCDC0_SELECT), + GPIO_FN(LCDC1_SELECT), + + /* SDENC */ + GPIO_FN(SDENC_CPG), + GPIO_FN(SDENC_DV_CLKI), + + /* SYSC */ + GPIO_FN(RESETP_PULLUP), + GPIO_FN(RESETP_PLAIN), + + /* DEBUG */ + GPIO_FN(EDEBGREQ_PULLDOWN), + GPIO_FN(EDEBGREQ_PULLUP), + + GPIO_FN(TRACEAUD_FROM_VIO), + GPIO_FN(TRACEAUD_FROM_LCDC0), + GPIO_FN(TRACEAUD_FROM_MEMC), +}; + +static struct pinmux_cfg_reg pinmux_config_regs[] = { + PORTCR(0, 0xe6050000), /* PORT0CR */ + PORTCR(1, 0xe6050001), /* PORT1CR */ + PORTCR(2, 0xe6050002), /* PORT2CR */ + PORTCR(3, 0xe6050003), /* PORT3CR */ + PORTCR(4, 0xe6050004), /* PORT4CR */ + PORTCR(5, 0xe6050005), /* PORT5CR */ + PORTCR(6, 0xe6050006), /* PORT6CR */ + PORTCR(7, 0xe6050007), /* PORT7CR */ + PORTCR(8, 0xe6050008), /* PORT8CR */ + PORTCR(9, 0xe6050009), /* PORT9CR */ + PORTCR(10, 0xe605000a), /* PORT10CR */ + PORTCR(11, 0xe605000b), /* PORT11CR */ + PORTCR(12, 0xe605000c), /* PORT12CR */ + PORTCR(13, 0xe605000d), /* PORT13CR */ + PORTCR(14, 0xe605000e), /* PORT14CR */ + PORTCR(15, 0xe605000f), /* PORT15CR */ + PORTCR(16, 0xe6050010), /* PORT16CR */ + PORTCR(17, 0xe6050011), /* PORT17CR */ + PORTCR(18, 0xe6050012), /* PORT18CR */ + PORTCR(19, 0xe6050013), /* PORT19CR */ + PORTCR(20, 0xe6050014), /* PORT20CR */ + PORTCR(21, 0xe6050015), /* PORT21CR */ + PORTCR(22, 0xe6050016), /* PORT22CR */ + PORTCR(23, 0xe6050017), /* PORT23CR */ + PORTCR(24, 0xe6050018), /* PORT24CR */ + PORTCR(25, 0xe6050019), /* PORT25CR */ + PORTCR(26, 0xe605001a), /* PORT26CR */ + PORTCR(27, 0xe605001b), /* PORT27CR */ + PORTCR(28, 0xe605001c), /* PORT28CR */ + PORTCR(29, 0xe605001d), /* PORT29CR */ + PORTCR(30, 0xe605001e), /* PORT30CR */ + PORTCR(31, 0xe605001f), /* PORT31CR */ + PORTCR(32, 0xe6050020), /* PORT32CR */ + PORTCR(33, 0xe6050021), /* PORT33CR */ + PORTCR(34, 0xe6050022), /* PORT34CR */ + PORTCR(35, 0xe6050023), /* PORT35CR */ + PORTCR(36, 0xe6050024), /* PORT36CR */ + PORTCR(37, 0xe6050025), /* PORT37CR */ + PORTCR(38, 0xe6050026), /* PORT38CR */ + PORTCR(39, 0xe6050027), /* PORT39CR */ + PORTCR(40, 0xe6050028), /* PORT40CR */ + PORTCR(41, 0xe6050029), /* PORT41CR */ + PORTCR(42, 0xe605002a), /* PORT42CR */ + PORTCR(43, 0xe605002b), /* PORT43CR */ + PORTCR(44, 0xe605002c), /* PORT44CR */ + PORTCR(45, 0xe605002d), /* PORT45CR */ + PORTCR(46, 0xe605002e), /* PORT46CR */ + PORTCR(47, 0xe605002f), /* PORT47CR */ + PORTCR(48, 0xe6050030), /* PORT48CR */ + PORTCR(49, 0xe6050031), /* PORT49CR */ + PORTCR(50, 0xe6050032), /* PORT50CR */ + PORTCR(51, 0xe6050033), /* PORT51CR */ + PORTCR(52, 0xe6050034), /* PORT52CR */ + PORTCR(53, 0xe6050035), /* PORT53CR */ + PORTCR(54, 0xe6050036), /* PORT54CR */ + PORTCR(55, 0xe6050037), /* PORT55CR */ + PORTCR(56, 0xe6050038), /* PORT56CR */ + PORTCR(57, 0xe6050039), /* PORT57CR */ + PORTCR(58, 0xe605003a), /* PORT58CR */ + PORTCR(59, 0xe605003b), /* PORT59CR */ + PORTCR(60, 0xe605003c), /* PORT60CR */ + PORTCR(61, 0xe605003d), /* PORT61CR */ + PORTCR(62, 0xe605003e), /* PORT62CR */ + PORTCR(63, 0xe605003f), /* PORT63CR */ + PORTCR(64, 0xe6050040), /* PORT64CR */ + PORTCR(65, 0xe6050041), /* PORT65CR */ + PORTCR(66, 0xe6050042), /* PORT66CR */ + PORTCR(67, 0xe6050043), /* PORT67CR */ + PORTCR(68, 0xe6050044), /* PORT68CR */ + PORTCR(69, 0xe6050045), /* PORT69CR */ + PORTCR(70, 0xe6050046), /* PORT70CR */ + PORTCR(71, 0xe6050047), /* PORT71CR */ + PORTCR(72, 0xe6050048), /* PORT72CR */ + PORTCR(73, 0xe6050049), /* PORT73CR */ + PORTCR(74, 0xe605004a), /* PORT74CR */ + PORTCR(75, 0xe605004b), /* PORT75CR */ + PORTCR(76, 0xe605004c), /* PORT76CR */ + PORTCR(77, 0xe605004d), /* PORT77CR */ + PORTCR(78, 0xe605004e), /* PORT78CR */ + PORTCR(79, 0xe605004f), /* PORT79CR */ + PORTCR(80, 0xe6050050), /* PORT80CR */ + PORTCR(81, 0xe6050051), /* PORT81CR */ + PORTCR(82, 0xe6050052), /* PORT82CR */ + PORTCR(83, 0xe6050053), /* PORT83CR */ + + PORTCR(84, 0xe6051054), /* PORT84CR */ + PORTCR(85, 0xe6051055), /* PORT85CR */ + PORTCR(86, 0xe6051056), /* PORT86CR */ + PORTCR(87, 0xe6051057), /* PORT87CR */ + PORTCR(88, 0xe6051058), /* PORT88CR */ + PORTCR(89, 0xe6051059), /* PORT89CR */ + PORTCR(90, 0xe605105a), /* PORT90CR */ + PORTCR(91, 0xe605105b), /* PORT91CR */ + PORTCR(92, 0xe605105c), /* PORT92CR */ + PORTCR(93, 0xe605105d), /* PORT93CR */ + PORTCR(94, 0xe605105e), /* PORT94CR */ + PORTCR(95, 0xe605105f), /* PORT95CR */ + PORTCR(96, 0xe6051060), /* PORT96CR */ + PORTCR(97, 0xe6051061), /* PORT97CR */ + PORTCR(98, 0xe6051062), /* PORT98CR */ + PORTCR(99, 0xe6051063), /* PORT99CR */ + PORTCR(100, 0xe6051064), /* PORT100CR */ + PORTCR(101, 0xe6051065), /* PORT101CR */ + PORTCR(102, 0xe6051066), /* PORT102CR */ + PORTCR(103, 0xe6051067), /* PORT103CR */ + PORTCR(104, 0xe6051068), /* PORT104CR */ + PORTCR(105, 0xe6051069), /* PORT105CR */ + PORTCR(106, 0xe605106a), /* PORT106CR */ + PORTCR(107, 0xe605106b), /* PORT107CR */ + PORTCR(108, 0xe605106c), /* PORT108CR */ + PORTCR(109, 0xe605106d), /* PORT109CR */ + PORTCR(110, 0xe605106e), /* PORT110CR */ + PORTCR(111, 0xe605106f), /* PORT111CR */ + PORTCR(112, 0xe6051070), /* PORT112CR */ + PORTCR(113, 0xe6051071), /* PORT113CR */ + PORTCR(114, 0xe6051072), /* PORT114CR */ + + PORTCR(115, 0xe6052073), /* PORT115CR */ + PORTCR(116, 0xe6052074), /* PORT116CR */ + PORTCR(117, 0xe6052075), /* PORT117CR */ + PORTCR(118, 0xe6052076), /* PORT118CR */ + PORTCR(119, 0xe6052077), /* PORT119CR */ + PORTCR(120, 0xe6052078), /* PORT120CR */ + PORTCR(121, 0xe6052079), /* PORT121CR */ + PORTCR(122, 0xe605207a), /* PORT122CR */ + PORTCR(123, 0xe605207b), /* PORT123CR */ + PORTCR(124, 0xe605207c), /* PORT124CR */ + PORTCR(125, 0xe605207d), /* PORT125CR */ + PORTCR(126, 0xe605207e), /* PORT126CR */ + PORTCR(127, 0xe605207f), /* PORT127CR */ + PORTCR(128, 0xe6052080), /* PORT128CR */ + PORTCR(129, 0xe6052081), /* PORT129CR */ + PORTCR(130, 0xe6052082), /* PORT130CR */ + PORTCR(131, 0xe6052083), /* PORT131CR */ + PORTCR(132, 0xe6052084), /* PORT132CR */ + PORTCR(133, 0xe6052085), /* PORT133CR */ + PORTCR(134, 0xe6052086), /* PORT134CR */ + PORTCR(135, 0xe6052087), /* PORT135CR */ + PORTCR(136, 0xe6052088), /* PORT136CR */ + PORTCR(137, 0xe6052089), /* PORT137CR */ + PORTCR(138, 0xe605208a), /* PORT138CR */ + PORTCR(139, 0xe605208b), /* PORT139CR */ + PORTCR(140, 0xe605208c), /* PORT140CR */ + PORTCR(141, 0xe605208d), /* PORT141CR */ + PORTCR(142, 0xe605208e), /* PORT142CR */ + PORTCR(143, 0xe605208f), /* PORT143CR */ + PORTCR(144, 0xe6052090), /* PORT144CR */ + PORTCR(145, 0xe6052091), /* PORT145CR */ + PORTCR(146, 0xe6052092), /* PORT146CR */ + PORTCR(147, 0xe6052093), /* PORT147CR */ + PORTCR(148, 0xe6052094), /* PORT148CR */ + PORTCR(149, 0xe6052095), /* PORT149CR */ + PORTCR(150, 0xe6052096), /* PORT150CR */ + PORTCR(151, 0xe6052097), /* PORT151CR */ + PORTCR(152, 0xe6052098), /* PORT152CR */ + PORTCR(153, 0xe6052099), /* PORT153CR */ + PORTCR(154, 0xe605209a), /* PORT154CR */ + PORTCR(155, 0xe605209b), /* PORT155CR */ + PORTCR(156, 0xe605209c), /* PORT156CR */ + PORTCR(157, 0xe605209d), /* PORT157CR */ + PORTCR(158, 0xe605209e), /* PORT158CR */ + PORTCR(159, 0xe605209f), /* PORT159CR */ + PORTCR(160, 0xe60520a0), /* PORT160CR */ + PORTCR(161, 0xe60520a1), /* PORT161CR */ + PORTCR(162, 0xe60520a2), /* PORT162CR */ + PORTCR(163, 0xe60520a3), /* PORT163CR */ + PORTCR(164, 0xe60520a4), /* PORT164CR */ + PORTCR(165, 0xe60520a5), /* PORT165CR */ + PORTCR(166, 0xe60520a6), /* PORT166CR */ + PORTCR(167, 0xe60520a7), /* PORT167CR */ + PORTCR(168, 0xe60520a8), /* PORT168CR */ + PORTCR(169, 0xe60520a9), /* PORT169CR */ + PORTCR(170, 0xe60520aa), /* PORT170CR */ + PORTCR(171, 0xe60520ab), /* PORT171CR */ + PORTCR(172, 0xe60520ac), /* PORT172CR */ + PORTCR(173, 0xe60520ad), /* PORT173CR */ + PORTCR(174, 0xe60520ae), /* PORT174CR */ + PORTCR(175, 0xe60520af), /* PORT175CR */ + PORTCR(176, 0xe60520b0), /* PORT176CR */ + PORTCR(177, 0xe60520b1), /* PORT177CR */ + PORTCR(178, 0xe60520b2), /* PORT178CR */ + PORTCR(179, 0xe60520b3), /* PORT179CR */ + PORTCR(180, 0xe60520b4), /* PORT180CR */ + PORTCR(181, 0xe60520b5), /* PORT181CR */ + PORTCR(182, 0xe60520b6), /* PORT182CR */ + PORTCR(183, 0xe60520b7), /* PORT183CR */ + PORTCR(184, 0xe60520b8), /* PORT184CR */ + PORTCR(185, 0xe60520b9), /* PORT185CR */ + PORTCR(186, 0xe60520ba), /* PORT186CR */ + PORTCR(187, 0xe60520bb), /* PORT187CR */ + PORTCR(188, 0xe60520bc), /* PORT188CR */ + PORTCR(189, 0xe60520bd), /* PORT189CR */ + PORTCR(190, 0xe60520be), /* PORT190CR */ + PORTCR(191, 0xe60520bf), /* PORT191CR */ + PORTCR(192, 0xe60520c0), /* PORT192CR */ + PORTCR(193, 0xe60520c1), /* PORT193CR */ + PORTCR(194, 0xe60520c2), /* PORT194CR */ + PORTCR(195, 0xe60520c3), /* PORT195CR */ + PORTCR(196, 0xe60520c4), /* PORT196CR */ + PORTCR(197, 0xe60520c5), /* PORT197CR */ + PORTCR(198, 0xe60520c6), /* PORT198CR */ + PORTCR(199, 0xe60520c7), /* PORT199CR */ + PORTCR(200, 0xe60520c8), /* PORT200CR */ + PORTCR(201, 0xe60520c9), /* PORT201CR */ + PORTCR(202, 0xe60520ca), /* PORT202CR */ + PORTCR(203, 0xe60520cb), /* PORT203CR */ + PORTCR(204, 0xe60520cc), /* PORT204CR */ + PORTCR(205, 0xe60520cd), /* PORT205CR */ + PORTCR(206, 0xe60520ce), /* PORT206CR */ + PORTCR(207, 0xe60520cf), /* PORT207CR */ + PORTCR(208, 0xe60520d0), /* PORT208CR */ + PORTCR(209, 0xe60520d1), /* PORT209CR */ + + PORTCR(210, 0xe60530d2), /* PORT210CR */ + PORTCR(211, 0xe60530d3), /* PORT211CR */ + + { PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1) { + MSEL1CR_31_0, MSEL1CR_31_1, + MSEL1CR_30_0, MSEL1CR_30_1, + MSEL1CR_29_0, MSEL1CR_29_1, + MSEL1CR_28_0, MSEL1CR_28_1, + MSEL1CR_27_0, MSEL1CR_27_1, + MSEL1CR_26_0, MSEL1CR_26_1, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + MSEL1CR_16_0, MSEL1CR_16_1, + MSEL1CR_15_0, MSEL1CR_15_1, + MSEL1CR_14_0, MSEL1CR_14_1, + MSEL1CR_13_0, MSEL1CR_13_1, + MSEL1CR_12_0, MSEL1CR_12_1, + 0, 0, 0, 0, + MSEL1CR_9_0, MSEL1CR_9_1, + 0, 0, + MSEL1CR_7_0, MSEL1CR_7_1, + MSEL1CR_6_0, MSEL1CR_6_1, + MSEL1CR_5_0, MSEL1CR_5_1, + MSEL1CR_4_0, MSEL1CR_4_1, + MSEL1CR_3_0, MSEL1CR_3_1, + MSEL1CR_2_0, MSEL1CR_2_1, + 0, 0, + MSEL1CR_0_0, MSEL1CR_0_1, + } + }, + { PINMUX_CFG_REG("MSEL3CR", 0xE6058020, 32, 1) { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + MSEL3CR_15_0, MSEL3CR_15_1, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + MSEL3CR_6_0, MSEL3CR_6_1, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, + } + }, + { PINMUX_CFG_REG("MSEL4CR", 0xE6058024, 32, 1) { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + MSEL4CR_19_0, MSEL4CR_19_1, + MSEL4CR_18_0, MSEL4CR_18_1, + 0, 0, 0, 0, + MSEL4CR_15_0, MSEL4CR_15_1, + 0, 0, 0, 0, 0, 0, 0, 0, + MSEL4CR_10_0, MSEL4CR_10_1, + 0, 0, 0, 0, 0, 0, + MSEL4CR_6_0, MSEL4CR_6_1, + 0, 0, + MSEL4CR_4_0, MSEL4CR_4_1, + 0, 0, 0, 0, + MSEL4CR_1_0, MSEL4CR_1_1, + 0, 0, + } + }, + { PINMUX_CFG_REG("MSEL5CR", 0xE6058028, 32, 1) { + MSEL5CR_31_0, MSEL5CR_31_1, + MSEL5CR_30_0, MSEL5CR_30_1, + MSEL5CR_29_0, MSEL5CR_29_1, + 0, 0, + MSEL5CR_27_0, MSEL5CR_27_1, + 0, 0, + MSEL5CR_25_0, MSEL5CR_25_1, + 0, 0, + MSEL5CR_23_0, MSEL5CR_23_1, + 0, 0, + MSEL5CR_21_0, MSEL5CR_21_1, + 0, 0, + MSEL5CR_19_0, MSEL5CR_19_1, + 0, 0, + MSEL5CR_17_0, MSEL5CR_17_1, + 0, 0, + MSEL5CR_15_0, MSEL5CR_15_1, + MSEL5CR_14_0, MSEL5CR_14_1, + MSEL5CR_13_0, MSEL5CR_13_1, + MSEL5CR_12_0, MSEL5CR_12_1, + MSEL5CR_11_0, MSEL5CR_11_1, + MSEL5CR_10_0, MSEL5CR_10_1, + 0, 0, + MSEL5CR_8_0, MSEL5CR_8_1, + MSEL5CR_7_0, MSEL5CR_7_1, + MSEL5CR_6_0, MSEL5CR_6_1, + MSEL5CR_5_0, MSEL5CR_5_1, + MSEL5CR_4_0, MSEL5CR_4_1, + MSEL5CR_3_0, MSEL5CR_3_1, + MSEL5CR_2_0, MSEL5CR_2_1, + 0, 0, + MSEL5CR_0_0, MSEL5CR_0_1, + } + }, + { }, +}; + +static struct pinmux_data_reg pinmux_data_regs[] = { + { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054800, 32) { + PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA, + PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA, + PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA, + PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA, + PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA, + PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA, + PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA, + PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA } + }, + { PINMUX_DATA_REG("PORTL063_032DR", 0xe6054804, 32) { + PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA, + PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA, + PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA, + PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA, + PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA, + PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA, + PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA, + PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA } + }, + { PINMUX_DATA_REG("PORTL095_064DR", 0xe6054808, 32) { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA, + PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA, + PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA, + PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA, + PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA } + }, + { PINMUX_DATA_REG("PORTD095_064DR", 0xe6055808, 32) { + PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA, + PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA, + PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0 } + }, + { PINMUX_DATA_REG("PORTD127_096DR", 0xe605580c, 32) { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, PORT114_DATA, PORT113_DATA, PORT112_DATA, + PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA, + PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA, + PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA, + PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA } + }, + { PINMUX_DATA_REG("PORTR127_096DR", 0xe605680C, 32) { + PORT127_DATA, PORT126_DATA, PORT125_DATA, PORT124_DATA, + PORT123_DATA, PORT122_DATA, PORT121_DATA, PORT120_DATA, + PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA, + PORT115_DATA, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0 } + }, + { PINMUX_DATA_REG("PORTR159_128DR", 0xe6056810, 32) { + PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA, + PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA, + PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA, + PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA, + PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA, + PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA, + PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA, + PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA } + }, + { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056814, 32) { + PORT191_DATA, PORT190_DATA, PORT189_DATA, PORT188_DATA, + PORT187_DATA, PORT186_DATA, PORT185_DATA, PORT184_DATA, + PORT183_DATA, PORT182_DATA, PORT181_DATA, PORT180_DATA, + PORT179_DATA, PORT178_DATA, PORT177_DATA, PORT176_DATA, + PORT175_DATA, PORT174_DATA, PORT173_DATA, PORT172_DATA, + PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA, + PORT167_DATA, PORT166_DATA, PORT165_DATA, PORT164_DATA, + PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA } + }, + { PINMUX_DATA_REG("PORTR223_192DR", 0xe6056818, 32) { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, PORT209_DATA, PORT208_DATA, + PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA, + PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA, + PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA, + PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA } + }, + { PINMUX_DATA_REG("PORTU223_192DR", 0xe6057818, 32) { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + PORT211_DATA, PORT210_DATA, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0 } + }, + { }, +}; + +static struct pinmux_irq pinmux_irqs[] = { + PINMUX_IRQ(evt2irq(0x0200), PORT2_FN0, PORT13_FN0), /* IRQ0A */ + PINMUX_IRQ(evt2irq(0x0220), PORT20_FN0), /* IRQ1A */ + PINMUX_IRQ(evt2irq(0x0240), PORT11_FN0, PORT12_FN0), /* IRQ2A */ + PINMUX_IRQ(evt2irq(0x0260), PORT10_FN0, PORT14_FN0), /* IRQ3A */ + PINMUX_IRQ(evt2irq(0x0280), PORT15_FN0, PORT172_FN0), /* IRQ4A */ + PINMUX_IRQ(evt2irq(0x02A0), PORT0_FN0, PORT1_FN0), /* IRQ5A */ + PINMUX_IRQ(evt2irq(0x02C0), PORT121_FN0, PORT173_FN0), /* IRQ6A */ + PINMUX_IRQ(evt2irq(0x02E0), PORT120_FN0, PORT209_FN0), /* IRQ7A */ + PINMUX_IRQ(evt2irq(0x0300), PORT119_FN0), /* IRQ8A */ + PINMUX_IRQ(evt2irq(0x0320), PORT118_FN0, PORT210_FN0), /* IRQ9A */ + PINMUX_IRQ(evt2irq(0x0340), PORT19_FN0), /* IRQ10A */ + PINMUX_IRQ(evt2irq(0x0360), PORT104_FN0), /* IRQ11A */ + PINMUX_IRQ(evt2irq(0x0380), PORT42_FN0, PORT97_FN0), /* IRQ12A */ + PINMUX_IRQ(evt2irq(0x03A0), PORT64_FN0, PORT98_FN0), /* IRQ13A */ + PINMUX_IRQ(evt2irq(0x03C0), PORT63_FN0, PORT99_FN0), /* IRQ14A */ + PINMUX_IRQ(evt2irq(0x03E0), PORT62_FN0, PORT100_FN0), /* IRQ15A */ + PINMUX_IRQ(evt2irq(0x3200), PORT68_FN0, PORT211_FN0), /* IRQ16A */ + PINMUX_IRQ(evt2irq(0x3220), PORT69_FN0), /* IRQ17A */ + PINMUX_IRQ(evt2irq(0x3240), PORT70_FN0), /* IRQ18A */ + PINMUX_IRQ(evt2irq(0x3260), PORT71_FN0), /* IRQ19A */ + PINMUX_IRQ(evt2irq(0x3280), PORT67_FN0), /* IRQ20A */ + PINMUX_IRQ(evt2irq(0x32A0), PORT202_FN0), /* IRQ21A */ + PINMUX_IRQ(evt2irq(0x32C0), PORT95_FN0), /* IRQ22A */ + PINMUX_IRQ(evt2irq(0x32E0), PORT96_FN0), /* IRQ23A */ + PINMUX_IRQ(evt2irq(0x3300), PORT180_FN0), /* IRQ24A */ + PINMUX_IRQ(evt2irq(0x3320), PORT38_FN0), /* IRQ25A */ + PINMUX_IRQ(evt2irq(0x3340), PORT58_FN0, PORT81_FN0), /* IRQ26A */ + PINMUX_IRQ(evt2irq(0x3360), PORT57_FN0, PORT168_FN0), /* IRQ27A */ + PINMUX_IRQ(evt2irq(0x3380), PORT56_FN0, PORT169_FN0), /* IRQ28A */ + PINMUX_IRQ(evt2irq(0x33A0), PORT50_FN0, PORT170_FN0), /* IRQ29A */ + PINMUX_IRQ(evt2irq(0x33C0), PORT49_FN0, PORT171_FN0), /* IRQ30A */ + PINMUX_IRQ(evt2irq(0x33E0), PORT41_FN0, PORT167_FN0), /* IRQ31A */ +}; + +static struct pinmux_info r8a7740_pinmux_info = { + .name = "r8a7740_pfc", + .reserved_id = PINMUX_RESERVED, + .data = { PINMUX_DATA_BEGIN, + PINMUX_DATA_END }, + .input = { PINMUX_INPUT_BEGIN, + PINMUX_INPUT_END }, + .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, + PINMUX_INPUT_PULLUP_END }, + .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, + PINMUX_INPUT_PULLDOWN_END }, + .output = { PINMUX_OUTPUT_BEGIN, + PINMUX_OUTPUT_END }, + .mark = { PINMUX_MARK_BEGIN, + PINMUX_MARK_END }, + .function = { PINMUX_FUNCTION_BEGIN, + PINMUX_FUNCTION_END }, + + .first_gpio = GPIO_PORT0, + .last_gpio = GPIO_FN_TRACEAUD_FROM_MEMC, + + .gpios = pinmux_gpios, + .cfg_regs = pinmux_config_regs, + .data_regs = pinmux_data_regs, + + .gpio_data = pinmux_data, + .gpio_data_size = ARRAY_SIZE(pinmux_data), + + .gpio_irq = pinmux_irqs, + .gpio_irq_size = ARRAY_SIZE(pinmux_irqs), +}; + +void r8a7740_pinmux_init(void) +{ + register_pinmux(&r8a7740_pinmux_info); +} diff --git a/arch/arm/cpu/armv7/rmobile/pfc-sh73a0.c b/arch/arm/cpu/armv7/rmobile/pfc-sh73a0.c new file mode 100644 index 0000000000..55dab7c138 --- /dev/null +++ b/arch/arm/cpu/armv7/rmobile/pfc-sh73a0.c @@ -0,0 +1,2807 @@ +/* + * sh73a0 processor support - PFC hardware block + * + * Copyright (C) 2010 Renesas Solutions Corp. + * Copyright (C) 2010 NISHIMOTO Hiroki + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the + * License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <common.h> +#include <sh_pfc.h> +#include <asm/arch/sh73a0-gpio.h> + +#define CPU_ALL_PORT(fn, pfx, sfx) \ + PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ + PORT_10(fn, pfx##2, sfx), PORT_10(fn, pfx##3, sfx), \ + PORT_10(fn, pfx##4, sfx), PORT_10(fn, pfx##5, sfx), \ + PORT_10(fn, pfx##6, sfx), PORT_10(fn, pfx##7, sfx), \ + PORT_10(fn, pfx##8, sfx), PORT_10(fn, pfx##9, sfx), \ + PORT_10(fn, pfx##10, sfx), \ + PORT_1(fn, pfx##110, sfx), PORT_1(fn, pfx##111, sfx), \ + PORT_1(fn, pfx##112, sfx), PORT_1(fn, pfx##113, sfx), \ + PORT_1(fn, pfx##114, sfx), PORT_1(fn, pfx##115, sfx), \ + PORT_1(fn, pfx##116, sfx), PORT_1(fn, pfx##117, sfx), \ + PORT_1(fn, pfx##118, sfx), \ + PORT_1(fn, pfx##128, sfx), PORT_1(fn, pfx##129, sfx), \ + PORT_10(fn, pfx##13, sfx), PORT_10(fn, pfx##14, sfx), \ + PORT_10(fn, pfx##15, sfx), \ + PORT_1(fn, pfx##160, sfx), PORT_1(fn, pfx##161, sfx), \ + PORT_1(fn, pfx##162, sfx), PORT_1(fn, pfx##163, sfx), \ + PORT_1(fn, pfx##164, sfx), \ + PORT_1(fn, pfx##192, sfx), PORT_1(fn, pfx##193, sfx), \ + PORT_1(fn, pfx##194, sfx), PORT_1(fn, pfx##195, sfx), \ + PORT_1(fn, pfx##196, sfx), PORT_1(fn, pfx##197, sfx), \ + PORT_1(fn, pfx##198, sfx), PORT_1(fn, pfx##199, sfx), \ + PORT_10(fn, pfx##20, sfx), PORT_10(fn, pfx##21, sfx), \ + PORT_10(fn, pfx##22, sfx), PORT_10(fn, pfx##23, sfx), \ + PORT_10(fn, pfx##24, sfx), PORT_10(fn, pfx##25, sfx), \ + PORT_10(fn, pfx##26, sfx), PORT_10(fn, pfx##27, sfx), \ + PORT_1(fn, pfx##280, sfx), PORT_1(fn, pfx##281, sfx), \ + PORT_1(fn, pfx##282, sfx), \ + PORT_1(fn, pfx##288, sfx), PORT_1(fn, pfx##289, sfx), \ + PORT_10(fn, pfx##29, sfx), PORT_10(fn, pfx##30, sfx) + +enum { + PINMUX_RESERVED = 0, + + PINMUX_DATA_BEGIN, + PORT_ALL(DATA), /* PORT0_DATA -> PORT309_DATA */ + PINMUX_DATA_END, + + PINMUX_INPUT_BEGIN, + PORT_ALL(IN), /* PORT0_IN -> PORT309_IN */ + PINMUX_INPUT_END, + + PINMUX_INPUT_PULLUP_BEGIN, + PORT_ALL(IN_PU), /* PORT0_IN_PU -> PORT309_IN_PU */ + PINMUX_INPUT_PULLUP_END, + + PINMUX_INPUT_PULLDOWN_BEGIN, + PORT_ALL(IN_PD), /* PORT0_IN_PD -> PORT309_IN_PD */ + PINMUX_INPUT_PULLDOWN_END, + + PINMUX_OUTPUT_BEGIN, + PORT_ALL(OUT), /* PORT0_OUT -> PORT309_OUT */ + PINMUX_OUTPUT_END, + + PINMUX_FUNCTION_BEGIN, + PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT309_FN_IN */ + PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT309_FN_OUT */ + PORT_ALL(FN0), /* PORT0_FN0 -> PORT309_FN0 */ + PORT_ALL(FN1), /* PORT0_FN1 -> PORT309_FN1 */ + PORT_ALL(FN2), /* PORT0_FN2 -> PORT309_FN2 */ + PORT_ALL(FN3), /* PORT0_FN3 -> PORT309_FN3 */ + PORT_ALL(FN4), /* PORT0_FN4 -> PORT309_FN4 */ + PORT_ALL(FN5), /* PORT0_FN5 -> PORT309_FN5 */ + PORT_ALL(FN6), /* PORT0_FN6 -> PORT309_FN6 */ + PORT_ALL(FN7), /* PORT0_FN7 -> PORT309_FN7 */ + + MSEL2CR_MSEL19_0, MSEL2CR_MSEL19_1, + MSEL2CR_MSEL18_0, MSEL2CR_MSEL18_1, + MSEL2CR_MSEL17_0, MSEL2CR_MSEL17_1, + MSEL2CR_MSEL16_0, MSEL2CR_MSEL16_1, + MSEL2CR_MSEL14_0, MSEL2CR_MSEL14_1, + MSEL2CR_MSEL13_0, MSEL2CR_MSEL13_1, + MSEL2CR_MSEL12_0, MSEL2CR_MSEL12_1, + MSEL2CR_MSEL11_0, MSEL2CR_MSEL11_1, + MSEL2CR_MSEL10_0, MSEL2CR_MSEL10_1, + MSEL2CR_MSEL9_0, MSEL2CR_MSEL9_1, + MSEL2CR_MSEL8_0, MSEL2CR_MSEL8_1, + MSEL2CR_MSEL7_0, MSEL2CR_MSEL7_1, + MSEL2CR_MSEL6_0, MSEL2CR_MSEL6_1, + MSEL2CR_MSEL4_0, MSEL2CR_MSEL4_1, + MSEL2CR_MSEL5_0, MSEL2CR_MSEL5_1, + MSEL2CR_MSEL3_0, MSEL2CR_MSEL3_1, + MSEL2CR_MSEL2_0, MSEL2CR_MSEL2_1, + MSEL2CR_MSEL1_0, MSEL2CR_MSEL1_1, + MSEL2CR_MSEL0_0, MSEL2CR_MSEL0_1, + MSEL3CR_MSEL28_0, MSEL3CR_MSEL28_1, + MSEL3CR_MSEL15_0, MSEL3CR_MSEL15_1, + MSEL3CR_MSEL11_0, MSEL3CR_MSEL11_1, + MSEL3CR_MSEL9_0, MSEL3CR_MSEL9_1, + MSEL3CR_MSEL6_0, MSEL3CR_MSEL6_1, + MSEL3CR_MSEL2_0, MSEL3CR_MSEL2_1, + MSEL4CR_MSEL29_0, MSEL4CR_MSEL29_1, + MSEL4CR_MSEL27_0, MSEL4CR_MSEL27_1, + MSEL4CR_MSEL26_0, MSEL4CR_MSEL26_1, + MSEL4CR_MSEL22_0, MSEL4CR_MSEL22_1, + MSEL4CR_MSEL21_0, MSEL4CR_MSEL21_1, + MSEL4CR_MSEL20_0, MSEL4CR_MSEL20_1, + MSEL4CR_MSEL19_0, MSEL4CR_MSEL19_1, + MSEL4CR_MSEL15_0, MSEL4CR_MSEL15_1, + MSEL4CR_MSEL13_0, MSEL4CR_MSEL13_1, + MSEL4CR_MSEL12_0, MSEL4CR_MSEL12_1, + MSEL4CR_MSEL11_0, MSEL4CR_MSEL11_1, + MSEL4CR_MSEL10_0, MSEL4CR_MSEL10_1, + MSEL4CR_MSEL9_0, MSEL4CR_MSEL9_1, + MSEL4CR_MSEL8_0, MSEL4CR_MSEL8_1, + MSEL4CR_MSEL7_0, MSEL4CR_MSEL7_1, + MSEL4CR_MSEL4_0, MSEL4CR_MSEL4_1, + MSEL4CR_MSEL1_0, MSEL4CR_MSEL1_1, + PINMUX_FUNCTION_END, + + PINMUX_MARK_BEGIN, + /* Hardware manual Table 25-1 (Function 0-7) */ + VBUS_0_MARK, + GPI0_MARK, + GPI1_MARK, + GPI2_MARK, + GPI3_MARK, + GPI4_MARK, + GPI5_MARK, + GPI6_MARK, + GPI7_MARK, + SCIFA7_RXD_MARK, + SCIFA7_CTS__MARK, + GPO7_MARK, MFG0_OUT2_MARK, + GPO6_MARK, MFG1_OUT2_MARK, + GPO5_MARK, SCIFA0_SCK_MARK, FSICOSLDT3_MARK, PORT16_VIO_CKOR_MARK, + SCIFA0_TXD_MARK, + SCIFA7_TXD_MARK, + SCIFA7_RTS__MARK, PORT19_VIO_CKO2_MARK, + GPO0_MARK, + GPO1_MARK, + GPO2_MARK, STATUS0_MARK, + GPO3_MARK, STATUS1_MARK, + GPO4_MARK, STATUS2_MARK, + VINT_MARK, + TCKON_MARK, + XDVFS1_MARK, PORT27_I2C_SCL2_MARK, PORT27_I2C_SCL3_MARK, \ + MFG0_OUT1_MARK, PORT27_IROUT_MARK, + XDVFS2_MARK, PORT28_I2C_SDA2_MARK, PORT28_I2C_SDA3_MARK, \ + PORT28_TPU1TO1_MARK, + SIM_RST_MARK, PORT29_TPU1TO1_MARK, + SIM_CLK_MARK, PORT30_VIO_CKOR_MARK, + SIM_D_MARK, PORT31_IROUT_MARK, + SCIFA4_TXD_MARK, + SCIFA4_RXD_MARK, XWUP_MARK, + SCIFA4_RTS__MARK, + SCIFA4_CTS__MARK, + FSIBOBT_MARK, FSIBIBT_MARK, + FSIBOLR_MARK, FSIBILR_MARK, + FSIBOSLD_MARK, + FSIBISLD_MARK, + VACK_MARK, + XTAL1L_MARK, + SCIFA0_RTS__MARK, FSICOSLDT2_MARK, + SCIFA0_RXD_MARK, + SCIFA0_CTS__MARK, FSICOSLDT1_MARK, + FSICOBT_MARK, FSICIBT_MARK, FSIDOBT_MARK, FSIDIBT_MARK, + FSICOLR_MARK, FSICILR_MARK, FSIDOLR_MARK, FSIDILR_MARK, + FSICOSLD_MARK, PORT47_FSICSPDIF_MARK, + FSICISLD_MARK, FSIDISLD_MARK, + FSIACK_MARK, PORT49_IRDA_OUT_MARK, PORT49_IROUT_MARK, FSIAOMC_MARK, + FSIAOLR_MARK, BBIF2_TSYNC2_MARK, TPU2TO2_MARK, FSIAILR_MARK, + + FSIAOBT_MARK, BBIF2_TSCK2_MARK, TPU2TO3_MARK, FSIAIBT_MARK, + FSIAOSLD_MARK, BBIF2_TXD2_MARK, + FSIASPDIF_MARK, PORT53_IRDA_IN_MARK, TPU3TO3_MARK, FSIBSPDIF_MARK, \ + PORT53_FSICSPDIF_MARK, + FSIBCK_MARK, PORT54_IRDA_FIRSEL_MARK, TPU3TO2_MARK, FSIBOMC_MARK, \ + FSICCK_MARK, FSICOMC_MARK, + FSIAISLD_MARK, TPU0TO0_MARK, + A0_MARK, BS__MARK, + A12_MARK, PORT58_KEYOUT7_MARK, TPU4TO2_MARK, + A13_MARK, PORT59_KEYOUT6_MARK, TPU0TO1_MARK, + A14_MARK, KEYOUT5_MARK, + A15_MARK, KEYOUT4_MARK, + A16_MARK, KEYOUT3_MARK, MSIOF0_SS1_MARK, + A17_MARK, KEYOUT2_MARK, MSIOF0_TSYNC_MARK, + A18_MARK, KEYOUT1_MARK, MSIOF0_TSCK_MARK, + A19_MARK, KEYOUT0_MARK, MSIOF0_TXD_MARK, + A20_MARK, KEYIN0_MARK, MSIOF0_RSCK_MARK, + A21_MARK, KEYIN1_MARK, MSIOF0_RSYNC_MARK, + A22_MARK, KEYIN2_MARK, MSIOF0_MCK0_MARK, + A23_MARK, KEYIN3_MARK, MSIOF0_MCK1_MARK, + A24_MARK, KEYIN4_MARK, MSIOF0_RXD_MARK, + A25_MARK, KEYIN5_MARK, MSIOF0_SS2_MARK, + A26_MARK, KEYIN6_MARK, + KEYIN7_MARK, + D0_NAF0_MARK, + D1_NAF1_MARK, + D2_NAF2_MARK, + D3_NAF3_MARK, + D4_NAF4_MARK, + D5_NAF5_MARK, + D6_NAF6_MARK, + D7_NAF7_MARK, + D8_NAF8_MARK, + D9_NAF9_MARK, + D10_NAF10_MARK, + D11_NAF11_MARK, + D12_NAF12_MARK, + D13_NAF13_MARK, + D14_NAF14_MARK, + D15_NAF15_MARK, + CS4__MARK, + CS5A__MARK, PORT91_RDWR_MARK, + CS5B__MARK, FCE1__MARK, + CS6B__MARK, DACK0_MARK, + FCE0__MARK, CS6A__MARK, + WAIT__MARK, DREQ0_MARK, + RD__FSC_MARK, + WE0__FWE_MARK, RDWR_FWE_MARK, + WE1__MARK, + FRB_MARK, + CKO_MARK, + NBRSTOUT__MARK, + NBRST__MARK, + BBIF2_TXD_MARK, + BBIF2_RXD_MARK, + BBIF2_SYNC_MARK, + BBIF2_SCK_MARK, + SCIFA3_CTS__MARK, MFG3_IN2_MARK, + SCIFA3_RXD_MARK, MFG3_IN1_MARK, + BBIF1_SS2_MARK, SCIFA3_RTS__MARK, MFG3_OUT1_MARK, + SCIFA3_TXD_MARK, + HSI_RX_DATA_MARK, BBIF1_RXD_MARK, + HSI_TX_WAKE_MARK, BBIF1_TSCK_MARK, + HSI_TX_DATA_MARK, BBIF1_TSYNC_MARK, + HSI_TX_READY_MARK, BBIF1_TXD_MARK, + HSI_RX_READY_MARK, BBIF1_RSCK_MARK, PORT115_I2C_SCL2_MARK, \ + PORT115_I2C_SCL3_MARK, + HSI_RX_WAKE_MARK, BBIF1_RSYNC_MARK, PORT116_I2C_SDA2_MARK, \ + PORT116_I2C_SDA3_MARK, + HSI_RX_FLAG_MARK, BBIF1_SS1_MARK, BBIF1_FLOW_MARK, + HSI_TX_FLAG_MARK, + VIO_VD_MARK, PORT128_LCD2VSYN_MARK, VIO2_VD_MARK, LCD2D0_MARK, + + VIO_HD_MARK, PORT129_LCD2HSYN_MARK, PORT129_LCD2CS__MARK, \ + VIO2_HD_MARK, LCD2D1_MARK, + VIO_D0_MARK, PORT130_MSIOF2_RXD_MARK, LCD2D10_MARK, + VIO_D1_MARK, PORT131_KEYOUT6_MARK, PORT131_MSIOF2_SS1_MARK, \ + PORT131_KEYOUT11_MARK, LCD2D11_MARK, + VIO_D2_MARK, PORT132_KEYOUT7_MARK, PORT132_MSIOF2_SS2_MARK, \ + PORT132_KEYOUT10_MARK, LCD2D12_MARK, + VIO_D3_MARK, MSIOF2_TSYNC_MARK, LCD2D13_MARK, + VIO_D4_MARK, MSIOF2_TXD_MARK, LCD2D14_MARK, + VIO_D5_MARK, MSIOF2_TSCK_MARK, LCD2D15_MARK, + VIO_D6_MARK, PORT136_KEYOUT8_MARK, LCD2D16_MARK, + VIO_D7_MARK, PORT137_KEYOUT9_MARK, LCD2D17_MARK, + VIO_D8_MARK, PORT138_KEYOUT8_MARK, VIO2_D0_MARK, LCD2D6_MARK, + VIO_D9_MARK, PORT139_KEYOUT9_MARK, VIO2_D1_MARK, LCD2D7_MARK, + VIO_D10_MARK, TPU0TO2_MARK, VIO2_D2_MARK, LCD2D8_MARK, + VIO_D11_MARK, TPU0TO3_MARK, VIO2_D3_MARK, LCD2D9_MARK, + VIO_D12_MARK, PORT142_KEYOUT10_MARK, VIO2_D4_MARK, LCD2D2_MARK, + VIO_D13_MARK, PORT143_KEYOUT11_MARK, PORT143_KEYOUT6_MARK, \ + VIO2_D5_MARK, LCD2D3_MARK, + VIO_D14_MARK, PORT144_KEYOUT7_MARK, VIO2_D6_MARK, LCD2D4_MARK, + VIO_D15_MARK, TPU1TO3_MARK, PORT145_LCD2DISP_MARK, \ + PORT145_LCD2RS_MARK, VIO2_D7_MARK, LCD2D5_MARK, + VIO_CLK_MARK, LCD2DCK_MARK, PORT146_LCD2WR__MARK, VIO2_CLK_MARK, \ + LCD2D18_MARK, + VIO_FIELD_MARK, LCD2RD__MARK, VIO2_FIELD_MARK, LCD2D19_MARK, + VIO_CKO_MARK, + A27_MARK, PORT149_RDWR_MARK, MFG0_IN1_MARK, PORT149_KEYOUT9_MARK, + MFG0_IN2_MARK, + TS_SPSYNC3_MARK, MSIOF2_RSCK_MARK, + TS_SDAT3_MARK, MSIOF2_RSYNC_MARK, + TPU1TO2_MARK, TS_SDEN3_MARK, PORT153_MSIOF2_SS1_MARK, + SCIFA2_TXD1_MARK, MSIOF2_MCK0_MARK, + SCIFA2_RXD1_MARK, MSIOF2_MCK1_MARK, + SCIFA2_RTS1__MARK, PORT156_MSIOF2_SS2_MARK, + SCIFA2_CTS1__MARK, PORT157_MSIOF2_RXD_MARK, + DINT__MARK, SCIFA2_SCK1_MARK, TS_SCK3_MARK, + PORT159_SCIFB_SCK_MARK, PORT159_SCIFA5_SCK_MARK, NMI_MARK, + PORT160_SCIFB_TXD_MARK, PORT160_SCIFA5_TXD_MARK, + PORT161_SCIFB_CTS__MARK, PORT161_SCIFA5_CTS__MARK, + PORT162_SCIFB_RXD_MARK, PORT162_SCIFA5_RXD_MARK, + PORT163_SCIFB_RTS__MARK, PORT163_SCIFA5_RTS__MARK, TPU3TO0_MARK, + LCDD0_MARK, + LCDD1_MARK, PORT193_SCIFA5_CTS__MARK, BBIF2_TSYNC1_MARK, + LCDD2_MARK, PORT194_SCIFA5_RTS__MARK, BBIF2_TSCK1_MARK, + LCDD3_MARK, PORT195_SCIFA5_RXD_MARK, BBIF2_TXD1_MARK, + LCDD4_MARK, PORT196_SCIFA5_TXD_MARK, + LCDD5_MARK, PORT197_SCIFA5_SCK_MARK, MFG2_OUT2_MARK, TPU2TO1_MARK, + LCDD6_MARK, + LCDD7_MARK, TPU4TO1_MARK, MFG4_OUT2_MARK, + LCDD8_MARK, D16_MARK, + LCDD9_MARK, D17_MARK, + LCDD10_MARK, D18_MARK, + LCDD11_MARK, D19_MARK, + LCDD12_MARK, D20_MARK, + LCDD13_MARK, D21_MARK, + LCDD14_MARK, D22_MARK, + LCDD15_MARK, PORT207_MSIOF0L_SS1_MARK, D23_MARK, + LCDD16_MARK, PORT208_MSIOF0L_SS2_MARK, D24_MARK, + LCDD17_MARK, D25_MARK, + LCDD18_MARK, DREQ2_MARK, PORT210_MSIOF0L_SS1_MARK, D26_MARK, + LCDD19_MARK, PORT211_MSIOF0L_SS2_MARK, D27_MARK, + LCDD20_MARK, TS_SPSYNC1_MARK, MSIOF0L_MCK0_MARK, D28_MARK, + LCDD21_MARK, TS_SDAT1_MARK, MSIOF0L_MCK1_MARK, D29_MARK, + LCDD22_MARK, TS_SDEN1_MARK, MSIOF0L_RSCK_MARK, D30_MARK, + LCDD23_MARK, TS_SCK1_MARK, MSIOF0L_RSYNC_MARK, D31_MARK, + LCDDCK_MARK, LCDWR__MARK, + LCDRD__MARK, DACK2_MARK, PORT217_LCD2RS_MARK, MSIOF0L_TSYNC_MARK, \ + VIO2_FIELD3_MARK, PORT217_LCD2DISP_MARK, + LCDHSYN_MARK, LCDCS__MARK, LCDCS2__MARK, DACK3_MARK, \ + PORT218_VIO_CKOR_MARK, + LCDDISP_MARK, LCDRS_MARK, PORT219_LCD2WR__MARK, DREQ3_MARK, \ + MSIOF0L_TSCK_MARK, VIO2_CLK3_MARK, LCD2DCK_2_MARK, + LCDVSYN_MARK, LCDVSYN2_MARK, + LCDLCLK_MARK, DREQ1_MARK, PORT221_LCD2CS__MARK, PWEN_MARK, \ + MSIOF0L_RXD_MARK, VIO2_HD3_MARK, PORT221_LCD2HSYN_MARK, + LCDDON_MARK, LCDDON2_MARK, DACK1_MARK, OVCN_MARK, MSIOF0L_TXD_MARK, \ + VIO2_VD3_MARK, PORT222_LCD2VSYN_MARK, + + SCIFA1_TXD_MARK, OVCN2_MARK, + EXTLP_MARK, SCIFA1_SCK_MARK, PORT226_VIO_CKO2_MARK, + SCIFA1_RTS__MARK, IDIN_MARK, + SCIFA1_RXD_MARK, + SCIFA1_CTS__MARK, MFG1_IN1_MARK, + MSIOF1_TXD_MARK, SCIFA2_TXD2_MARK, + MSIOF1_TSYNC_MARK, SCIFA2_CTS2__MARK, + MSIOF1_TSCK_MARK, SCIFA2_SCK2_MARK, + MSIOF1_RXD_MARK, SCIFA2_RXD2_MARK, + MSIOF1_RSCK_MARK, SCIFA2_RTS2__MARK, VIO2_CLK2_MARK, LCD2D20_MARK, + MSIOF1_RSYNC_MARK, MFG1_IN2_MARK, VIO2_VD2_MARK, LCD2D21_MARK, + MSIOF1_MCK0_MARK, PORT236_I2C_SDA2_MARK, + MSIOF1_MCK1_MARK, PORT237_I2C_SCL2_MARK, + MSIOF1_SS1_MARK, VIO2_FIELD2_MARK, LCD2D22_MARK, + MSIOF1_SS2_MARK, VIO2_HD2_MARK, LCD2D23_MARK, + SCIFA6_TXD_MARK, + PORT241_IRDA_OUT_MARK, PORT241_IROUT_MARK, MFG4_OUT1_MARK, TPU4TO0_MARK, + PORT242_IRDA_IN_MARK, MFG4_IN2_MARK, + PORT243_IRDA_FIRSEL_MARK, PORT243_VIO_CKO2_MARK, + PORT244_SCIFA5_CTS__MARK, MFG2_IN1_MARK, PORT244_SCIFB_CTS__MARK, \ + MSIOF2R_RXD_MARK, + PORT245_SCIFA5_RTS__MARK, MFG2_IN2_MARK, PORT245_SCIFB_RTS__MARK, \ + MSIOF2R_TXD_MARK, + PORT246_SCIFA5_RXD_MARK, MFG1_OUT1_MARK, PORT246_SCIFB_RXD_MARK, \ + TPU1TO0_MARK, + PORT247_SCIFA5_TXD_MARK, MFG3_OUT2_MARK, PORT247_SCIFB_TXD_MARK, \ + TPU3TO1_MARK, + PORT248_SCIFA5_SCK_MARK, MFG2_OUT1_MARK, PORT248_SCIFB_SCK_MARK, \ + TPU2TO0_MARK, PORT248_I2C_SCL3_MARK, MSIOF2R_TSCK_MARK, + PORT249_IROUT_MARK, MFG4_IN1_MARK, PORT249_I2C_SDA3_MARK, \ + MSIOF2R_TSYNC_MARK, + SDHICLK0_MARK, + SDHICD0_MARK, + SDHID0_0_MARK, + SDHID0_1_MARK, + SDHID0_2_MARK, + SDHID0_3_MARK, + SDHICMD0_MARK, + SDHIWP0_MARK, + SDHICLK1_MARK, + SDHID1_0_MARK, TS_SPSYNC2_MARK, + SDHID1_1_MARK, TS_SDAT2_MARK, + SDHID1_2_MARK, TS_SDEN2_MARK, + SDHID1_3_MARK, TS_SCK2_MARK, + SDHICMD1_MARK, + SDHICLK2_MARK, + SDHID2_0_MARK, TS_SPSYNC4_MARK, + SDHID2_1_MARK, TS_SDAT4_MARK, + SDHID2_2_MARK, TS_SDEN4_MARK, + SDHID2_3_MARK, TS_SCK4_MARK, + SDHICMD2_MARK, + MMCCLK0_MARK, + MMCD0_0_MARK, + MMCD0_1_MARK, + MMCD0_2_MARK, + MMCD0_3_MARK, + MMCD0_4_MARK, TS_SPSYNC5_MARK, + MMCD0_5_MARK, TS_SDAT5_MARK, + MMCD0_6_MARK, TS_SDEN5_MARK, + MMCD0_7_MARK, TS_SCK5_MARK, + MMCCMD0_MARK, + RESETOUTS__MARK, EXTAL2OUT_MARK, + MCP_WAIT__MCP_FRB_MARK, + MCP_CKO_MARK, MMCCLK1_MARK, + MCP_D15_MCP_NAF15_MARK, + MCP_D14_MCP_NAF14_MARK, + MCP_D13_MCP_NAF13_MARK, + MCP_D12_MCP_NAF12_MARK, + MCP_D11_MCP_NAF11_MARK, + MCP_D10_MCP_NAF10_MARK, + MCP_D9_MCP_NAF9_MARK, + MCP_D8_MCP_NAF8_MARK, MMCCMD1_MARK, + MCP_D7_MCP_NAF7_MARK, MMCD1_7_MARK, + + MCP_D6_MCP_NAF6_MARK, MMCD1_6_MARK, + MCP_D5_MCP_NAF5_MARK, MMCD1_5_MARK, + MCP_D4_MCP_NAF4_MARK, MMCD1_4_MARK, + MCP_D3_MCP_NAF3_MARK, MMCD1_3_MARK, + MCP_D2_MCP_NAF2_MARK, MMCD1_2_MARK, + MCP_D1_MCP_NAF1_MARK, MMCD1_1_MARK, + MCP_D0_MCP_NAF0_MARK, MMCD1_0_MARK, + MCP_NBRSTOUT__MARK, + MCP_WE0__MCP_FWE_MARK, MCP_RDWR_MCP_FWE_MARK, + + /* MSEL2 special cases */ + TSIF2_TS_XX1_MARK, + TSIF2_TS_XX2_MARK, + TSIF2_TS_XX3_MARK, + TSIF2_TS_XX4_MARK, + TSIF2_TS_XX5_MARK, + TSIF1_TS_XX1_MARK, + TSIF1_TS_XX2_MARK, + TSIF1_TS_XX3_MARK, + TSIF1_TS_XX4_MARK, + TSIF1_TS_XX5_MARK, + TSIF0_TS_XX1_MARK, + TSIF0_TS_XX2_MARK, + TSIF0_TS_XX3_MARK, + TSIF0_TS_XX4_MARK, + TSIF0_TS_XX5_MARK, + MST1_TS_XX1_MARK, + MST1_TS_XX2_MARK, + MST1_TS_XX3_MARK, + MST1_TS_XX4_MARK, + MST1_TS_XX5_MARK, + MST0_TS_XX1_MARK, + MST0_TS_XX2_MARK, + MST0_TS_XX3_MARK, + MST0_TS_XX4_MARK, + MST0_TS_XX5_MARK, + + /* MSEL3 special cases */ + SDHI0_VCCQ_MC0_ON_MARK, + SDHI0_VCCQ_MC0_OFF_MARK, + DEBUG_MON_VIO_MARK, + DEBUG_MON_LCDD_MARK, + LCDC_LCDC0_MARK, + LCDC_LCDC1_MARK, + + /* MSEL4 special cases */ + IRQ9_MEM_INT_MARK, + IRQ9_MCP_INT_MARK, + A11_MARK, + KEYOUT8_MARK, + TPU4TO3_MARK, + RESETA_N_PU_ON_MARK, + RESETA_N_PU_OFF_MARK, + EDBGREQ_PD_MARK, + EDBGREQ_PU_MARK, + + /* Functions with pull-ups */ + KEYIN0_PU_MARK, + KEYIN1_PU_MARK, + KEYIN2_PU_MARK, + KEYIN3_PU_MARK, + KEYIN4_PU_MARK, + KEYIN5_PU_MARK, + KEYIN6_PU_MARK, + KEYIN7_PU_MARK, + SDHICD0_PU_MARK, + SDHID0_0_PU_MARK, + SDHID0_1_PU_MARK, + SDHID0_2_PU_MARK, + SDHID0_3_PU_MARK, + SDHICMD0_PU_MARK, + SDHIWP0_PU_MARK, + SDHID1_0_PU_MARK, + SDHID1_1_PU_MARK, + SDHID1_2_PU_MARK, + SDHID1_3_PU_MARK, + SDHICMD1_PU_MARK, + SDHID2_0_PU_MARK, + SDHID2_1_PU_MARK, + SDHID2_2_PU_MARK, + SDHID2_3_PU_MARK, + SDHICMD2_PU_MARK, + MMCCMD0_PU_MARK, + MMCCMD1_PU_MARK, + MMCD0_0_PU_MARK, + MMCD0_1_PU_MARK, + MMCD0_2_PU_MARK, + MMCD0_3_PU_MARK, + MMCD0_4_PU_MARK, + MMCD0_5_PU_MARK, + MMCD0_6_PU_MARK, + MMCD0_7_PU_MARK, + FSIBISLD_PU_MARK, + FSIACK_PU_MARK, + FSIAILR_PU_MARK, + FSIAIBT_PU_MARK, + FSIAISLD_PU_MARK, + + PINMUX_MARK_END, +}; + +static unsigned short pinmux_data[] = { + /* specify valid pin states for each pin in GPIO mode */ + + /* Table 25-1 (I/O and Pull U/D) */ + PORT_DATA_I_PD(0), + PORT_DATA_I_PU(1), + PORT_DATA_I_PU(2), + PORT_DATA_I_PU(3), + PORT_DATA_I_PU(4), + PORT_DATA_I_PU(5), + PORT_DATA_I_PU(6), + PORT_DATA_I_PU(7), + PORT_DATA_I_PU(8), + PORT_DATA_I_PD(9), + PORT_DATA_I_PD(10), + PORT_DATA_I_PU_PD(11), + PORT_DATA_IO_PU_PD(12), + PORT_DATA_IO_PU_PD(13), + PORT_DATA_IO_PU_PD(14), + PORT_DATA_IO_PU_PD(15), + PORT_DATA_IO_PD(16), + PORT_DATA_IO_PD(17), + PORT_DATA_IO_PU(18), + PORT_DATA_IO_PU(19), + PORT_DATA_O(20), + PORT_DATA_O(21), + PORT_DATA_O(22), + PORT_DATA_O(23), + PORT_DATA_O(24), + PORT_DATA_I_PD(25), + PORT_DATA_I_PD(26), + PORT_DATA_IO_PU(27), + PORT_DATA_IO_PU(28), + PORT_DATA_IO_PD(29), + PORT_DATA_IO_PD(30), + PORT_DATA_IO_PU(31), + PORT_DATA_IO_PD(32), + PORT_DATA_I_PU_PD(33), + PORT_DATA_IO_PD(34), + PORT_DATA_I_PU_PD(35), + PORT_DATA_IO_PD(36), + PORT_DATA_IO(37), + PORT_DATA_O(38), + PORT_DATA_I_PU(39), + PORT_DATA_I_PU_PD(40), + PORT_DATA_O(41), + PORT_DATA_IO_PD(42), + PORT_DATA_IO_PU_PD(43), + PORT_DATA_IO_PU_PD(44), + PORT_DATA_IO_PD(45), + PORT_DATA_IO_PD(46), + PORT_DATA_IO_PD(47), + PORT_DATA_I_PD(48), + PORT_DATA_IO_PU_PD(49), + PORT_DATA_IO_PD(50), + + PORT_DATA_IO_PD(51), + PORT_DATA_O(52), + PORT_DATA_IO_PU_PD(53), + PORT_DATA_IO_PU_PD(54), + PORT_DATA_IO_PD(55), + PORT_DATA_I_PU_PD(56), + PORT_DATA_IO(57), + PORT_DATA_IO(58), + PORT_DATA_IO(59), + PORT_DATA_IO(60), + PORT_DATA_IO(61), + PORT_DATA_IO_PD(62), + PORT_DATA_IO_PD(63), + PORT_DATA_IO_PU_PD(64), + PORT_DATA_IO_PD(65), + PORT_DATA_IO_PU_PD(66), + PORT_DATA_IO_PU_PD(67), + PORT_DATA_IO_PU_PD(68), + PORT_DATA_IO_PU_PD(69), + PORT_DATA_IO_PU_PD(70), + PORT_DATA_IO_PU_PD(71), + PORT_DATA_IO_PU_PD(72), + PORT_DATA_I_PU_PD(73), + PORT_DATA_IO_PU(74), + PORT_DATA_IO_PU(75), + PORT_DATA_IO_PU(76), + PORT_DATA_IO_PU(77), + PORT_DATA_IO_PU(78), + PORT_DATA_IO_PU(79), + PORT_DATA_IO_PU(80), + PORT_DATA_IO_PU(81), + PORT_DATA_IO_PU(82), + PORT_DATA_IO_PU(83), + PORT_DATA_IO_PU(84), + PORT_DATA_IO_PU(85), + PORT_DATA_IO_PU(86), + PORT_DATA_IO_PU(87), + PORT_DATA_IO_PU(88), + PORT_DATA_IO_PU(89), + PORT_DATA_O(90), + PORT_DATA_IO_PU(91), + PORT_DATA_O(92), + PORT_DATA_IO_PU(93), + PORT_DATA_O(94), + PORT_DATA_I_PU_PD(95), + PORT_DATA_IO(96), + PORT_DATA_IO(97), + PORT_DATA_IO(98), + PORT_DATA_I_PU(99), + PORT_DATA_O(100), + PORT_DATA_O(101), + PORT_DATA_I_PU(102), + PORT_DATA_IO_PD(103), + PORT_DATA_I_PU_PD(104), + PORT_DATA_I_PD(105), + PORT_DATA_I_PD(106), + PORT_DATA_I_PU_PD(107), + PORT_DATA_I_PU_PD(108), + PORT_DATA_IO_PD(109), + PORT_DATA_IO_PD(110), + PORT_DATA_IO_PU_PD(111), + PORT_DATA_IO_PU_PD(112), + PORT_DATA_IO_PU_PD(113), + PORT_DATA_IO_PD(114), + PORT_DATA_IO_PU(115), + PORT_DATA_IO_PU(116), + PORT_DATA_IO_PU_PD(117), + PORT_DATA_IO_PU_PD(118), + PORT_DATA_IO_PD(128), + + PORT_DATA_IO_PD(129), + PORT_DATA_IO_PU_PD(130), + PORT_DATA_IO_PD(131), + PORT_DATA_IO_PD(132), + PORT_DATA_IO_PD(133), + PORT_DATA_IO_PU_PD(134), + PORT_DATA_IO_PU_PD(135), + PORT_DATA_IO_PU_PD(136), + PORT_DATA_IO_PU_PD(137), + PORT_DATA_IO_PD(138), + PORT_DATA_IO_PD(139), + PORT_DATA_IO_PD(140), + PORT_DATA_IO_PD(141), + PORT_DATA_IO_PD(142), + PORT_DATA_IO_PD(143), + PORT_DATA_IO_PU_PD(144), + PORT_DATA_IO_PD(145), + PORT_DATA_IO_PU_PD(146), + PORT_DATA_IO_PU_PD(147), + PORT_DATA_IO_PU_PD(148), + PORT_DATA_IO_PU_PD(149), + PORT_DATA_I_PU_PD(150), + PORT_DATA_IO_PU_PD(151), + PORT_DATA_IO_PU_PD(152), + PORT_DATA_IO_PD(153), + PORT_DATA_IO_PD(154), + PORT_DATA_I_PU_PD(155), + PORT_DATA_IO_PU_PD(156), + PORT_DATA_I_PD(157), + PORT_DATA_IO_PD(158), + PORT_DATA_IO_PU_PD(159), + PORT_DATA_IO_PU_PD(160), + PORT_DATA_I_PU_PD(161), + PORT_DATA_I_PU_PD(162), + PORT_DATA_IO_PU_PD(163), + PORT_DATA_I_PU_PD(164), + PORT_DATA_IO_PD(192), + PORT_DATA_IO_PU_PD(193), + PORT_DATA_IO_PD(194), + PORT_DATA_IO_PU_PD(195), + PORT_DATA_IO_PD(196), + PORT_DATA_IO_PD(197), + PORT_DATA_IO_PD(198), + PORT_DATA_IO_PD(199), + PORT_DATA_IO_PU_PD(200), + PORT_DATA_IO_PU_PD(201), + PORT_DATA_IO_PU_PD(202), + PORT_DATA_IO_PU_PD(203), + PORT_DATA_IO_PU_PD(204), + PORT_DATA_IO_PU_PD(205), + PORT_DATA_IO_PU_PD(206), + PORT_DATA_IO_PD(207), + PORT_DATA_IO_PD(208), + PORT_DATA_IO_PD(209), + PORT_DATA_IO_PD(210), + PORT_DATA_IO_PD(211), + PORT_DATA_IO_PD(212), + PORT_DATA_IO_PD(213), + PORT_DATA_IO_PU_PD(214), + PORT_DATA_IO_PU_PD(215), + PORT_DATA_IO_PD(216), + PORT_DATA_IO_PD(217), + PORT_DATA_O(218), + PORT_DATA_IO_PD(219), + PORT_DATA_IO_PD(220), + PORT_DATA_IO_PU_PD(221), + PORT_DATA_IO_PU_PD(222), + PORT_DATA_I_PU_PD(223), + PORT_DATA_I_PU_PD(224), + + PORT_DATA_IO_PU_PD(225), + PORT_DATA_O(226), + PORT_DATA_IO_PU_PD(227), + PORT_DATA_I_PU_PD(228), + PORT_DATA_I_PD(229), + PORT_DATA_IO(230), + PORT_DATA_IO_PU_PD(231), + PORT_DATA_IO_PU_PD(232), + PORT_DATA_I_PU_PD(233), + PORT_DATA_IO_PU_PD(234), + PORT_DATA_IO_PU_PD(235), + PORT_DATA_IO_PU_PD(236), + PORT_DATA_IO_PD(237), + PORT_DATA_IO_PU_PD(238), + PORT_DATA_IO_PU_PD(239), + PORT_DATA_IO_PU_PD(240), + PORT_DATA_O(241), + PORT_DATA_I_PD(242), + PORT_DATA_IO_PU_PD(243), + PORT_DATA_IO_PU_PD(244), + PORT_DATA_IO_PU_PD(245), + PORT_DATA_IO_PU_PD(246), + PORT_DATA_IO_PU_PD(247), + PORT_DATA_IO_PU_PD(248), + PORT_DATA_IO_PU_PD(249), + PORT_DATA_IO_PU_PD(250), + PORT_DATA_IO_PU_PD(251), + PORT_DATA_IO_PU_PD(252), + PORT_DATA_IO_PU_PD(253), + PORT_DATA_IO_PU_PD(254), + PORT_DATA_IO_PU_PD(255), + PORT_DATA_IO_PU_PD(256), + PORT_DATA_IO_PU_PD(257), + PORT_DATA_IO_PU_PD(258), + PORT_DATA_IO_PU_PD(259), + PORT_DATA_IO_PU_PD(260), + PORT_DATA_IO_PU_PD(261), + PORT_DATA_IO_PU_PD(262), + PORT_DATA_IO_PU_PD(263), + PORT_DATA_IO_PU_PD(264), + PORT_DATA_IO_PU_PD(265), + PORT_DATA_IO_PU_PD(266), + PORT_DATA_IO_PU_PD(267), + PORT_DATA_IO_PU_PD(268), + PORT_DATA_IO_PU_PD(269), + PORT_DATA_IO_PU_PD(270), + PORT_DATA_IO_PU_PD(271), + PORT_DATA_IO_PU_PD(272), + PORT_DATA_IO_PU_PD(273), + PORT_DATA_IO_PU_PD(274), + PORT_DATA_IO_PU_PD(275), + PORT_DATA_IO_PU_PD(276), + PORT_DATA_IO_PU_PD(277), + PORT_DATA_IO_PU_PD(278), + PORT_DATA_IO_PU_PD(279), + PORT_DATA_IO_PU_PD(280), + PORT_DATA_O(281), + PORT_DATA_O(282), + PORT_DATA_I_PU(288), + PORT_DATA_IO_PU_PD(289), + PORT_DATA_IO_PU_PD(290), + PORT_DATA_IO_PU_PD(291), + PORT_DATA_IO_PU_PD(292), + PORT_DATA_IO_PU_PD(293), + PORT_DATA_IO_PU_PD(294), + PORT_DATA_IO_PU_PD(295), + PORT_DATA_IO_PU_PD(296), + PORT_DATA_IO_PU_PD(297), + PORT_DATA_IO_PU_PD(298), + + PORT_DATA_IO_PU_PD(299), + PORT_DATA_IO_PU_PD(300), + PORT_DATA_IO_PU_PD(301), + PORT_DATA_IO_PU_PD(302), + PORT_DATA_IO_PU_PD(303), + PORT_DATA_IO_PU_PD(304), + PORT_DATA_IO_PU_PD(305), + PORT_DATA_O(306), + PORT_DATA_O(307), + PORT_DATA_I_PU(308), + PORT_DATA_O(309), + + /* Table 25-1 (Function 0-7) */ + PINMUX_DATA(VBUS_0_MARK, PORT0_FN1), + PINMUX_DATA(GPI0_MARK, PORT1_FN1), + PINMUX_DATA(GPI1_MARK, PORT2_FN1), + PINMUX_DATA(GPI2_MARK, PORT3_FN1), + PINMUX_DATA(GPI3_MARK, PORT4_FN1), + PINMUX_DATA(GPI4_MARK, PORT5_FN1), + PINMUX_DATA(GPI5_MARK, PORT6_FN1), + PINMUX_DATA(GPI6_MARK, PORT7_FN1), + PINMUX_DATA(GPI7_MARK, PORT8_FN1), + PINMUX_DATA(SCIFA7_RXD_MARK, PORT12_FN2), + PINMUX_DATA(SCIFA7_CTS__MARK, PORT13_FN2), + PINMUX_DATA(GPO7_MARK, PORT14_FN1), \ + PINMUX_DATA(MFG0_OUT2_MARK, PORT14_FN4), + PINMUX_DATA(GPO6_MARK, PORT15_FN1), \ + PINMUX_DATA(MFG1_OUT2_MARK, PORT15_FN4), + PINMUX_DATA(GPO5_MARK, PORT16_FN1), \ + PINMUX_DATA(SCIFA0_SCK_MARK, PORT16_FN2), \ + PINMUX_DATA(FSICOSLDT3_MARK, PORT16_FN3), \ + PINMUX_DATA(PORT16_VIO_CKOR_MARK, PORT16_FN4), + PINMUX_DATA(SCIFA0_TXD_MARK, PORT17_FN2), + PINMUX_DATA(SCIFA7_TXD_MARK, PORT18_FN2), + PINMUX_DATA(SCIFA7_RTS__MARK, PORT19_FN2), \ + PINMUX_DATA(PORT19_VIO_CKO2_MARK, PORT19_FN3), + PINMUX_DATA(GPO0_MARK, PORT20_FN1), + PINMUX_DATA(GPO1_MARK, PORT21_FN1), + PINMUX_DATA(GPO2_MARK, PORT22_FN1), \ + PINMUX_DATA(STATUS0_MARK, PORT22_FN2), + PINMUX_DATA(GPO3_MARK, PORT23_FN1), \ + PINMUX_DATA(STATUS1_MARK, PORT23_FN2), + PINMUX_DATA(GPO4_MARK, PORT24_FN1), \ + PINMUX_DATA(STATUS2_MARK, PORT24_FN2), + PINMUX_DATA(VINT_MARK, PORT25_FN1), + PINMUX_DATA(TCKON_MARK, PORT26_FN1), + PINMUX_DATA(XDVFS1_MARK, PORT27_FN1), \ + PINMUX_DATA(PORT27_I2C_SCL2_MARK, PORT27_FN2, MSEL2CR_MSEL17_0, + MSEL2CR_MSEL16_1), \ + PINMUX_DATA(PORT27_I2C_SCL3_MARK, PORT27_FN3, MSEL2CR_MSEL19_0, + MSEL2CR_MSEL18_1), \ + PINMUX_DATA(MFG0_OUT1_MARK, PORT27_FN4), \ + PINMUX_DATA(PORT27_IROUT_MARK, PORT27_FN7), + PINMUX_DATA(XDVFS2_MARK, PORT28_FN1), \ + PINMUX_DATA(PORT28_I2C_SDA2_MARK, PORT28_FN2, MSEL2CR_MSEL17_0, + MSEL2CR_MSEL16_1), \ + PINMUX_DATA(PORT28_I2C_SDA3_MARK, PORT28_FN3, MSEL2CR_MSEL19_0, + MSEL2CR_MSEL18_1), \ + PINMUX_DATA(PORT28_TPU1TO1_MARK, PORT28_FN7), + PINMUX_DATA(SIM_RST_MARK, PORT29_FN1), \ + PINMUX_DATA(PORT29_TPU1TO1_MARK, PORT29_FN4), + PINMUX_DATA(SIM_CLK_MARK, PORT30_FN1), \ + PINMUX_DATA(PORT30_VIO_CKOR_MARK, PORT30_FN4), + PINMUX_DATA(SIM_D_MARK, PORT31_FN1), \ + PINMUX_DATA(PORT31_IROUT_MARK, PORT31_FN4), + PINMUX_DATA(SCIFA4_TXD_MARK, PORT32_FN2), + PINMUX_DATA(SCIFA4_RXD_MARK, PORT33_FN2), \ + PINMUX_DATA(XWUP_MARK, PORT33_FN3), + PINMUX_DATA(SCIFA4_RTS__MARK, PORT34_FN2), + PINMUX_DATA(SCIFA4_CTS__MARK, PORT35_FN2), + PINMUX_DATA(FSIBOBT_MARK, PORT36_FN1), \ + PINMUX_DATA(FSIBIBT_MARK, PORT36_FN2), + PINMUX_DATA(FSIBOLR_MARK, PORT37_FN1), \ + PINMUX_DATA(FSIBILR_MARK, PORT37_FN2), + PINMUX_DATA(FSIBOSLD_MARK, PORT38_FN1), + PINMUX_DATA(FSIBISLD_MARK, PORT39_FN1), + PINMUX_DATA(VACK_MARK, PORT40_FN1), + PINMUX_DATA(XTAL1L_MARK, PORT41_FN1), + PINMUX_DATA(SCIFA0_RTS__MARK, PORT42_FN2), \ + PINMUX_DATA(FSICOSLDT2_MARK, PORT42_FN3), + PINMUX_DATA(SCIFA0_RXD_MARK, PORT43_FN2), + PINMUX_DATA(SCIFA0_CTS__MARK, PORT44_FN2), \ + PINMUX_DATA(FSICOSLDT1_MARK, PORT44_FN3), + PINMUX_DATA(FSICOBT_MARK, PORT45_FN1), \ + PINMUX_DATA(FSICIBT_MARK, PORT45_FN2), \ + PINMUX_DATA(FSIDOBT_MARK, PORT45_FN3), \ + PINMUX_DATA(FSIDIBT_MARK, PORT45_FN4), + PINMUX_DATA(FSICOLR_MARK, PORT46_FN1), \ + PINMUX_DATA(FSICILR_MARK, PORT46_FN2), \ + PINMUX_DATA(FSIDOLR_MARK, PORT46_FN3), \ + PINMUX_DATA(FSIDILR_MARK, PORT46_FN4), + PINMUX_DATA(FSICOSLD_MARK, PORT47_FN1), \ + PINMUX_DATA(PORT47_FSICSPDIF_MARK, PORT47_FN2), + PINMUX_DATA(FSICISLD_MARK, PORT48_FN1), \ + PINMUX_DATA(FSIDISLD_MARK, PORT48_FN3), + PINMUX_DATA(FSIACK_MARK, PORT49_FN1), \ + PINMUX_DATA(PORT49_IRDA_OUT_MARK, PORT49_FN2, MSEL4CR_MSEL19_1), \ + PINMUX_DATA(PORT49_IROUT_MARK, PORT49_FN4), \ + PINMUX_DATA(FSIAOMC_MARK, PORT49_FN5), + PINMUX_DATA(FSIAOLR_MARK, PORT50_FN1), \ + PINMUX_DATA(BBIF2_TSYNC2_MARK, PORT50_FN2), \ + PINMUX_DATA(TPU2TO2_MARK, PORT50_FN3), \ + PINMUX_DATA(FSIAILR_MARK, PORT50_FN5), + + PINMUX_DATA(FSIAOBT_MARK, PORT51_FN1), \ + PINMUX_DATA(BBIF2_TSCK2_MARK, PORT51_FN2), \ + PINMUX_DATA(TPU2TO3_MARK, PORT51_FN3), \ + PINMUX_DATA(FSIAIBT_MARK, PORT51_FN5), + PINMUX_DATA(FSIAOSLD_MARK, PORT52_FN1), \ + PINMUX_DATA(BBIF2_TXD2_MARK, PORT52_FN2), + PINMUX_DATA(FSIASPDIF_MARK, PORT53_FN1), \ + PINMUX_DATA(PORT53_IRDA_IN_MARK, PORT53_FN2, MSEL4CR_MSEL19_1), \ + PINMUX_DATA(TPU3TO3_MARK, PORT53_FN3), \ + PINMUX_DATA(FSIBSPDIF_MARK, PORT53_FN5), \ + PINMUX_DATA(PORT53_FSICSPDIF_MARK, PORT53_FN6), + PINMUX_DATA(FSIBCK_MARK, PORT54_FN1), \ + PINMUX_DATA(PORT54_IRDA_FIRSEL_MARK, PORT54_FN2, MSEL4CR_MSEL19_1), \ + PINMUX_DATA(TPU3TO2_MARK, PORT54_FN3), \ + PINMUX_DATA(FSIBOMC_MARK, PORT54_FN5), \ + PINMUX_DATA(FSICCK_MARK, PORT54_FN6), \ + PINMUX_DATA(FSICOMC_MARK, PORT54_FN7), + PINMUX_DATA(FSIAISLD_MARK, PORT55_FN1), \ + PINMUX_DATA(TPU0TO0_MARK, PORT55_FN3), + PINMUX_DATA(A0_MARK, PORT57_FN1), \ + PINMUX_DATA(BS__MARK, PORT57_FN2), + PINMUX_DATA(A12_MARK, PORT58_FN1), \ + PINMUX_DATA(PORT58_KEYOUT7_MARK, PORT58_FN2), \ + PINMUX_DATA(TPU4TO2_MARK, PORT58_FN4), + PINMUX_DATA(A13_MARK, PORT59_FN1), \ + PINMUX_DATA(PORT59_KEYOUT6_MARK, PORT59_FN2), \ + PINMUX_DATA(TPU0TO1_MARK, PORT59_FN4), + PINMUX_DATA(A14_MARK, PORT60_FN1), \ + PINMUX_DATA(KEYOUT5_MARK, PORT60_FN2), + PINMUX_DATA(A15_MARK, PORT61_FN1), \ + PINMUX_DATA(KEYOUT4_MARK, PORT61_FN2), + PINMUX_DATA(A16_MARK, PORT62_FN1), \ + PINMUX_DATA(KEYOUT3_MARK, PORT62_FN2), \ + PINMUX_DATA(MSIOF0_SS1_MARK, PORT62_FN4, MSEL3CR_MSEL11_0), + PINMUX_DATA(A17_MARK, PORT63_FN1), \ + PINMUX_DATA(KEYOUT2_MARK, PORT63_FN2), \ + PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT63_FN4, MSEL3CR_MSEL11_0), + PINMUX_DATA(A18_MARK, PORT64_FN1), \ + PINMUX_DATA(KEYOUT1_MARK, PORT64_FN2), \ + PINMUX_DATA(MSIOF0_TSCK_MARK, PORT64_FN4, MSEL3CR_MSEL11_0), + PINMUX_DATA(A19_MARK, PORT65_FN1), \ + PINMUX_DATA(KEYOUT0_MARK, PORT65_FN2), \ + PINMUX_DATA(MSIOF0_TXD_MARK, PORT65_FN4, MSEL3CR_MSEL11_0), + PINMUX_DATA(A20_MARK, PORT66_FN1), \ + PINMUX_DATA(KEYIN0_MARK, PORT66_FN2), \ + PINMUX_DATA(MSIOF0_RSCK_MARK, PORT66_FN4, MSEL3CR_MSEL11_0), + PINMUX_DATA(A21_MARK, PORT67_FN1), \ + PINMUX_DATA(KEYIN1_MARK, PORT67_FN2), \ + PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT67_FN4, MSEL3CR_MSEL11_0), + PINMUX_DATA(A22_MARK, PORT68_FN1), \ + PINMUX_DATA(KEYIN2_MARK, PORT68_FN2), \ + PINMUX_DATA(MSIOF0_MCK0_MARK, PORT68_FN4, MSEL3CR_MSEL11_0), + PINMUX_DATA(A23_MARK, PORT69_FN1), \ + PINMUX_DATA(KEYIN3_MARK, PORT69_FN2), \ + PINMUX_DATA(MSIOF0_MCK1_MARK, PORT69_FN4, MSEL3CR_MSEL11_0), + PINMUX_DATA(A24_MARK, PORT70_FN1), \ + PINMUX_DATA(KEYIN4_MARK, PORT70_FN2), \ + PINMUX_DATA(MSIOF0_RXD_MARK, PORT70_FN4, MSEL3CR_MSEL11_0), + PINMUX_DATA(A25_MARK, PORT71_FN1), \ + PINMUX_DATA(KEYIN5_MARK, PORT71_FN2), \ + PINMUX_DATA(MSIOF0_SS2_MARK, PORT71_FN4, MSEL3CR_MSEL11_0), + PINMUX_DATA(A26_MARK, PORT72_FN1), \ + PINMUX_DATA(KEYIN6_MARK, PORT72_FN2), + PINMUX_DATA(KEYIN7_MARK, PORT73_FN2), + PINMUX_DATA(D0_NAF0_MARK, PORT74_FN1), + PINMUX_DATA(D1_NAF1_MARK, PORT75_FN1), + PINMUX_DATA(D2_NAF2_MARK, PORT76_FN1), + PINMUX_DATA(D3_NAF3_MARK, PORT77_FN1), + PINMUX_DATA(D4_NAF4_MARK, PORT78_FN1), + PINMUX_DATA(D5_NAF5_MARK, PORT79_FN1), + PINMUX_DATA(D6_NAF6_MARK, PORT80_FN1), + PINMUX_DATA(D7_NAF7_MARK, PORT81_FN1), + PINMUX_DATA(D8_NAF8_MARK, PORT82_FN1), + PINMUX_DATA(D9_NAF9_MARK, PORT83_FN1), + PINMUX_DATA(D10_NAF10_MARK, PORT84_FN1), + PINMUX_DATA(D11_NAF11_MARK, PORT85_FN1), + PINMUX_DATA(D12_NAF12_MARK, PORT86_FN1), + PINMUX_DATA(D13_NAF13_MARK, PORT87_FN1), + PINMUX_DATA(D14_NAF14_MARK, PORT88_FN1), + PINMUX_DATA(D15_NAF15_MARK, PORT89_FN1), + PINMUX_DATA(CS4__MARK, PORT90_FN1), + PINMUX_DATA(CS5A__MARK, PORT91_FN1), \ + PINMUX_DATA(PORT91_RDWR_MARK, PORT91_FN2), + PINMUX_DATA(CS5B__MARK, PORT92_FN1), \ + PINMUX_DATA(FCE1__MARK, PORT92_FN2), + PINMUX_DATA(CS6B__MARK, PORT93_FN1), \ + PINMUX_DATA(DACK0_MARK, PORT93_FN4), + PINMUX_DATA(FCE0__MARK, PORT94_FN1), \ + PINMUX_DATA(CS6A__MARK, PORT94_FN2), + PINMUX_DATA(WAIT__MARK, PORT95_FN1), \ + PINMUX_DATA(DREQ0_MARK, PORT95_FN2), + PINMUX_DATA(RD__FSC_MARK, PORT96_FN1), + PINMUX_DATA(WE0__FWE_MARK, PORT97_FN1), \ + PINMUX_DATA(RDWR_FWE_MARK, PORT97_FN2), + PINMUX_DATA(WE1__MARK, PORT98_FN1), + PINMUX_DATA(FRB_MARK, PORT99_FN1), + PINMUX_DATA(CKO_MARK, PORT100_FN1), + PINMUX_DATA(NBRSTOUT__MARK, PORT101_FN1), + PINMUX_DATA(NBRST__MARK, PORT102_FN1), + PINMUX_DATA(BBIF2_TXD_MARK, PORT103_FN3), + PINMUX_DATA(BBIF2_RXD_MARK, PORT104_FN3), + PINMUX_DATA(BBIF2_SYNC_MARK, PORT105_FN3), + PINMUX_DATA(BBIF2_SCK_MARK, PORT106_FN3), + PINMUX_DATA(SCIFA3_CTS__MARK, PORT107_FN3), \ + PINMUX_DATA(MFG3_IN2_MARK, PORT107_FN4), + PINMUX_DATA(SCIFA3_RXD_MARK, PORT108_FN3), \ + PINMUX_DATA(MFG3_IN1_MARK, PORT108_FN4), + PINMUX_DATA(BBIF1_SS2_MARK, PORT109_FN2), \ + PINMUX_DATA(SCIFA3_RTS__MARK, PORT109_FN3), \ + PINMUX_DATA(MFG3_OUT1_MARK, PORT109_FN4), + PINMUX_DATA(SCIFA3_TXD_MARK, PORT110_FN3), + PINMUX_DATA(HSI_RX_DATA_MARK, PORT111_FN1), \ + PINMUX_DATA(BBIF1_RXD_MARK, PORT111_FN3), + PINMUX_DATA(HSI_TX_WAKE_MARK, PORT112_FN1), \ + PINMUX_DATA(BBIF1_TSCK_MARK, PORT112_FN3), + PINMUX_DATA(HSI_TX_DATA_MARK, PORT113_FN1), \ + PINMUX_DATA(BBIF1_TSYNC_MARK, PORT113_FN3), + PINMUX_DATA(HSI_TX_READY_MARK, PORT114_FN1), \ + PINMUX_DATA(BBIF1_TXD_MARK, PORT114_FN3), + PINMUX_DATA(HSI_RX_READY_MARK, PORT115_FN1), \ + PINMUX_DATA(BBIF1_RSCK_MARK, PORT115_FN3), \ + PINMUX_DATA(PORT115_I2C_SCL2_MARK, PORT115_FN5, MSEL2CR_MSEL17_1), \ + PINMUX_DATA(PORT115_I2C_SCL3_MARK, PORT115_FN6, MSEL2CR_MSEL19_1), + PINMUX_DATA(HSI_RX_WAKE_MARK, PORT116_FN1), \ + PINMUX_DATA(BBIF1_RSYNC_MARK, PORT116_FN3), \ + PINMUX_DATA(PORT116_I2C_SDA2_MARK, PORT116_FN5, MSEL2CR_MSEL17_1), \ + PINMUX_DATA(PORT116_I2C_SDA3_MARK, PORT116_FN6, MSEL2CR_MSEL19_1), + PINMUX_DATA(HSI_RX_FLAG_MARK, PORT117_FN1), \ + PINMUX_DATA(BBIF1_SS1_MARK, PORT117_FN2), \ + PINMUX_DATA(BBIF1_FLOW_MARK, PORT117_FN3), + PINMUX_DATA(HSI_TX_FLAG_MARK, PORT118_FN1), + PINMUX_DATA(VIO_VD_MARK, PORT128_FN1), \ + PINMUX_DATA(PORT128_LCD2VSYN_MARK, PORT128_FN4, MSEL3CR_MSEL2_0), \ + PINMUX_DATA(VIO2_VD_MARK, PORT128_FN6, MSEL4CR_MSEL27_0), \ + PINMUX_DATA(LCD2D0_MARK, PORT128_FN7), + + PINMUX_DATA(VIO_HD_MARK, PORT129_FN1), \ + PINMUX_DATA(PORT129_LCD2HSYN_MARK, PORT129_FN4), \ + PINMUX_DATA(PORT129_LCD2CS__MARK, PORT129_FN5), \ + PINMUX_DATA(VIO2_HD_MARK, PORT129_FN6, MSEL4CR_MSEL27_0), \ + PINMUX_DATA(LCD2D1_MARK, PORT129_FN7), + PINMUX_DATA(VIO_D0_MARK, PORT130_FN1), \ + PINMUX_DATA(PORT130_MSIOF2_RXD_MARK, PORT130_FN3, MSEL4CR_MSEL11_0, + MSEL4CR_MSEL10_1), \ + PINMUX_DATA(LCD2D10_MARK, PORT130_FN7), + PINMUX_DATA(VIO_D1_MARK, PORT131_FN1), \ + PINMUX_DATA(PORT131_KEYOUT6_MARK, PORT131_FN2), \ + PINMUX_DATA(PORT131_MSIOF2_SS1_MARK, PORT131_FN3), \ + PINMUX_DATA(PORT131_KEYOUT11_MARK, PORT131_FN4), \ + PINMUX_DATA(LCD2D11_MARK, PORT131_FN7), + PINMUX_DATA(VIO_D2_MARK, PORT132_FN1), \ + PINMUX_DATA(PORT132_KEYOUT7_MARK, PORT132_FN2), \ + PINMUX_DATA(PORT132_MSIOF2_SS2_MARK, PORT132_FN3), \ + PINMUX_DATA(PORT132_KEYOUT10_MARK, PORT132_FN4), \ + PINMUX_DATA(LCD2D12_MARK, PORT132_FN7), + PINMUX_DATA(VIO_D3_MARK, PORT133_FN1), \ + PINMUX_DATA(MSIOF2_TSYNC_MARK, PORT133_FN3, MSEL4CR_MSEL11_0), \ + PINMUX_DATA(LCD2D13_MARK, PORT133_FN7), + PINMUX_DATA(VIO_D4_MARK, PORT134_FN1), \ + PINMUX_DATA(MSIOF2_TXD_MARK, PORT134_FN3, MSEL4CR_MSEL11_0), \ + PINMUX_DATA(LCD2D14_MARK, PORT134_FN7), + PINMUX_DATA(VIO_D5_MARK, PORT135_FN1), \ + PINMUX_DATA(MSIOF2_TSCK_MARK, PORT135_FN3, MSEL4CR_MSEL11_0), \ + PINMUX_DATA(LCD2D15_MARK, PORT135_FN7), + PINMUX_DATA(VIO_D6_MARK, PORT136_FN1), \ + PINMUX_DATA(PORT136_KEYOUT8_MARK, PORT136_FN2), \ + PINMUX_DATA(LCD2D16_MARK, PORT136_FN7), + PINMUX_DATA(VIO_D7_MARK, PORT137_FN1), \ + PINMUX_DATA(PORT137_KEYOUT9_MARK, PORT137_FN2), \ + PINMUX_DATA(LCD2D17_MARK, PORT137_FN7), + PINMUX_DATA(VIO_D8_MARK, PORT138_FN1), \ + PINMUX_DATA(PORT138_KEYOUT8_MARK, PORT138_FN2), \ + PINMUX_DATA(VIO2_D0_MARK, PORT138_FN6), \ + PINMUX_DATA(LCD2D6_MARK, PORT138_FN7), + PINMUX_DATA(VIO_D9_MARK, PORT139_FN1), \ + PINMUX_DATA(PORT139_KEYOUT9_MARK, PORT139_FN2), \ + PINMUX_DATA(VIO2_D1_MARK, PORT139_FN6), \ + PINMUX_DATA(LCD2D7_MARK, PORT139_FN7), + PINMUX_DATA(VIO_D10_MARK, PORT140_FN1), \ + PINMUX_DATA(TPU0TO2_MARK, PORT140_FN4), \ + PINMUX_DATA(VIO2_D2_MARK, PORT140_FN6), \ + PINMUX_DATA(LCD2D8_MARK, PORT140_FN7), + PINMUX_DATA(VIO_D11_MARK, PORT141_FN1), \ + PINMUX_DATA(TPU0TO3_MARK, PORT141_FN4), \ + PINMUX_DATA(VIO2_D3_MARK, PORT141_FN6), \ + PINMUX_DATA(LCD2D9_MARK, PORT141_FN7), + PINMUX_DATA(VIO_D12_MARK, PORT142_FN1), \ + PINMUX_DATA(PORT142_KEYOUT10_MARK, PORT142_FN2), \ + PINMUX_DATA(VIO2_D4_MARK, PORT142_FN6), \ + PINMUX_DATA(LCD2D2_MARK, PORT142_FN7), + PINMUX_DATA(VIO_D13_MARK, PORT143_FN1), \ + PINMUX_DATA(PORT143_KEYOUT11_MARK, PORT143_FN2), \ + PINMUX_DATA(PORT143_KEYOUT6_MARK, PORT143_FN3), \ + PINMUX_DATA(VIO2_D5_MARK, PORT143_FN6), \ + PINMUX_DATA(LCD2D3_MARK, PORT143_FN7), + PINMUX_DATA(VIO_D14_MARK, PORT144_FN1), \ + PINMUX_DATA(PORT144_KEYOUT7_MARK, PORT144_FN2), \ + PINMUX_DATA(VIO2_D6_MARK, PORT144_FN6), \ + PINMUX_DATA(LCD2D4_MARK, PORT144_FN7), + PINMUX_DATA(VIO_D15_MARK, PORT145_FN1), \ + PINMUX_DATA(TPU1TO3_MARK, PORT145_FN3), \ + PINMUX_DATA(PORT145_LCD2DISP_MARK, PORT145_FN4), \ + PINMUX_DATA(PORT145_LCD2RS_MARK, PORT145_FN5), \ + PINMUX_DATA(VIO2_D7_MARK, PORT145_FN6), \ + PINMUX_DATA(LCD2D5_MARK, PORT145_FN7), + PINMUX_DATA(VIO_CLK_MARK, PORT146_FN1), \ + PINMUX_DATA(LCD2DCK_MARK, PORT146_FN4), \ + PINMUX_DATA(PORT146_LCD2WR__MARK, PORT146_FN5), \ + PINMUX_DATA(VIO2_CLK_MARK, PORT146_FN6, MSEL4CR_MSEL27_0), \ + PINMUX_DATA(LCD2D18_MARK, PORT146_FN7), + PINMUX_DATA(VIO_FIELD_MARK, PORT147_FN1), \ + PINMUX_DATA(LCD2RD__MARK, PORT147_FN4), \ + PINMUX_DATA(VIO2_FIELD_MARK, PORT147_FN6, MSEL4CR_MSEL27_0), \ + PINMUX_DATA(LCD2D19_MARK, PORT147_FN7), + PINMUX_DATA(VIO_CKO_MARK, PORT148_FN1), + PINMUX_DATA(A27_MARK, PORT149_FN1), \ + PINMUX_DATA(PORT149_RDWR_MARK, PORT149_FN2), \ + PINMUX_DATA(MFG0_IN1_MARK, PORT149_FN3), \ + PINMUX_DATA(PORT149_KEYOUT9_MARK, PORT149_FN4), + PINMUX_DATA(MFG0_IN2_MARK, PORT150_FN3), + PINMUX_DATA(TS_SPSYNC3_MARK, PORT151_FN4), \ + PINMUX_DATA(MSIOF2_RSCK_MARK, PORT151_FN5), + PINMUX_DATA(TS_SDAT3_MARK, PORT152_FN4), \ + PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT152_FN5), + PINMUX_DATA(TPU1TO2_MARK, PORT153_FN3), \ + PINMUX_DATA(TS_SDEN3_MARK, PORT153_FN4), \ + PINMUX_DATA(PORT153_MSIOF2_SS1_MARK, PORT153_FN5), + PINMUX_DATA(SCIFA2_TXD1_MARK, PORT154_FN2, MSEL3CR_MSEL9_0), \ + PINMUX_DATA(MSIOF2_MCK0_MARK, PORT154_FN5), + PINMUX_DATA(SCIFA2_RXD1_MARK, PORT155_FN2, MSEL3CR_MSEL9_0), \ + PINMUX_DATA(MSIOF2_MCK1_MARK, PORT155_FN5), + PINMUX_DATA(SCIFA2_RTS1__MARK, PORT156_FN2, MSEL3CR_MSEL9_0), \ + PINMUX_DATA(PORT156_MSIOF2_SS2_MARK, PORT156_FN5), + PINMUX_DATA(SCIFA2_CTS1__MARK, PORT157_FN2, MSEL3CR_MSEL9_0), \ + PINMUX_DATA(PORT157_MSIOF2_RXD_MARK, PORT157_FN5, MSEL4CR_MSEL11_0, + MSEL4CR_MSEL10_0), + PINMUX_DATA(DINT__MARK, PORT158_FN1), \ + PINMUX_DATA(SCIFA2_SCK1_MARK, PORT158_FN2, MSEL3CR_MSEL9_0), \ + PINMUX_DATA(TS_SCK3_MARK, PORT158_FN4), + PINMUX_DATA(PORT159_SCIFB_SCK_MARK, PORT159_FN1, MSEL4CR_MSEL22_0), \ + PINMUX_DATA(PORT159_SCIFA5_SCK_MARK, PORT159_FN2, MSEL4CR_MSEL21_1), \ + PINMUX_DATA(NMI_MARK, PORT159_FN3), + PINMUX_DATA(PORT160_SCIFB_TXD_MARK, PORT160_FN1, MSEL4CR_MSEL22_0), \ + PINMUX_DATA(PORT160_SCIFA5_TXD_MARK, PORT160_FN2, MSEL4CR_MSEL21_1), + PINMUX_DATA(PORT161_SCIFB_CTS__MARK, PORT161_FN1, MSEL4CR_MSEL22_0), \ + PINMUX_DATA(PORT161_SCIFA5_CTS__MARK, PORT161_FN2, MSEL4CR_MSEL21_1), + PINMUX_DATA(PORT162_SCIFB_RXD_MARK, PORT162_FN1, MSEL4CR_MSEL22_0), \ + PINMUX_DATA(PORT162_SCIFA5_RXD_MARK, PORT162_FN2, MSEL4CR_MSEL21_1), + PINMUX_DATA(PORT163_SCIFB_RTS__MARK, PORT163_FN1, MSEL4CR_MSEL22_0), \ + PINMUX_DATA(PORT163_SCIFA5_RTS__MARK, PORT163_FN2, MSEL4CR_MSEL21_1), \ + PINMUX_DATA(TPU3TO0_MARK, PORT163_FN5), + PINMUX_DATA(LCDD0_MARK, PORT192_FN1), + PINMUX_DATA(LCDD1_MARK, PORT193_FN1), \ + PINMUX_DATA(PORT193_SCIFA5_CTS__MARK, PORT193_FN3, MSEL4CR_MSEL21_0, + MSEL4CR_MSEL20_1), \ + PINMUX_DATA(BBIF2_TSYNC1_MARK, PORT193_FN5), + PINMUX_DATA(LCDD2_MARK, PORT194_FN1), \ + PINMUX_DATA(PORT194_SCIFA5_RTS__MARK, PORT194_FN3, MSEL4CR_MSEL21_0, + MSEL4CR_MSEL20_1), \ + PINMUX_DATA(BBIF2_TSCK1_MARK, PORT194_FN5), + PINMUX_DATA(LCDD3_MARK, PORT195_FN1), \ + PINMUX_DATA(PORT195_SCIFA5_RXD_MARK, PORT195_FN3, MSEL4CR_MSEL21_0, + MSEL4CR_MSEL20_1), \ + PINMUX_DATA(BBIF2_TXD1_MARK, PORT195_FN5), + PINMUX_DATA(LCDD4_MARK, PORT196_FN1), \ + PINMUX_DATA(PORT196_SCIFA5_TXD_MARK, PORT196_FN3, MSEL4CR_MSEL21_0, + MSEL4CR_MSEL20_1), + PINMUX_DATA(LCDD5_MARK, PORT197_FN1), \ + PINMUX_DATA(PORT197_SCIFA5_SCK_MARK, PORT197_FN3, MSEL4CR_MSEL21_0, + MSEL4CR_MSEL20_1), \ + PINMUX_DATA(MFG2_OUT2_MARK, PORT197_FN5), \ + PINMUX_DATA(TPU2TO1_MARK, PORT197_FN7), + PINMUX_DATA(LCDD6_MARK, PORT198_FN1), + PINMUX_DATA(LCDD7_MARK, PORT199_FN1), \ + PINMUX_DATA(TPU4TO1_MARK, PORT199_FN2), \ + PINMUX_DATA(MFG4_OUT2_MARK, PORT199_FN5), + PINMUX_DATA(LCDD8_MARK, PORT200_FN1), \ + PINMUX_DATA(D16_MARK, PORT200_FN6), + PINMUX_DATA(LCDD9_MARK, PORT201_FN1), \ + PINMUX_DATA(D17_MARK, PORT201_FN6), + PINMUX_DATA(LCDD10_MARK, PORT202_FN1), \ + PINMUX_DATA(D18_MARK, PORT202_FN6), + PINMUX_DATA(LCDD11_MARK, PORT203_FN1), \ + PINMUX_DATA(D19_MARK, PORT203_FN6), + PINMUX_DATA(LCDD12_MARK, PORT204_FN1), \ + PINMUX_DATA(D20_MARK, PORT204_FN6), + PINMUX_DATA(LCDD13_MARK, PORT205_FN1), \ + PINMUX_DATA(D21_MARK, PORT205_FN6), + PINMUX_DATA(LCDD14_MARK, PORT206_FN1), \ + PINMUX_DATA(D22_MARK, PORT206_FN6), + PINMUX_DATA(LCDD15_MARK, PORT207_FN1), \ + PINMUX_DATA(PORT207_MSIOF0L_SS1_MARK, PORT207_FN2, MSEL3CR_MSEL11_1), \ + PINMUX_DATA(D23_MARK, PORT207_FN6), + PINMUX_DATA(LCDD16_MARK, PORT208_FN1), \ + PINMUX_DATA(PORT208_MSIOF0L_SS2_MARK, PORT208_FN2, MSEL3CR_MSEL11_1), \ + PINMUX_DATA(D24_MARK, PORT208_FN6), + PINMUX_DATA(LCDD17_MARK, PORT209_FN1), \ + PINMUX_DATA(D25_MARK, PORT209_FN6), + PINMUX_DATA(LCDD18_MARK, PORT210_FN1), \ + PINMUX_DATA(DREQ2_MARK, PORT210_FN2), \ + PINMUX_DATA(PORT210_MSIOF0L_SS1_MARK, PORT210_FN5, MSEL3CR_MSEL11_1), \ + PINMUX_DATA(D26_MARK, PORT210_FN6), + PINMUX_DATA(LCDD19_MARK, PORT211_FN1), \ + PINMUX_DATA(PORT211_MSIOF0L_SS2_MARK, PORT211_FN5, MSEL3CR_MSEL11_1), \ + PINMUX_DATA(D27_MARK, PORT211_FN6), + PINMUX_DATA(LCDD20_MARK, PORT212_FN1), \ + PINMUX_DATA(TS_SPSYNC1_MARK, PORT212_FN2), \ + PINMUX_DATA(MSIOF0L_MCK0_MARK, PORT212_FN5, MSEL3CR_MSEL11_1), \ + PINMUX_DATA(D28_MARK, PORT212_FN6), + PINMUX_DATA(LCDD21_MARK, PORT213_FN1), \ + PINMUX_DATA(TS_SDAT1_MARK, PORT213_FN2), \ + PINMUX_DATA(MSIOF0L_MCK1_MARK, PORT213_FN5, MSEL3CR_MSEL11_1), \ + PINMUX_DATA(D29_MARK, PORT213_FN6), + PINMUX_DATA(LCDD22_MARK, PORT214_FN1), \ + PINMUX_DATA(TS_SDEN1_MARK, PORT214_FN2), \ + PINMUX_DATA(MSIOF0L_RSCK_MARK, PORT214_FN5, MSEL3CR_MSEL11_1), \ + PINMUX_DATA(D30_MARK, PORT214_FN6), + PINMUX_DATA(LCDD23_MARK, PORT215_FN1), \ + PINMUX_DATA(TS_SCK1_MARK, PORT215_FN2), \ + PINMUX_DATA(MSIOF0L_RSYNC_MARK, PORT215_FN5, MSEL3CR_MSEL11_1), \ + PINMUX_DATA(D31_MARK, PORT215_FN6), + PINMUX_DATA(LCDDCK_MARK, PORT216_FN1), \ + PINMUX_DATA(LCDWR__MARK, PORT216_FN2), + PINMUX_DATA(LCDRD__MARK, PORT217_FN1), \ + PINMUX_DATA(DACK2_MARK, PORT217_FN2), \ + PINMUX_DATA(PORT217_LCD2RS_MARK, PORT217_FN3), \ + PINMUX_DATA(MSIOF0L_TSYNC_MARK, PORT217_FN5, MSEL3CR_MSEL11_1), \ + PINMUX_DATA(VIO2_FIELD3_MARK, PORT217_FN6, MSEL4CR_MSEL27_1, + MSEL4CR_MSEL26_1), \ + PINMUX_DATA(PORT217_LCD2DISP_MARK, PORT217_FN7), + PINMUX_DATA(LCDHSYN_MARK, PORT218_FN1), \ + PINMUX_DATA(LCDCS__MARK, PORT218_FN2), \ + PINMUX_DATA(LCDCS2__MARK, PORT218_FN3), \ + PINMUX_DATA(DACK3_MARK, PORT218_FN4), \ + PINMUX_DATA(PORT218_VIO_CKOR_MARK, PORT218_FN5), + PINMUX_DATA(LCDDISP_MARK, PORT219_FN1), \ + PINMUX_DATA(LCDRS_MARK, PORT219_FN2), \ + PINMUX_DATA(PORT219_LCD2WR__MARK, PORT219_FN3), \ + PINMUX_DATA(DREQ3_MARK, PORT219_FN4), \ + PINMUX_DATA(MSIOF0L_TSCK_MARK, PORT219_FN5, MSEL3CR_MSEL11_1), \ + PINMUX_DATA(VIO2_CLK3_MARK, PORT219_FN6, MSEL4CR_MSEL27_1, + MSEL4CR_MSEL26_1), \ + PINMUX_DATA(LCD2DCK_2_MARK, PORT219_FN7), + PINMUX_DATA(LCDVSYN_MARK, PORT220_FN1), \ + PINMUX_DATA(LCDVSYN2_MARK, PORT220_FN2), + PINMUX_DATA(LCDLCLK_MARK, PORT221_FN1), \ + PINMUX_DATA(DREQ1_MARK, PORT221_FN2), \ + PINMUX_DATA(PORT221_LCD2CS__MARK, PORT221_FN3), \ + PINMUX_DATA(PWEN_MARK, PORT221_FN4), \ + PINMUX_DATA(MSIOF0L_RXD_MARK, PORT221_FN5, MSEL3CR_MSEL11_1), \ + PINMUX_DATA(VIO2_HD3_MARK, PORT221_FN6, MSEL4CR_MSEL27_1, + MSEL4CR_MSEL26_1), \ + PINMUX_DATA(PORT221_LCD2HSYN_MARK, PORT221_FN7), + PINMUX_DATA(LCDDON_MARK, PORT222_FN1), \ + PINMUX_DATA(LCDDON2_MARK, PORT222_FN2), \ + PINMUX_DATA(DACK1_MARK, PORT222_FN3), \ + PINMUX_DATA(OVCN_MARK, PORT222_FN4), \ + PINMUX_DATA(MSIOF0L_TXD_MARK, PORT222_FN5, MSEL3CR_MSEL11_1), \ + PINMUX_DATA(VIO2_VD3_MARK, PORT222_FN6, MSEL4CR_MSEL27_1, + MSEL4CR_MSEL26_1), \ + PINMUX_DATA(PORT222_LCD2VSYN_MARK, PORT222_FN7, MSEL3CR_MSEL2_1), + + PINMUX_DATA(SCIFA1_TXD_MARK, PORT225_FN2), \ + PINMUX_DATA(OVCN2_MARK, PORT225_FN4), + PINMUX_DATA(EXTLP_MARK, PORT226_FN1), \ + PINMUX_DATA(SCIFA1_SCK_MARK, PORT226_FN2), \ + PINMUX_DATA(PORT226_VIO_CKO2_MARK, PORT226_FN5), + PINMUX_DATA(SCIFA1_RTS__MARK, PORT227_FN2), \ + PINMUX_DATA(IDIN_MARK, PORT227_FN4), + PINMUX_DATA(SCIFA1_RXD_MARK, PORT228_FN2), + PINMUX_DATA(SCIFA1_CTS__MARK, PORT229_FN2), \ + PINMUX_DATA(MFG1_IN1_MARK, PORT229_FN3), + PINMUX_DATA(MSIOF1_TXD_MARK, PORT230_FN1), \ + PINMUX_DATA(SCIFA2_TXD2_MARK, PORT230_FN2, MSEL3CR_MSEL9_1), + PINMUX_DATA(MSIOF1_TSYNC_MARK, PORT231_FN1), \ + PINMUX_DATA(SCIFA2_CTS2__MARK, PORT231_FN2, MSEL3CR_MSEL9_1), + PINMUX_DATA(MSIOF1_TSCK_MARK, PORT232_FN1), \ + PINMUX_DATA(SCIFA2_SCK2_MARK, PORT232_FN2, MSEL3CR_MSEL9_1), + PINMUX_DATA(MSIOF1_RXD_MARK, PORT233_FN1), \ + PINMUX_DATA(SCIFA2_RXD2_MARK, PORT233_FN2, MSEL3CR_MSEL9_1), + PINMUX_DATA(MSIOF1_RSCK_MARK, PORT234_FN1), \ + PINMUX_DATA(SCIFA2_RTS2__MARK, PORT234_FN2, MSEL3CR_MSEL9_1), \ + PINMUX_DATA(VIO2_CLK2_MARK, PORT234_FN6, MSEL4CR_MSEL27_1, + MSEL4CR_MSEL26_0), \ + PINMUX_DATA(LCD2D20_MARK, PORT234_FN7), + PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT235_FN1), \ + PINMUX_DATA(MFG1_IN2_MARK, PORT235_FN3), \ + PINMUX_DATA(VIO2_VD2_MARK, PORT235_FN6, MSEL4CR_MSEL27_1, + MSEL4CR_MSEL26_0), \ + PINMUX_DATA(LCD2D21_MARK, PORT235_FN7), + PINMUX_DATA(MSIOF1_MCK0_MARK, PORT236_FN1), \ + PINMUX_DATA(PORT236_I2C_SDA2_MARK, PORT236_FN2, MSEL2CR_MSEL17_0, + MSEL2CR_MSEL16_0), + PINMUX_DATA(MSIOF1_MCK1_MARK, PORT237_FN1), \ + PINMUX_DATA(PORT237_I2C_SCL2_MARK, PORT237_FN2, MSEL2CR_MSEL17_0, + MSEL2CR_MSEL16_0), + PINMUX_DATA(MSIOF1_SS1_MARK, PORT238_FN1), \ + PINMUX_DATA(VIO2_FIELD2_MARK, PORT238_FN6, MSEL4CR_MSEL27_1, + MSEL4CR_MSEL26_0), \ + PINMUX_DATA(LCD2D22_MARK, PORT238_FN7), + PINMUX_DATA(MSIOF1_SS2_MARK, PORT239_FN1), \ + PINMUX_DATA(VIO2_HD2_MARK, PORT239_FN6, MSEL4CR_MSEL27_1, + MSEL4CR_MSEL26_0), \ + PINMUX_DATA(LCD2D23_MARK, PORT239_FN7), + PINMUX_DATA(SCIFA6_TXD_MARK, PORT240_FN1), + PINMUX_DATA(PORT241_IRDA_OUT_MARK, PORT241_FN1, MSEL4CR_MSEL19_0), \ + PINMUX_DATA(PORT241_IROUT_MARK, PORT241_FN2), \ + PINMUX_DATA(MFG4_OUT1_MARK, PORT241_FN3), \ + PINMUX_DATA(TPU4TO0_MARK, PORT241_FN4), + PINMUX_DATA(PORT242_IRDA_IN_MARK, PORT242_FN1, MSEL4CR_MSEL19_0), \ + PINMUX_DATA(MFG4_IN2_MARK, PORT242_FN3), + PINMUX_DATA(PORT243_IRDA_FIRSEL_MARK, PORT243_FN1, MSEL4CR_MSEL19_0), \ + PINMUX_DATA(PORT243_VIO_CKO2_MARK, PORT243_FN2), + PINMUX_DATA(PORT244_SCIFA5_CTS__MARK, PORT244_FN1, MSEL4CR_MSEL21_0, + MSEL4CR_MSEL20_0), \ + PINMUX_DATA(MFG2_IN1_MARK, PORT244_FN2), \ + PINMUX_DATA(PORT244_SCIFB_CTS__MARK, PORT244_FN3, MSEL4CR_MSEL22_1), \ + PINMUX_DATA(MSIOF2R_RXD_MARK, PORT244_FN7, MSEL4CR_MSEL11_1), + PINMUX_DATA(PORT245_SCIFA5_RTS__MARK, PORT245_FN1, MSEL4CR_MSEL21_0, + MSEL4CR_MSEL20_0), \ + PINMUX_DATA(MFG2_IN2_MARK, PORT245_FN2), \ + PINMUX_DATA(PORT245_SCIFB_RTS__MARK, PORT245_FN3, MSEL4CR_MSEL22_1), \ + PINMUX_DATA(MSIOF2R_TXD_MARK, PORT245_FN7, MSEL4CR_MSEL11_1), + PINMUX_DATA(PORT246_SCIFA5_RXD_MARK, PORT246_FN1, MSEL4CR_MSEL21_0, + MSEL4CR_MSEL20_0), \ + PINMUX_DATA(MFG1_OUT1_MARK, PORT246_FN2), \ + PINMUX_DATA(PORT246_SCIFB_RXD_MARK, PORT246_FN3, MSEL4CR_MSEL22_1), \ + PINMUX_DATA(TPU1TO0_MARK, PORT246_FN4), + PINMUX_DATA(PORT247_SCIFA5_TXD_MARK, PORT247_FN1, MSEL4CR_MSEL21_0, + MSEL4CR_MSEL20_0), \ + PINMUX_DATA(MFG3_OUT2_MARK, PORT247_FN2), \ + PINMUX_DATA(PORT247_SCIFB_TXD_MARK, PORT247_FN3, MSEL4CR_MSEL22_1), \ + PINMUX_DATA(TPU3TO1_MARK, PORT247_FN4), + PINMUX_DATA(PORT248_SCIFA5_SCK_MARK, PORT248_FN1, MSEL4CR_MSEL21_0, + MSEL4CR_MSEL20_0), \ + PINMUX_DATA(MFG2_OUT1_MARK, PORT248_FN2), \ + PINMUX_DATA(PORT248_SCIFB_SCK_MARK, PORT248_FN3, MSEL4CR_MSEL22_1), \ + PINMUX_DATA(TPU2TO0_MARK, PORT248_FN4), \ + PINMUX_DATA(PORT248_I2C_SCL3_MARK, PORT248_FN5, MSEL2CR_MSEL19_0, + MSEL2CR_MSEL18_0), \ + PINMUX_DATA(MSIOF2R_TSCK_MARK, PORT248_FN7, MSEL4CR_MSEL11_1), + PINMUX_DATA(PORT249_IROUT_MARK, PORT249_FN1), \ + PINMUX_DATA(MFG4_IN1_MARK, PORT249_FN2), \ + PINMUX_DATA(PORT249_I2C_SDA3_MARK, PORT249_FN5, MSEL2CR_MSEL19_0, + MSEL2CR_MSEL18_0), \ + PINMUX_DATA(MSIOF2R_TSYNC_MARK, PORT249_FN7, MSEL4CR_MSEL11_1), + PINMUX_DATA(SDHICLK0_MARK, PORT250_FN1), + PINMUX_DATA(SDHICD0_MARK, PORT251_FN1), + PINMUX_DATA(SDHID0_0_MARK, PORT252_FN1), + PINMUX_DATA(SDHID0_1_MARK, PORT253_FN1), + PINMUX_DATA(SDHID0_2_MARK, PORT254_FN1), + PINMUX_DATA(SDHID0_3_MARK, PORT255_FN1), + PINMUX_DATA(SDHICMD0_MARK, PORT256_FN1), + PINMUX_DATA(SDHIWP0_MARK, PORT257_FN1), + PINMUX_DATA(SDHICLK1_MARK, PORT258_FN1), + PINMUX_DATA(SDHID1_0_MARK, PORT259_FN1), \ + PINMUX_DATA(TS_SPSYNC2_MARK, PORT259_FN3), + PINMUX_DATA(SDHID1_1_MARK, PORT260_FN1), \ + PINMUX_DATA(TS_SDAT2_MARK, PORT260_FN3), + PINMUX_DATA(SDHID1_2_MARK, PORT261_FN1), \ + PINMUX_DATA(TS_SDEN2_MARK, PORT261_FN3), + PINMUX_DATA(SDHID1_3_MARK, PORT262_FN1), \ + PINMUX_DATA(TS_SCK2_MARK, PORT262_FN3), + PINMUX_DATA(SDHICMD1_MARK, PORT263_FN1), + PINMUX_DATA(SDHICLK2_MARK, PORT264_FN1), + PINMUX_DATA(SDHID2_0_MARK, PORT265_FN1), \ + PINMUX_DATA(TS_SPSYNC4_MARK, PORT265_FN3), + PINMUX_DATA(SDHID2_1_MARK, PORT266_FN1), \ + PINMUX_DATA(TS_SDAT4_MARK, PORT266_FN3), + PINMUX_DATA(SDHID2_2_MARK, PORT267_FN1), \ + PINMUX_DATA(TS_SDEN4_MARK, PORT267_FN3), + PINMUX_DATA(SDHID2_3_MARK, PORT268_FN1), \ + PINMUX_DATA(TS_SCK4_MARK, PORT268_FN3), + PINMUX_DATA(SDHICMD2_MARK, PORT269_FN1), + PINMUX_DATA(MMCCLK0_MARK, PORT270_FN1, MSEL4CR_MSEL15_0), + PINMUX_DATA(MMCD0_0_MARK, PORT271_FN1, PORT271_IN_PU, + MSEL4CR_MSEL15_0), + PINMUX_DATA(MMCD0_1_MARK, PORT272_FN1, PORT272_IN_PU, + MSEL4CR_MSEL15_0), + PINMUX_DATA(MMCD0_2_MARK, PORT273_FN1, PORT273_IN_PU, + MSEL4CR_MSEL15_0), + PINMUX_DATA(MMCD0_3_MARK, PORT274_FN1, PORT274_IN_PU, + MSEL4CR_MSEL15_0), + PINMUX_DATA(MMCD0_4_MARK, PORT275_FN1, PORT275_IN_PU, + MSEL4CR_MSEL15_0), \ + PINMUX_DATA(TS_SPSYNC5_MARK, PORT275_FN3), + PINMUX_DATA(MMCD0_5_MARK, PORT276_FN1, PORT276_IN_PU, + MSEL4CR_MSEL15_0), \ + PINMUX_DATA(TS_SDAT5_MARK, PORT276_FN3), + PINMUX_DATA(MMCD0_6_MARK, PORT277_FN1, PORT277_IN_PU, + MSEL4CR_MSEL15_0), \ + PINMUX_DATA(TS_SDEN5_MARK, PORT277_FN3), + PINMUX_DATA(MMCD0_7_MARK, PORT278_FN1, PORT278_IN_PU, + MSEL4CR_MSEL15_0), \ + PINMUX_DATA(TS_SCK5_MARK, PORT278_FN3), + PINMUX_DATA(MMCCMD0_MARK, PORT279_FN1, PORT279_IN_PU, + MSEL4CR_MSEL15_0), + PINMUX_DATA(RESETOUTS__MARK, PORT281_FN1), \ + PINMUX_DATA(EXTAL2OUT_MARK, PORT281_FN2), + PINMUX_DATA(MCP_WAIT__MCP_FRB_MARK, PORT288_FN1), + PINMUX_DATA(MCP_CKO_MARK, PORT289_FN1), \ + PINMUX_DATA(MMCCLK1_MARK, PORT289_FN2, MSEL4CR_MSEL15_1), + PINMUX_DATA(MCP_D15_MCP_NAF15_MARK, PORT290_FN1), + PINMUX_DATA(MCP_D14_MCP_NAF14_MARK, PORT291_FN1), + PINMUX_DATA(MCP_D13_MCP_NAF13_MARK, PORT292_FN1), + PINMUX_DATA(MCP_D12_MCP_NAF12_MARK, PORT293_FN1), + PINMUX_DATA(MCP_D11_MCP_NAF11_MARK, PORT294_FN1), + PINMUX_DATA(MCP_D10_MCP_NAF10_MARK, PORT295_FN1), + PINMUX_DATA(MCP_D9_MCP_NAF9_MARK, PORT296_FN1), + PINMUX_DATA(MCP_D8_MCP_NAF8_MARK, PORT297_FN1), \ + PINMUX_DATA(MMCCMD1_MARK, PORT297_FN2, MSEL4CR_MSEL15_1), + PINMUX_DATA(MCP_D7_MCP_NAF7_MARK, PORT298_FN1), \ + PINMUX_DATA(MMCD1_7_MARK, PORT298_FN2, MSEL4CR_MSEL15_1), + + PINMUX_DATA(MCP_D6_MCP_NAF6_MARK, PORT299_FN1), \ + PINMUX_DATA(MMCD1_6_MARK, PORT299_FN2, MSEL4CR_MSEL15_1), + PINMUX_DATA(MCP_D5_MCP_NAF5_MARK, PORT300_FN1), \ + PINMUX_DATA(MMCD1_5_MARK, PORT300_FN2, MSEL4CR_MSEL15_1), + PINMUX_DATA(MCP_D4_MCP_NAF4_MARK, PORT301_FN1), \ + PINMUX_DATA(MMCD1_4_MARK, PORT301_FN2, MSEL4CR_MSEL15_1), + PINMUX_DATA(MCP_D3_MCP_NAF3_MARK, PORT302_FN1), \ + PINMUX_DATA(MMCD1_3_MARK, PORT302_FN2, MSEL4CR_MSEL15_1), + PINMUX_DATA(MCP_D2_MCP_NAF2_MARK, PORT303_FN1), \ + PINMUX_DATA(MMCD1_2_MARK, PORT303_FN2, MSEL4CR_MSEL15_1), + PINMUX_DATA(MCP_D1_MCP_NAF1_MARK, PORT304_FN1), \ + PINMUX_DATA(MMCD1_1_MARK, PORT304_FN2, MSEL4CR_MSEL15_1), + PINMUX_DATA(MCP_D0_MCP_NAF0_MARK, PORT305_FN1), \ + PINMUX_DATA(MMCD1_0_MARK, PORT305_FN2, MSEL4CR_MSEL15_1), + PINMUX_DATA(MCP_NBRSTOUT__MARK, PORT306_FN1), + PINMUX_DATA(MCP_WE0__MCP_FWE_MARK, PORT309_FN1), \ + PINMUX_DATA(MCP_RDWR_MCP_FWE_MARK, PORT309_FN2), + + /* MSEL2 special cases */ + PINMUX_DATA(TSIF2_TS_XX1_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_0, + MSEL2CR_MSEL12_0), + PINMUX_DATA(TSIF2_TS_XX2_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_0, + MSEL2CR_MSEL12_1), + PINMUX_DATA(TSIF2_TS_XX3_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_1, + MSEL2CR_MSEL12_0), + PINMUX_DATA(TSIF2_TS_XX4_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_1, + MSEL2CR_MSEL12_1), + PINMUX_DATA(TSIF2_TS_XX5_MARK, MSEL2CR_MSEL14_1, MSEL2CR_MSEL13_0, + MSEL2CR_MSEL12_0), + PINMUX_DATA(TSIF1_TS_XX1_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_0, + MSEL2CR_MSEL9_0), + PINMUX_DATA(TSIF1_TS_XX2_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_0, + MSEL2CR_MSEL9_1), + PINMUX_DATA(TSIF1_TS_XX3_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_1, + MSEL2CR_MSEL9_0), + PINMUX_DATA(TSIF1_TS_XX4_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_1, + MSEL2CR_MSEL9_1), + PINMUX_DATA(TSIF1_TS_XX5_MARK, MSEL2CR_MSEL11_1, MSEL2CR_MSEL10_0, + MSEL2CR_MSEL9_0), + PINMUX_DATA(TSIF0_TS_XX1_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_0, + MSEL2CR_MSEL6_0), + PINMUX_DATA(TSIF0_TS_XX2_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_0, + MSEL2CR_MSEL6_1), + PINMUX_DATA(TSIF0_TS_XX3_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_1, + MSEL2CR_MSEL6_0), + PINMUX_DATA(TSIF0_TS_XX4_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_1, + MSEL2CR_MSEL6_1), + PINMUX_DATA(TSIF0_TS_XX5_MARK, MSEL2CR_MSEL8_1, MSEL2CR_MSEL7_0, + MSEL2CR_MSEL6_0), + PINMUX_DATA(MST1_TS_XX1_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_0, + MSEL2CR_MSEL3_0), + PINMUX_DATA(MST1_TS_XX2_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_0, + MSEL2CR_MSEL3_1), + PINMUX_DATA(MST1_TS_XX3_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_1, + MSEL2CR_MSEL3_0), + PINMUX_DATA(MST1_TS_XX4_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_1, + MSEL2CR_MSEL3_1), + PINMUX_DATA(MST1_TS_XX5_MARK, MSEL2CR_MSEL5_1, MSEL2CR_MSEL4_0, + MSEL2CR_MSEL3_0), + PINMUX_DATA(MST0_TS_XX1_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_0, + MSEL2CR_MSEL0_0), + PINMUX_DATA(MST0_TS_XX2_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_0, + MSEL2CR_MSEL0_1), + PINMUX_DATA(MST0_TS_XX3_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_1, + MSEL2CR_MSEL0_0), + PINMUX_DATA(MST0_TS_XX4_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_1, + MSEL2CR_MSEL0_1), + PINMUX_DATA(MST0_TS_XX5_MARK, MSEL2CR_MSEL2_1, MSEL2CR_MSEL1_0, + MSEL2CR_MSEL0_0), + + /* MSEL3 special cases */ + PINMUX_DATA(SDHI0_VCCQ_MC0_ON_MARK, MSEL3CR_MSEL28_1), + PINMUX_DATA(SDHI0_VCCQ_MC0_OFF_MARK, MSEL3CR_MSEL28_0), + PINMUX_DATA(DEBUG_MON_VIO_MARK, MSEL3CR_MSEL15_0), + PINMUX_DATA(DEBUG_MON_LCDD_MARK, MSEL3CR_MSEL15_1), + PINMUX_DATA(LCDC_LCDC0_MARK, MSEL3CR_MSEL6_0), + PINMUX_DATA(LCDC_LCDC1_MARK, MSEL3CR_MSEL6_1), + + /* MSEL4 special cases */ + PINMUX_DATA(IRQ9_MEM_INT_MARK, MSEL4CR_MSEL29_0), + PINMUX_DATA(IRQ9_MCP_INT_MARK, MSEL4CR_MSEL29_1), + PINMUX_DATA(A11_MARK, MSEL4CR_MSEL13_0, MSEL4CR_MSEL12_0), + PINMUX_DATA(KEYOUT8_MARK, MSEL4CR_MSEL13_0, MSEL4CR_MSEL12_1), + PINMUX_DATA(TPU4TO3_MARK, MSEL4CR_MSEL13_1, MSEL4CR_MSEL12_0), + PINMUX_DATA(RESETA_N_PU_ON_MARK, MSEL4CR_MSEL4_0), + PINMUX_DATA(RESETA_N_PU_OFF_MARK, MSEL4CR_MSEL4_1), + PINMUX_DATA(EDBGREQ_PD_MARK, MSEL4CR_MSEL1_0), + PINMUX_DATA(EDBGREQ_PU_MARK, MSEL4CR_MSEL1_1), + + /* Functions with pull-ups */ + PINMUX_DATA(KEYIN0_PU_MARK, PORT66_FN2, PORT66_IN_PU), + PINMUX_DATA(KEYIN1_PU_MARK, PORT67_FN2, PORT67_IN_PU), + PINMUX_DATA(KEYIN2_PU_MARK, PORT68_FN2, PORT68_IN_PU), + PINMUX_DATA(KEYIN3_PU_MARK, PORT69_FN2, PORT69_IN_PU), + PINMUX_DATA(KEYIN4_PU_MARK, PORT70_FN2, PORT70_IN_PU), + PINMUX_DATA(KEYIN5_PU_MARK, PORT71_FN2, PORT71_IN_PU), + PINMUX_DATA(KEYIN6_PU_MARK, PORT72_FN2, PORT72_IN_PU), + PINMUX_DATA(KEYIN7_PU_MARK, PORT73_FN2, PORT73_IN_PU), + + PINMUX_DATA(SDHICD0_PU_MARK, PORT251_FN1, PORT251_IN_PU), + PINMUX_DATA(SDHID0_0_PU_MARK, PORT252_FN1, PORT252_IN_PU), + PINMUX_DATA(SDHID0_1_PU_MARK, PORT253_FN1, PORT253_IN_PU), + PINMUX_DATA(SDHID0_2_PU_MARK, PORT254_FN1, PORT254_IN_PU), + PINMUX_DATA(SDHID0_3_PU_MARK, PORT255_FN1, PORT255_IN_PU), + PINMUX_DATA(SDHICMD0_PU_MARK, PORT256_FN1, PORT256_IN_PU), + PINMUX_DATA(SDHIWP0_PU_MARK, PORT257_FN1, PORT256_IN_PU), + PINMUX_DATA(SDHID1_0_PU_MARK, PORT259_FN1, PORT259_IN_PU), + PINMUX_DATA(SDHID1_1_PU_MARK, PORT260_FN1, PORT260_IN_PU), + PINMUX_DATA(SDHID1_2_PU_MARK, PORT261_FN1, PORT261_IN_PU), + PINMUX_DATA(SDHID1_3_PU_MARK, PORT262_FN1, PORT262_IN_PU), + PINMUX_DATA(SDHICMD1_PU_MARK, PORT263_FN1, PORT263_IN_PU), + PINMUX_DATA(SDHID2_0_PU_MARK, PORT265_FN1, PORT265_IN_PU), + PINMUX_DATA(SDHID2_1_PU_MARK, PORT266_FN1, PORT266_IN_PU), + PINMUX_DATA(SDHID2_2_PU_MARK, PORT267_FN1, PORT267_IN_PU), + PINMUX_DATA(SDHID2_3_PU_MARK, PORT268_FN1, PORT268_IN_PU), + PINMUX_DATA(SDHICMD2_PU_MARK, PORT269_FN1, PORT269_IN_PU), + + PINMUX_DATA(MMCCMD0_PU_MARK, PORT279_FN1, PORT279_IN_PU, + MSEL4CR_MSEL15_0), + PINMUX_DATA(MMCCMD1_PU_MARK, PORT297_FN2, PORT297_IN_PU, + MSEL4CR_MSEL15_1), + + PINMUX_DATA(MMCD0_0_PU_MARK, + PORT271_FN1, PORT271_IN_PU, MSEL4CR_MSEL15_0), + PINMUX_DATA(MMCD0_1_PU_MARK, + PORT272_FN1, PORT272_IN_PU, MSEL4CR_MSEL15_0), + PINMUX_DATA(MMCD0_2_PU_MARK, + PORT273_FN1, PORT273_IN_PU, MSEL4CR_MSEL15_0), + PINMUX_DATA(MMCD0_3_PU_MARK, + PORT274_FN1, PORT274_IN_PU, MSEL4CR_MSEL15_0), + PINMUX_DATA(MMCD0_4_PU_MARK, + PORT275_FN1, PORT275_IN_PU, MSEL4CR_MSEL15_0), + PINMUX_DATA(MMCD0_5_PU_MARK, + PORT276_FN1, PORT276_IN_PU, MSEL4CR_MSEL15_0), + PINMUX_DATA(MMCD0_6_PU_MARK, + PORT277_FN1, PORT277_IN_PU, MSEL4CR_MSEL15_0), + PINMUX_DATA(MMCD0_7_PU_MARK, + PORT278_FN1, PORT278_IN_PU, MSEL4CR_MSEL15_0), + + PINMUX_DATA(FSIBISLD_PU_MARK, PORT39_FN1, PORT39_IN_PU), + PINMUX_DATA(FSIACK_PU_MARK, PORT49_FN1, PORT49_IN_PU), + PINMUX_DATA(FSIAILR_PU_MARK, PORT50_FN5, PORT50_IN_PU), + PINMUX_DATA(FSIAIBT_PU_MARK, PORT51_FN5, PORT51_IN_PU), + PINMUX_DATA(FSIAISLD_PU_MARK, PORT55_FN1, PORT55_IN_PU), +}; + +static struct pinmux_gpio pinmux_gpios[] = { + GPIO_PORT_ALL(), + + /* Table 25-1 (Functions 0-7) */ + GPIO_FN(VBUS_0), + GPIO_FN(GPI0), + GPIO_FN(GPI1), + GPIO_FN(GPI2), + GPIO_FN(GPI3), + GPIO_FN(GPI4), + GPIO_FN(GPI5), + GPIO_FN(GPI6), + GPIO_FN(GPI7), + GPIO_FN(SCIFA7_RXD), + GPIO_FN(SCIFA7_CTS_), + GPIO_FN(GPO7), \ + GPIO_FN(MFG0_OUT2), + GPIO_FN(GPO6), \ + GPIO_FN(MFG1_OUT2), + GPIO_FN(GPO5), \ + GPIO_FN(SCIFA0_SCK), \ + GPIO_FN(FSICOSLDT3), \ + GPIO_FN(PORT16_VIO_CKOR), + GPIO_FN(SCIFA0_TXD), + GPIO_FN(SCIFA7_TXD), + GPIO_FN(SCIFA7_RTS_), \ + GPIO_FN(PORT19_VIO_CKO2), + GPIO_FN(GPO0), + GPIO_FN(GPO1), + GPIO_FN(GPO2), \ + GPIO_FN(STATUS0), + GPIO_FN(GPO3), \ + GPIO_FN(STATUS1), + GPIO_FN(GPO4), \ + GPIO_FN(STATUS2), + GPIO_FN(VINT), + GPIO_FN(TCKON), + GPIO_FN(XDVFS1), \ + GPIO_FN(PORT27_I2C_SCL2), \ + GPIO_FN(PORT27_I2C_SCL3), \ + GPIO_FN(MFG0_OUT1), \ + GPIO_FN(PORT27_IROUT), + GPIO_FN(XDVFS2), \ + GPIO_FN(PORT28_I2C_SDA2), \ + GPIO_FN(PORT28_I2C_SDA3), \ + GPIO_FN(PORT28_TPU1TO1), + GPIO_FN(SIM_RST), \ + GPIO_FN(PORT29_TPU1TO1), + GPIO_FN(SIM_CLK), \ + GPIO_FN(PORT30_VIO_CKOR), + GPIO_FN(SIM_D), \ + GPIO_FN(PORT31_IROUT), + GPIO_FN(SCIFA4_TXD), + GPIO_FN(SCIFA4_RXD), \ + GPIO_FN(XWUP), + GPIO_FN(SCIFA4_RTS_), + GPIO_FN(SCIFA4_CTS_), + GPIO_FN(FSIBOBT), \ + GPIO_FN(FSIBIBT), + GPIO_FN(FSIBOLR), \ + GPIO_FN(FSIBILR), + GPIO_FN(FSIBOSLD), + GPIO_FN(FSIBISLD), + GPIO_FN(VACK), + GPIO_FN(XTAL1L), + GPIO_FN(SCIFA0_RTS_), \ + GPIO_FN(FSICOSLDT2), + GPIO_FN(SCIFA0_RXD), + GPIO_FN(SCIFA0_CTS_), \ + GPIO_FN(FSICOSLDT1), + GPIO_FN(FSICOBT), \ + GPIO_FN(FSICIBT), \ + GPIO_FN(FSIDOBT), \ + GPIO_FN(FSIDIBT), + GPIO_FN(FSICOLR), \ + GPIO_FN(FSICILR), \ + GPIO_FN(FSIDOLR), \ + GPIO_FN(FSIDILR), + GPIO_FN(FSICOSLD), \ + GPIO_FN(PORT47_FSICSPDIF), + GPIO_FN(FSICISLD), \ + GPIO_FN(FSIDISLD), + GPIO_FN(FSIACK), \ + GPIO_FN(PORT49_IRDA_OUT), \ + GPIO_FN(PORT49_IROUT), \ + GPIO_FN(FSIAOMC), + GPIO_FN(FSIAOLR), \ + GPIO_FN(BBIF2_TSYNC2), \ + GPIO_FN(TPU2TO2), \ + GPIO_FN(FSIAILR), + + GPIO_FN(FSIAOBT), \ + GPIO_FN(BBIF2_TSCK2), \ + GPIO_FN(TPU2TO3), \ + GPIO_FN(FSIAIBT), + GPIO_FN(FSIAOSLD), \ + GPIO_FN(BBIF2_TXD2), + GPIO_FN(FSIASPDIF), \ + GPIO_FN(PORT53_IRDA_IN), \ + GPIO_FN(TPU3TO3), \ + GPIO_FN(FSIBSPDIF), \ + GPIO_FN(PORT53_FSICSPDIF), + GPIO_FN(FSIBCK), \ + GPIO_FN(PORT54_IRDA_FIRSEL), \ + GPIO_FN(TPU3TO2), \ + GPIO_FN(FSIBOMC), \ + GPIO_FN(FSICCK), \ + GPIO_FN(FSICOMC), + GPIO_FN(FSIAISLD), \ + GPIO_FN(TPU0TO0), + GPIO_FN(A0), \ + GPIO_FN(BS_), + GPIO_FN(A12), \ + GPIO_FN(PORT58_KEYOUT7), \ + GPIO_FN(TPU4TO2), + GPIO_FN(A13), \ + GPIO_FN(PORT59_KEYOUT6), \ + GPIO_FN(TPU0TO1), + GPIO_FN(A14), \ + GPIO_FN(KEYOUT5), + GPIO_FN(A15), \ + GPIO_FN(KEYOUT4), + GPIO_FN(A16), \ + GPIO_FN(KEYOUT3), \ + GPIO_FN(MSIOF0_SS1), + GPIO_FN(A17), \ + GPIO_FN(KEYOUT2), \ + GPIO_FN(MSIOF0_TSYNC), + GPIO_FN(A18), \ + GPIO_FN(KEYOUT1), \ + GPIO_FN(MSIOF0_TSCK), + GPIO_FN(A19), \ + GPIO_FN(KEYOUT0), \ + GPIO_FN(MSIOF0_TXD), + GPIO_FN(A20), \ + GPIO_FN(KEYIN0), \ + GPIO_FN(MSIOF0_RSCK), + GPIO_FN(A21), \ + GPIO_FN(KEYIN1), \ + GPIO_FN(MSIOF0_RSYNC), + GPIO_FN(A22), \ + GPIO_FN(KEYIN2), \ + GPIO_FN(MSIOF0_MCK0), + GPIO_FN(A23), \ + GPIO_FN(KEYIN3), \ + GPIO_FN(MSIOF0_MCK1), + GPIO_FN(A24), \ + GPIO_FN(KEYIN4), \ + GPIO_FN(MSIOF0_RXD), + GPIO_FN(A25), \ + GPIO_FN(KEYIN5), \ + GPIO_FN(MSIOF0_SS2), + GPIO_FN(A26), \ + GPIO_FN(KEYIN6), + GPIO_FN(KEYIN7), + GPIO_FN(D0_NAF0), + GPIO_FN(D1_NAF1), + GPIO_FN(D2_NAF2), + GPIO_FN(D3_NAF3), + GPIO_FN(D4_NAF4), + GPIO_FN(D5_NAF5), + GPIO_FN(D6_NAF6), + GPIO_FN(D7_NAF7), + GPIO_FN(D8_NAF8), + GPIO_FN(D9_NAF9), + GPIO_FN(D10_NAF10), + GPIO_FN(D11_NAF11), + GPIO_FN(D12_NAF12), + GPIO_FN(D13_NAF13), + GPIO_FN(D14_NAF14), + GPIO_FN(D15_NAF15), + GPIO_FN(CS4_), + GPIO_FN(CS5A_), \ + GPIO_FN(PORT91_RDWR), + GPIO_FN(CS5B_), \ + GPIO_FN(FCE1_), + GPIO_FN(CS6B_), \ + GPIO_FN(DACK0), + GPIO_FN(FCE0_), \ + GPIO_FN(CS6A_), + GPIO_FN(WAIT_), \ + GPIO_FN(DREQ0), + GPIO_FN(RD__FSC), + GPIO_FN(WE0__FWE), \ + GPIO_FN(RDWR_FWE), + GPIO_FN(WE1_), + GPIO_FN(FRB), + GPIO_FN(CKO), + GPIO_FN(NBRSTOUT_), + GPIO_FN(NBRST_), + GPIO_FN(BBIF2_TXD), + GPIO_FN(BBIF2_RXD), + GPIO_FN(BBIF2_SYNC), + GPIO_FN(BBIF2_SCK), + GPIO_FN(SCIFA3_CTS_), \ + GPIO_FN(MFG3_IN2), + GPIO_FN(SCIFA3_RXD), \ + GPIO_FN(MFG3_IN1), + GPIO_FN(BBIF1_SS2), \ + GPIO_FN(SCIFA3_RTS_), \ + GPIO_FN(MFG3_OUT1), + GPIO_FN(SCIFA3_TXD), + GPIO_FN(HSI_RX_DATA), \ + GPIO_FN(BBIF1_RXD), + GPIO_FN(HSI_TX_WAKE), \ + GPIO_FN(BBIF1_TSCK), + GPIO_FN(HSI_TX_DATA), \ + GPIO_FN(BBIF1_TSYNC), + GPIO_FN(HSI_TX_READY), \ + GPIO_FN(BBIF1_TXD), + GPIO_FN(HSI_RX_READY), \ + GPIO_FN(BBIF1_RSCK), \ + GPIO_FN(PORT115_I2C_SCL2), \ + GPIO_FN(PORT115_I2C_SCL3), + GPIO_FN(HSI_RX_WAKE), \ + GPIO_FN(BBIF1_RSYNC), \ + GPIO_FN(PORT116_I2C_SDA2), \ + GPIO_FN(PORT116_I2C_SDA3), + GPIO_FN(HSI_RX_FLAG), \ + GPIO_FN(BBIF1_SS1), \ + GPIO_FN(BBIF1_FLOW), + GPIO_FN(HSI_TX_FLAG), + GPIO_FN(VIO_VD), \ + GPIO_FN(PORT128_LCD2VSYN), \ + GPIO_FN(VIO2_VD), \ + GPIO_FN(LCD2D0), + + GPIO_FN(VIO_HD), \ + GPIO_FN(PORT129_LCD2HSYN), \ + GPIO_FN(PORT129_LCD2CS_), \ + GPIO_FN(VIO2_HD), \ + GPIO_FN(LCD2D1), + GPIO_FN(VIO_D0), \ + GPIO_FN(PORT130_MSIOF2_RXD), \ + GPIO_FN(LCD2D10), + GPIO_FN(VIO_D1), \ + GPIO_FN(PORT131_KEYOUT6), \ + GPIO_FN(PORT131_MSIOF2_SS1), \ + GPIO_FN(PORT131_KEYOUT11), \ + GPIO_FN(LCD2D11), + GPIO_FN(VIO_D2), \ + GPIO_FN(PORT132_KEYOUT7), \ + GPIO_FN(PORT132_MSIOF2_SS2), \ + GPIO_FN(PORT132_KEYOUT10), \ + GPIO_FN(LCD2D12), + GPIO_FN(VIO_D3), \ + GPIO_FN(MSIOF2_TSYNC), \ + GPIO_FN(LCD2D13), + GPIO_FN(VIO_D4), \ + GPIO_FN(MSIOF2_TXD), \ + GPIO_FN(LCD2D14), + GPIO_FN(VIO_D5), \ + GPIO_FN(MSIOF2_TSCK), \ + GPIO_FN(LCD2D15), + GPIO_FN(VIO_D6), \ + GPIO_FN(PORT136_KEYOUT8), \ + GPIO_FN(LCD2D16), + GPIO_FN(VIO_D7), \ + GPIO_FN(PORT137_KEYOUT9), \ + GPIO_FN(LCD2D17), + GPIO_FN(VIO_D8), \ + GPIO_FN(PORT138_KEYOUT8), \ + GPIO_FN(VIO2_D0), \ + GPIO_FN(LCD2D6), + GPIO_FN(VIO_D9), \ + GPIO_FN(PORT139_KEYOUT9), \ + GPIO_FN(VIO2_D1), \ + GPIO_FN(LCD2D7), + GPIO_FN(VIO_D10), \ + GPIO_FN(TPU0TO2), \ + GPIO_FN(VIO2_D2), \ + GPIO_FN(LCD2D8), + GPIO_FN(VIO_D11), \ + GPIO_FN(TPU0TO3), \ + GPIO_FN(VIO2_D3), \ + GPIO_FN(LCD2D9), + GPIO_FN(VIO_D12), \ + GPIO_FN(PORT142_KEYOUT10), \ + GPIO_FN(VIO2_D4), \ + GPIO_FN(LCD2D2), + GPIO_FN(VIO_D13), \ + GPIO_FN(PORT143_KEYOUT11), \ + GPIO_FN(PORT143_KEYOUT6), \ + GPIO_FN(VIO2_D5), \ + GPIO_FN(LCD2D3), + GPIO_FN(VIO_D14), \ + GPIO_FN(PORT144_KEYOUT7), \ + GPIO_FN(VIO2_D6), \ + GPIO_FN(LCD2D4), + GPIO_FN(VIO_D15), \ + GPIO_FN(TPU1TO3), \ + GPIO_FN(PORT145_LCD2DISP), \ + GPIO_FN(PORT145_LCD2RS), \ + GPIO_FN(VIO2_D7), \ + GPIO_FN(LCD2D5), + GPIO_FN(VIO_CLK), \ + GPIO_FN(LCD2DCK), \ + GPIO_FN(PORT146_LCD2WR_), \ + GPIO_FN(VIO2_CLK), \ + GPIO_FN(LCD2D18), + GPIO_FN(VIO_FIELD), \ + GPIO_FN(LCD2RD_), \ + GPIO_FN(VIO2_FIELD), \ + GPIO_FN(LCD2D19), + GPIO_FN(VIO_CKO), + GPIO_FN(A27), \ + GPIO_FN(PORT149_RDWR), \ + GPIO_FN(MFG0_IN1), \ + GPIO_FN(PORT149_KEYOUT9), + GPIO_FN(MFG0_IN2), + GPIO_FN(TS_SPSYNC3), \ + GPIO_FN(MSIOF2_RSCK), + GPIO_FN(TS_SDAT3), \ + GPIO_FN(MSIOF2_RSYNC), + GPIO_FN(TPU1TO2), \ + GPIO_FN(TS_SDEN3), \ + GPIO_FN(PORT153_MSIOF2_SS1), + GPIO_FN(SCIFA2_TXD1), \ + GPIO_FN(MSIOF2_MCK0), + GPIO_FN(SCIFA2_RXD1), \ + GPIO_FN(MSIOF2_MCK1), + GPIO_FN(SCIFA2_RTS1_), \ + GPIO_FN(PORT156_MSIOF2_SS2), + GPIO_FN(SCIFA2_CTS1_), \ + GPIO_FN(PORT157_MSIOF2_RXD), + GPIO_FN(DINT_), \ + GPIO_FN(SCIFA2_SCK1), \ + GPIO_FN(TS_SCK3), + GPIO_FN(PORT159_SCIFB_SCK), \ + GPIO_FN(PORT159_SCIFA5_SCK), \ + GPIO_FN(NMI), + GPIO_FN(PORT160_SCIFB_TXD), \ + GPIO_FN(PORT160_SCIFA5_TXD), + GPIO_FN(PORT161_SCIFB_CTS_), \ + GPIO_FN(PORT161_SCIFA5_CTS_), + GPIO_FN(PORT162_SCIFB_RXD), \ + GPIO_FN(PORT162_SCIFA5_RXD), + GPIO_FN(PORT163_SCIFB_RTS_), \ + GPIO_FN(PORT163_SCIFA5_RTS_), \ + GPIO_FN(TPU3TO0), + GPIO_FN(LCDD0), + GPIO_FN(LCDD1), \ + GPIO_FN(PORT193_SCIFA5_CTS_), \ + GPIO_FN(BBIF2_TSYNC1), + GPIO_FN(LCDD2), \ + GPIO_FN(PORT194_SCIFA5_RTS_), \ + GPIO_FN(BBIF2_TSCK1), + GPIO_FN(LCDD3), \ + GPIO_FN(PORT195_SCIFA5_RXD), \ + GPIO_FN(BBIF2_TXD1), + GPIO_FN(LCDD4), \ + GPIO_FN(PORT196_SCIFA5_TXD), + GPIO_FN(LCDD5), \ + GPIO_FN(PORT197_SCIFA5_SCK), \ + GPIO_FN(MFG2_OUT2), \ + GPIO_FN(TPU2TO1), + GPIO_FN(LCDD6), + GPIO_FN(LCDD7), \ + GPIO_FN(TPU4TO1), \ + GPIO_FN(MFG4_OUT2), + GPIO_FN(LCDD8), \ + GPIO_FN(D16), + GPIO_FN(LCDD9), \ + GPIO_FN(D17), + GPIO_FN(LCDD10), \ + GPIO_FN(D18), + GPIO_FN(LCDD11), \ + GPIO_FN(D19), + GPIO_FN(LCDD12), \ + GPIO_FN(D20), + GPIO_FN(LCDD13), \ + GPIO_FN(D21), + GPIO_FN(LCDD14), \ + GPIO_FN(D22), + GPIO_FN(LCDD15), \ + GPIO_FN(PORT207_MSIOF0L_SS1), \ + GPIO_FN(D23), + GPIO_FN(LCDD16), \ + GPIO_FN(PORT208_MSIOF0L_SS2), \ + GPIO_FN(D24), + GPIO_FN(LCDD17), \ + GPIO_FN(D25), + GPIO_FN(LCDD18), \ + GPIO_FN(DREQ2), \ + GPIO_FN(PORT210_MSIOF0L_SS1), \ + GPIO_FN(D26), + GPIO_FN(LCDD19), \ + GPIO_FN(PORT211_MSIOF0L_SS2), \ + GPIO_FN(D27), + GPIO_FN(LCDD20), \ + GPIO_FN(TS_SPSYNC1), \ + GPIO_FN(MSIOF0L_MCK0), \ + GPIO_FN(D28), + GPIO_FN(LCDD21), \ + GPIO_FN(TS_SDAT1), \ + GPIO_FN(MSIOF0L_MCK1), \ + GPIO_FN(D29), + GPIO_FN(LCDD22), \ + GPIO_FN(TS_SDEN1), \ + GPIO_FN(MSIOF0L_RSCK), \ + GPIO_FN(D30), + GPIO_FN(LCDD23), \ + GPIO_FN(TS_SCK1), \ + GPIO_FN(MSIOF0L_RSYNC), \ + GPIO_FN(D31), + GPIO_FN(LCDDCK), \ + GPIO_FN(LCDWR_), + GPIO_FN(LCDRD_), \ + GPIO_FN(DACK2), \ + GPIO_FN(PORT217_LCD2RS), \ + GPIO_FN(MSIOF0L_TSYNC), \ + GPIO_FN(VIO2_FIELD3), \ + GPIO_FN(PORT217_LCD2DISP), + GPIO_FN(LCDHSYN), \ + GPIO_FN(LCDCS_), \ + GPIO_FN(LCDCS2_), \ + GPIO_FN(DACK3), \ + GPIO_FN(PORT218_VIO_CKOR), + GPIO_FN(LCDDISP), \ + GPIO_FN(LCDRS), \ + GPIO_FN(PORT219_LCD2WR_), \ + GPIO_FN(DREQ3), \ + GPIO_FN(MSIOF0L_TSCK), \ + GPIO_FN(VIO2_CLK3), \ + GPIO_FN(LCD2DCK_2), + GPIO_FN(LCDVSYN), \ + GPIO_FN(LCDVSYN2), + GPIO_FN(LCDLCLK), \ + GPIO_FN(DREQ1), \ + GPIO_FN(PORT221_LCD2CS_), \ + GPIO_FN(PWEN), \ + GPIO_FN(MSIOF0L_RXD), \ + GPIO_FN(VIO2_HD3), \ + GPIO_FN(PORT221_LCD2HSYN), + GPIO_FN(LCDDON), \ + GPIO_FN(LCDDON2), \ + GPIO_FN(DACK1), \ + GPIO_FN(OVCN), \ + GPIO_FN(MSIOF0L_TXD), \ + GPIO_FN(VIO2_VD3), \ + GPIO_FN(PORT222_LCD2VSYN), + + GPIO_FN(SCIFA1_TXD), \ + GPIO_FN(OVCN2), + GPIO_FN(EXTLP), \ + GPIO_FN(SCIFA1_SCK), \ + GPIO_FN(PORT226_VIO_CKO2), + GPIO_FN(SCIFA1_RTS_), \ + GPIO_FN(IDIN), + GPIO_FN(SCIFA1_RXD), + GPIO_FN(SCIFA1_CTS_), \ + GPIO_FN(MFG1_IN1), + GPIO_FN(MSIOF1_TXD), \ + GPIO_FN(SCIFA2_TXD2), + GPIO_FN(MSIOF1_TSYNC), \ + GPIO_FN(SCIFA2_CTS2_), + GPIO_FN(MSIOF1_TSCK), \ + GPIO_FN(SCIFA2_SCK2), + GPIO_FN(MSIOF1_RXD), \ + GPIO_FN(SCIFA2_RXD2), + GPIO_FN(MSIOF1_RSCK), \ + GPIO_FN(SCIFA2_RTS2_), \ + GPIO_FN(VIO2_CLK2), \ + GPIO_FN(LCD2D20), + GPIO_FN(MSIOF1_RSYNC), \ + GPIO_FN(MFG1_IN2), \ + GPIO_FN(VIO2_VD2), \ + GPIO_FN(LCD2D21), + GPIO_FN(MSIOF1_MCK0), \ + GPIO_FN(PORT236_I2C_SDA2), + GPIO_FN(MSIOF1_MCK1), \ + GPIO_FN(PORT237_I2C_SCL2), + GPIO_FN(MSIOF1_SS1), \ + GPIO_FN(VIO2_FIELD2), \ + GPIO_FN(LCD2D22), + GPIO_FN(MSIOF1_SS2), \ + GPIO_FN(VIO2_HD2), \ + GPIO_FN(LCD2D23), + GPIO_FN(SCIFA6_TXD), + GPIO_FN(PORT241_IRDA_OUT), \ + GPIO_FN(PORT241_IROUT), \ + GPIO_FN(MFG4_OUT1), \ + GPIO_FN(TPU4TO0), + GPIO_FN(PORT242_IRDA_IN), \ + GPIO_FN(MFG4_IN2), + GPIO_FN(PORT243_IRDA_FIRSEL), \ + GPIO_FN(PORT243_VIO_CKO2), + GPIO_FN(PORT244_SCIFA5_CTS_), \ + GPIO_FN(MFG2_IN1), \ + GPIO_FN(PORT244_SCIFB_CTS_), \ + GPIO_FN(MSIOF2R_RXD), + GPIO_FN(PORT245_SCIFA5_RTS_), \ + GPIO_FN(MFG2_IN2), \ + GPIO_FN(PORT245_SCIFB_RTS_), \ + GPIO_FN(MSIOF2R_TXD), + GPIO_FN(PORT246_SCIFA5_RXD), \ + GPIO_FN(MFG1_OUT1), \ + GPIO_FN(PORT246_SCIFB_RXD), \ + GPIO_FN(TPU1TO0), + GPIO_FN(PORT247_SCIFA5_TXD), \ + GPIO_FN(MFG3_OUT2), \ + GPIO_FN(PORT247_SCIFB_TXD), \ + GPIO_FN(TPU3TO1), + GPIO_FN(PORT248_SCIFA5_SCK), \ + GPIO_FN(MFG2_OUT1), \ + GPIO_FN(PORT248_SCIFB_SCK), \ + GPIO_FN(TPU2TO0), \ + GPIO_FN(PORT248_I2C_SCL3), \ + GPIO_FN(MSIOF2R_TSCK), + GPIO_FN(PORT249_IROUT), \ + GPIO_FN(MFG4_IN1), \ + GPIO_FN(PORT249_I2C_SDA3), \ + GPIO_FN(MSIOF2R_TSYNC), + GPIO_FN(SDHICLK0), + GPIO_FN(SDHICD0), + GPIO_FN(SDHID0_0), + GPIO_FN(SDHID0_1), + GPIO_FN(SDHID0_2), + GPIO_FN(SDHID0_3), + GPIO_FN(SDHICMD0), + GPIO_FN(SDHIWP0), + GPIO_FN(SDHICLK1), + GPIO_FN(SDHID1_0), \ + GPIO_FN(TS_SPSYNC2), + GPIO_FN(SDHID1_1), \ + GPIO_FN(TS_SDAT2), + GPIO_FN(SDHID1_2), \ + GPIO_FN(TS_SDEN2), + GPIO_FN(SDHID1_3), \ + GPIO_FN(TS_SCK2), + GPIO_FN(SDHICMD1), + GPIO_FN(SDHICLK2), + GPIO_FN(SDHID2_0), \ + GPIO_FN(TS_SPSYNC4), + GPIO_FN(SDHID2_1), \ + GPIO_FN(TS_SDAT4), + GPIO_FN(SDHID2_2), \ + GPIO_FN(TS_SDEN4), + GPIO_FN(SDHID2_3), \ + GPIO_FN(TS_SCK4), + GPIO_FN(SDHICMD2), + GPIO_FN(MMCCLK0), + GPIO_FN(MMCD0_0), + GPIO_FN(MMCD0_1), + GPIO_FN(MMCD0_2), + GPIO_FN(MMCD0_3), + GPIO_FN(MMCD0_4), \ + GPIO_FN(TS_SPSYNC5), + GPIO_FN(MMCD0_5), \ + GPIO_FN(TS_SDAT5), + GPIO_FN(MMCD0_6), \ + GPIO_FN(TS_SDEN5), + GPIO_FN(MMCD0_7), \ + GPIO_FN(TS_SCK5), + GPIO_FN(MMCCMD0), + GPIO_FN(RESETOUTS_), \ + GPIO_FN(EXTAL2OUT), + GPIO_FN(MCP_WAIT__MCP_FRB), + GPIO_FN(MCP_CKO), \ + GPIO_FN(MMCCLK1), + GPIO_FN(MCP_D15_MCP_NAF15), + GPIO_FN(MCP_D14_MCP_NAF14), + GPIO_FN(MCP_D13_MCP_NAF13), + GPIO_FN(MCP_D12_MCP_NAF12), + GPIO_FN(MCP_D11_MCP_NAF11), + GPIO_FN(MCP_D10_MCP_NAF10), + GPIO_FN(MCP_D9_MCP_NAF9), + GPIO_FN(MCP_D8_MCP_NAF8), \ + GPIO_FN(MMCCMD1), + GPIO_FN(MCP_D7_MCP_NAF7), \ + GPIO_FN(MMCD1_7), + + GPIO_FN(MCP_D6_MCP_NAF6), \ + GPIO_FN(MMCD1_6), + GPIO_FN(MCP_D5_MCP_NAF5), \ + GPIO_FN(MMCD1_5), + GPIO_FN(MCP_D4_MCP_NAF4), \ + GPIO_FN(MMCD1_4), + GPIO_FN(MCP_D3_MCP_NAF3), \ + GPIO_FN(MMCD1_3), + GPIO_FN(MCP_D2_MCP_NAF2), \ + GPIO_FN(MMCD1_2), + GPIO_FN(MCP_D1_MCP_NAF1), \ + GPIO_FN(MMCD1_1), + GPIO_FN(MCP_D0_MCP_NAF0), \ + GPIO_FN(MMCD1_0), + GPIO_FN(MCP_NBRSTOUT_), + GPIO_FN(MCP_WE0__MCP_FWE), \ + GPIO_FN(MCP_RDWR_MCP_FWE), + + /* MSEL2 special cases */ + GPIO_FN(TSIF2_TS_XX1), + GPIO_FN(TSIF2_TS_XX2), + GPIO_FN(TSIF2_TS_XX3), + GPIO_FN(TSIF2_TS_XX4), + GPIO_FN(TSIF2_TS_XX5), + GPIO_FN(TSIF1_TS_XX1), + GPIO_FN(TSIF1_TS_XX2), + GPIO_FN(TSIF1_TS_XX3), + GPIO_FN(TSIF1_TS_XX4), + GPIO_FN(TSIF1_TS_XX5), + GPIO_FN(TSIF0_TS_XX1), + GPIO_FN(TSIF0_TS_XX2), + GPIO_FN(TSIF0_TS_XX3), + GPIO_FN(TSIF0_TS_XX4), + GPIO_FN(TSIF0_TS_XX5), + GPIO_FN(MST1_TS_XX1), + GPIO_FN(MST1_TS_XX2), + GPIO_FN(MST1_TS_XX3), + GPIO_FN(MST1_TS_XX4), + GPIO_FN(MST1_TS_XX5), + GPIO_FN(MST0_TS_XX1), + GPIO_FN(MST0_TS_XX2), + GPIO_FN(MST0_TS_XX3), + GPIO_FN(MST0_TS_XX4), + GPIO_FN(MST0_TS_XX5), + + /* MSEL3 special cases */ + GPIO_FN(SDHI0_VCCQ_MC0_ON), + GPIO_FN(SDHI0_VCCQ_MC0_OFF), + GPIO_FN(DEBUG_MON_VIO), + GPIO_FN(DEBUG_MON_LCDD), + GPIO_FN(LCDC_LCDC0), + GPIO_FN(LCDC_LCDC1), + + /* MSEL4 special cases */ + GPIO_FN(IRQ9_MEM_INT), + GPIO_FN(IRQ9_MCP_INT), + GPIO_FN(A11), + GPIO_FN(KEYOUT8), + GPIO_FN(TPU4TO3), + GPIO_FN(RESETA_N_PU_ON), + GPIO_FN(RESETA_N_PU_OFF), + GPIO_FN(EDBGREQ_PD), + GPIO_FN(EDBGREQ_PU), + + /* Functions with pull-ups */ + GPIO_FN(KEYIN0_PU), + GPIO_FN(KEYIN1_PU), + GPIO_FN(KEYIN2_PU), + GPIO_FN(KEYIN3_PU), + GPIO_FN(KEYIN4_PU), + GPIO_FN(KEYIN5_PU), + GPIO_FN(KEYIN6_PU), + GPIO_FN(KEYIN7_PU), + GPIO_FN(SDHICD0_PU), + GPIO_FN(SDHID0_0_PU), + GPIO_FN(SDHID0_1_PU), + GPIO_FN(SDHID0_2_PU), + GPIO_FN(SDHID0_3_PU), + GPIO_FN(SDHICMD0_PU), + GPIO_FN(SDHIWP0_PU), + GPIO_FN(SDHID1_0_PU), + GPIO_FN(SDHID1_1_PU), + GPIO_FN(SDHID1_2_PU), + GPIO_FN(SDHID1_3_PU), + GPIO_FN(SDHICMD1_PU), + GPIO_FN(SDHID2_0_PU), + GPIO_FN(SDHID2_1_PU), + GPIO_FN(SDHID2_2_PU), + GPIO_FN(SDHID2_3_PU), + GPIO_FN(SDHICMD2_PU), + GPIO_FN(MMCCMD0_PU), + GPIO_FN(MMCCMD1_PU), + GPIO_FN(MMCD0_0_PU), + GPIO_FN(MMCD0_1_PU), + GPIO_FN(MMCD0_2_PU), + GPIO_FN(MMCD0_3_PU), + GPIO_FN(MMCD0_4_PU), + GPIO_FN(MMCD0_5_PU), + GPIO_FN(MMCD0_6_PU), + GPIO_FN(MMCD0_7_PU), + GPIO_FN(FSIACK_PU), + GPIO_FN(FSIAILR_PU), + GPIO_FN(FSIAIBT_PU), + GPIO_FN(FSIAISLD_PU), +}; + +static struct pinmux_cfg_reg pinmux_config_regs[] = { + PORTCR(0, 0xe6050000), /* PORT0CR */ + PORTCR(1, 0xe6050001), /* PORT1CR */ + PORTCR(2, 0xe6050002), /* PORT2CR */ + PORTCR(3, 0xe6050003), /* PORT3CR */ + PORTCR(4, 0xe6050004), /* PORT4CR */ + PORTCR(5, 0xe6050005), /* PORT5CR */ + PORTCR(6, 0xe6050006), /* PORT6CR */ + PORTCR(7, 0xe6050007), /* PORT7CR */ + PORTCR(8, 0xe6050008), /* PORT8CR */ + PORTCR(9, 0xe6050009), /* PORT9CR */ + + PORTCR(10, 0xe605000a), /* PORT10CR */ + PORTCR(11, 0xe605000b), /* PORT11CR */ + PORTCR(12, 0xe605000c), /* PORT12CR */ + PORTCR(13, 0xe605000d), /* PORT13CR */ + PORTCR(14, 0xe605000e), /* PORT14CR */ + PORTCR(15, 0xe605000f), /* PORT15CR */ + PORTCR(16, 0xe6050010), /* PORT16CR */ + PORTCR(17, 0xe6050011), /* PORT17CR */ + PORTCR(18, 0xe6050012), /* PORT18CR */ + PORTCR(19, 0xe6050013), /* PORT19CR */ + + PORTCR(20, 0xe6050014), /* PORT20CR */ + PORTCR(21, 0xe6050015), /* PORT21CR */ + PORTCR(22, 0xe6050016), /* PORT22CR */ + PORTCR(23, 0xe6050017), /* PORT23CR */ + PORTCR(24, 0xe6050018), /* PORT24CR */ + PORTCR(25, 0xe6050019), /* PORT25CR */ + PORTCR(26, 0xe605001a), /* PORT26CR */ + PORTCR(27, 0xe605001b), /* PORT27CR */ + PORTCR(28, 0xe605001c), /* PORT28CR */ + PORTCR(29, 0xe605001d), /* PORT29CR */ + + PORTCR(30, 0xe605001e), /* PORT30CR */ + PORTCR(31, 0xe605001f), /* PORT31CR */ + PORTCR(32, 0xe6051020), /* PORT32CR */ + PORTCR(33, 0xe6051021), /* PORT33CR */ + PORTCR(34, 0xe6051022), /* PORT34CR */ + PORTCR(35, 0xe6051023), /* PORT35CR */ + PORTCR(36, 0xe6051024), /* PORT36CR */ + PORTCR(37, 0xe6051025), /* PORT37CR */ + PORTCR(38, 0xe6051026), /* PORT38CR */ + PORTCR(39, 0xe6051027), /* PORT39CR */ + + PORTCR(40, 0xe6051028), /* PORT40CR */ + PORTCR(41, 0xe6051029), /* PORT41CR */ + PORTCR(42, 0xe605102a), /* PORT42CR */ + PORTCR(43, 0xe605102b), /* PORT43CR */ + PORTCR(44, 0xe605102c), /* PORT44CR */ + PORTCR(45, 0xe605102d), /* PORT45CR */ + PORTCR(46, 0xe605102e), /* PORT46CR */ + PORTCR(47, 0xe605102f), /* PORT47CR */ + PORTCR(48, 0xe6051030), /* PORT48CR */ + PORTCR(49, 0xe6051031), /* PORT49CR */ + + PORTCR(50, 0xe6051032), /* PORT50CR */ + PORTCR(51, 0xe6051033), /* PORT51CR */ + PORTCR(52, 0xe6051034), /* PORT52CR */ + PORTCR(53, 0xe6051035), /* PORT53CR */ + PORTCR(54, 0xe6051036), /* PORT54CR */ + PORTCR(55, 0xe6051037), /* PORT55CR */ + PORTCR(56, 0xe6051038), /* PORT56CR */ + PORTCR(57, 0xe6051039), /* PORT57CR */ + PORTCR(58, 0xe605103a), /* PORT58CR */ + PORTCR(59, 0xe605103b), /* PORT59CR */ + + PORTCR(60, 0xe605103c), /* PORT60CR */ + PORTCR(61, 0xe605103d), /* PORT61CR */ + PORTCR(62, 0xe605103e), /* PORT62CR */ + PORTCR(63, 0xe605103f), /* PORT63CR */ + PORTCR(64, 0xe6051040), /* PORT64CR */ + PORTCR(65, 0xe6051041), /* PORT65CR */ + PORTCR(66, 0xe6051042), /* PORT66CR */ + PORTCR(67, 0xe6051043), /* PORT67CR */ + PORTCR(68, 0xe6051044), /* PORT68CR */ + PORTCR(69, 0xe6051045), /* PORT69CR */ + + PORTCR(70, 0xe6051046), /* PORT70CR */ + PORTCR(71, 0xe6051047), /* PORT71CR */ + PORTCR(72, 0xe6051048), /* PORT72CR */ + PORTCR(73, 0xe6051049), /* PORT73CR */ + PORTCR(74, 0xe605104a), /* PORT74CR */ + PORTCR(75, 0xe605104b), /* PORT75CR */ + PORTCR(76, 0xe605104c), /* PORT76CR */ + PORTCR(77, 0xe605104d), /* PORT77CR */ + PORTCR(78, 0xe605104e), /* PORT78CR */ + PORTCR(79, 0xe605104f), /* PORT79CR */ + + PORTCR(80, 0xe6051050), /* PORT80CR */ + PORTCR(81, 0xe6051051), /* PORT81CR */ + PORTCR(82, 0xe6051052), /* PORT82CR */ + PORTCR(83, 0xe6051053), /* PORT83CR */ + PORTCR(84, 0xe6051054), /* PORT84CR */ + PORTCR(85, 0xe6051055), /* PORT85CR */ + PORTCR(86, 0xe6051056), /* PORT86CR */ + PORTCR(87, 0xe6051057), /* PORT87CR */ + PORTCR(88, 0xe6051058), /* PORT88CR */ + PORTCR(89, 0xe6051059), /* PORT89CR */ + + PORTCR(90, 0xe605105a), /* PORT90CR */ + PORTCR(91, 0xe605105b), /* PORT91CR */ + PORTCR(92, 0xe605105c), /* PORT92CR */ + PORTCR(93, 0xe605105d), /* PORT93CR */ + PORTCR(94, 0xe605105e), /* PORT94CR */ + PORTCR(95, 0xe605105f), /* PORT95CR */ + PORTCR(96, 0xe6052060), /* PORT96CR */ + PORTCR(97, 0xe6052061), /* PORT97CR */ + PORTCR(98, 0xe6052062), /* PORT98CR */ + PORTCR(99, 0xe6052063), /* PORT99CR */ + + PORTCR(100, 0xe6052064), /* PORT100CR */ + PORTCR(101, 0xe6052065), /* PORT101CR */ + PORTCR(102, 0xe6052066), /* PORT102CR */ + PORTCR(103, 0xe6052067), /* PORT103CR */ + PORTCR(104, 0xe6052068), /* PORT104CR */ + PORTCR(105, 0xe6052069), /* PORT105CR */ + PORTCR(106, 0xe605206a), /* PORT106CR */ + PORTCR(107, 0xe605206b), /* PORT107CR */ + PORTCR(108, 0xe605206c), /* PORT108CR */ + PORTCR(109, 0xe605206d), /* PORT109CR */ + + PORTCR(110, 0xe605206e), /* PORT110CR */ + PORTCR(111, 0xe605206f), /* PORT111CR */ + PORTCR(112, 0xe6052070), /* PORT112CR */ + PORTCR(113, 0xe6052071), /* PORT113CR */ + PORTCR(114, 0xe6052072), /* PORT114CR */ + PORTCR(115, 0xe6052073), /* PORT115CR */ + PORTCR(116, 0xe6052074), /* PORT116CR */ + PORTCR(117, 0xe6052075), /* PORT117CR */ + PORTCR(118, 0xe6052076), /* PORT118CR */ + + PORTCR(128, 0xe6052080), /* PORT128CR */ + PORTCR(129, 0xe6052081), /* PORT129CR */ + + PORTCR(130, 0xe6052082), /* PORT130CR */ + PORTCR(131, 0xe6052083), /* PORT131CR */ + PORTCR(132, 0xe6052084), /* PORT132CR */ + PORTCR(133, 0xe6052085), /* PORT133CR */ + PORTCR(134, 0xe6052086), /* PORT134CR */ + PORTCR(135, 0xe6052087), /* PORT135CR */ + PORTCR(136, 0xe6052088), /* PORT136CR */ + PORTCR(137, 0xe6052089), /* PORT137CR */ + PORTCR(138, 0xe605208a), /* PORT138CR */ + PORTCR(139, 0xe605208b), /* PORT139CR */ + + PORTCR(140, 0xe605208c), /* PORT140CR */ + PORTCR(141, 0xe605208d), /* PORT141CR */ + PORTCR(142, 0xe605208e), /* PORT142CR */ + PORTCR(143, 0xe605208f), /* PORT143CR */ + PORTCR(144, 0xe6052090), /* PORT144CR */ + PORTCR(145, 0xe6052091), /* PORT145CR */ + PORTCR(146, 0xe6052092), /* PORT146CR */ + PORTCR(147, 0xe6052093), /* PORT147CR */ + PORTCR(148, 0xe6052094), /* PORT148CR */ + PORTCR(149, 0xe6052095), /* PORT149CR */ + + PORTCR(150, 0xe6052096), /* PORT150CR */ + PORTCR(151, 0xe6052097), /* PORT151CR */ + PORTCR(152, 0xe6052098), /* PORT152CR */ + PORTCR(153, 0xe6052099), /* PORT153CR */ + PORTCR(154, 0xe605209a), /* PORT154CR */ + PORTCR(155, 0xe605209b), /* PORT155CR */ + PORTCR(156, 0xe605209c), /* PORT156CR */ + PORTCR(157, 0xe605209d), /* PORT157CR */ + PORTCR(158, 0xe605209e), /* PORT158CR */ + PORTCR(159, 0xe605209f), /* PORT159CR */ + + PORTCR(160, 0xe60520a0), /* PORT160CR */ + PORTCR(161, 0xe60520a1), /* PORT161CR */ + PORTCR(162, 0xe60520a2), /* PORT162CR */ + PORTCR(163, 0xe60520a3), /* PORT163CR */ + PORTCR(164, 0xe60520a4), /* PORT164CR */ + + PORTCR(192, 0xe60520c0), /* PORT192CR */ + PORTCR(193, 0xe60520c1), /* PORT193CR */ + PORTCR(194, 0xe60520c2), /* PORT194CR */ + PORTCR(195, 0xe60520c3), /* PORT195CR */ + PORTCR(196, 0xe60520c4), /* PORT196CR */ + PORTCR(197, 0xe60520c5), /* PORT197CR */ + PORTCR(198, 0xe60520c6), /* PORT198CR */ + PORTCR(199, 0xe60520c7), /* PORT199CR */ + + PORTCR(200, 0xe60520c8), /* PORT200CR */ + PORTCR(201, 0xe60520c9), /* PORT201CR */ + PORTCR(202, 0xe60520ca), /* PORT202CR */ + PORTCR(203, 0xe60520cb), /* PORT203CR */ + PORTCR(204, 0xe60520cc), /* PORT204CR */ + PORTCR(205, 0xe60520cd), /* PORT205CR */ + PORTCR(206, 0xe60520ce), /* PORT206CR */ + PORTCR(207, 0xe60520cf), /* PORT207CR */ + PORTCR(208, 0xe60520d0), /* PORT208CR */ + PORTCR(209, 0xe60520d1), /* PORT209CR */ + + PORTCR(210, 0xe60520d2), /* PORT210CR */ + PORTCR(211, 0xe60520d3), /* PORT211CR */ + PORTCR(212, 0xe60520d4), /* PORT212CR */ + PORTCR(213, 0xe60520d5), /* PORT213CR */ + PORTCR(214, 0xe60520d6), /* PORT214CR */ + PORTCR(215, 0xe60520d7), /* PORT215CR */ + PORTCR(216, 0xe60520d8), /* PORT216CR */ + PORTCR(217, 0xe60520d9), /* PORT217CR */ + PORTCR(218, 0xe60520da), /* PORT218CR */ + PORTCR(219, 0xe60520db), /* PORT219CR */ + + PORTCR(220, 0xe60520dc), /* PORT220CR */ + PORTCR(221, 0xe60520dd), /* PORT221CR */ + PORTCR(222, 0xe60520de), /* PORT222CR */ + PORTCR(223, 0xe60520df), /* PORT223CR */ + PORTCR(224, 0xe60530e0), /* PORT224CR */ + PORTCR(225, 0xe60530e1), /* PORT225CR */ + PORTCR(226, 0xe60530e2), /* PORT226CR */ + PORTCR(227, 0xe60530e3), /* PORT227CR */ + PORTCR(228, 0xe60530e4), /* PORT228CR */ + PORTCR(229, 0xe60530e5), /* PORT229CR */ + + PORTCR(230, 0xe60530e6), /* PORT230CR */ + PORTCR(231, 0xe60530e7), /* PORT231CR */ + PORTCR(232, 0xe60530e8), /* PORT232CR */ + PORTCR(233, 0xe60530e9), /* PORT233CR */ + PORTCR(234, 0xe60530ea), /* PORT234CR */ + PORTCR(235, 0xe60530eb), /* PORT235CR */ + PORTCR(236, 0xe60530ec), /* PORT236CR */ + PORTCR(237, 0xe60530ed), /* PORT237CR */ + PORTCR(238, 0xe60530ee), /* PORT238CR */ + PORTCR(239, 0xe60530ef), /* PORT239CR */ + + PORTCR(240, 0xe60530f0), /* PORT240CR */ + PORTCR(241, 0xe60530f1), /* PORT241CR */ + PORTCR(242, 0xe60530f2), /* PORT242CR */ + PORTCR(243, 0xe60530f3), /* PORT243CR */ + PORTCR(244, 0xe60530f4), /* PORT244CR */ + PORTCR(245, 0xe60530f5), /* PORT245CR */ + PORTCR(246, 0xe60530f6), /* PORT246CR */ + PORTCR(247, 0xe60530f7), /* PORT247CR */ + PORTCR(248, 0xe60530f8), /* PORT248CR */ + PORTCR(249, 0xe60530f9), /* PORT249CR */ + + PORTCR(250, 0xe60530fa), /* PORT250CR */ + PORTCR(251, 0xe60530fb), /* PORT251CR */ + PORTCR(252, 0xe60530fc), /* PORT252CR */ + PORTCR(253, 0xe60530fd), /* PORT253CR */ + PORTCR(254, 0xe60530fe), /* PORT254CR */ + PORTCR(255, 0xe60530ff), /* PORT255CR */ + PORTCR(256, 0xe6053100), /* PORT256CR */ + PORTCR(257, 0xe6053101), /* PORT257CR */ + PORTCR(258, 0xe6053102), /* PORT258CR */ + PORTCR(259, 0xe6053103), /* PORT259CR */ + + PORTCR(260, 0xe6053104), /* PORT260CR */ + PORTCR(261, 0xe6053105), /* PORT261CR */ + PORTCR(262, 0xe6053106), /* PORT262CR */ + PORTCR(263, 0xe6053107), /* PORT263CR */ + PORTCR(264, 0xe6053108), /* PORT264CR */ + PORTCR(265, 0xe6053109), /* PORT265CR */ + PORTCR(266, 0xe605310a), /* PORT266CR */ + PORTCR(267, 0xe605310b), /* PORT267CR */ + PORTCR(268, 0xe605310c), /* PORT268CR */ + PORTCR(269, 0xe605310d), /* PORT269CR */ + + PORTCR(270, 0xe605310e), /* PORT270CR */ + PORTCR(271, 0xe605310f), /* PORT271CR */ + PORTCR(272, 0xe6053110), /* PORT272CR */ + PORTCR(273, 0xe6053111), /* PORT273CR */ + PORTCR(274, 0xe6053112), /* PORT274CR */ + PORTCR(275, 0xe6053113), /* PORT275CR */ + PORTCR(276, 0xe6053114), /* PORT276CR */ + PORTCR(277, 0xe6053115), /* PORT277CR */ + PORTCR(278, 0xe6053116), /* PORT278CR */ + PORTCR(279, 0xe6053117), /* PORT279CR */ + + PORTCR(280, 0xe6053118), /* PORT280CR */ + PORTCR(281, 0xe6053119), /* PORT281CR */ + PORTCR(282, 0xe605311a), /* PORT282CR */ + + PORTCR(288, 0xe6052120), /* PORT288CR */ + PORTCR(289, 0xe6052121), /* PORT289CR */ + + PORTCR(290, 0xe6052122), /* PORT290CR */ + PORTCR(291, 0xe6052123), /* PORT291CR */ + PORTCR(292, 0xe6052124), /* PORT292CR */ + PORTCR(293, 0xe6052125), /* PORT293CR */ + PORTCR(294, 0xe6052126), /* PORT294CR */ + PORTCR(295, 0xe6052127), /* PORT295CR */ + PORTCR(296, 0xe6052128), /* PORT296CR */ + PORTCR(297, 0xe6052129), /* PORT297CR */ + PORTCR(298, 0xe605212a), /* PORT298CR */ + PORTCR(299, 0xe605212b), /* PORT299CR */ + + PORTCR(300, 0xe605212c), /* PORT300CR */ + PORTCR(301, 0xe605212d), /* PORT301CR */ + PORTCR(302, 0xe605212e), /* PORT302CR */ + PORTCR(303, 0xe605212f), /* PORT303CR */ + PORTCR(304, 0xe6052130), /* PORT304CR */ + PORTCR(305, 0xe6052131), /* PORT305CR */ + PORTCR(306, 0xe6052132), /* PORT306CR */ + PORTCR(307, 0xe6052133), /* PORT307CR */ + PORTCR(308, 0xe6052134), /* PORT308CR */ + PORTCR(309, 0xe6052135), /* PORT309CR */ + + { PINMUX_CFG_REG("MSEL2CR", 0xe605801c, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + MSEL2CR_MSEL19_0, MSEL2CR_MSEL19_1, + MSEL2CR_MSEL18_0, MSEL2CR_MSEL18_1, + MSEL2CR_MSEL17_0, MSEL2CR_MSEL17_1, + MSEL2CR_MSEL16_0, MSEL2CR_MSEL16_1, + 0, 0, + MSEL2CR_MSEL14_0, MSEL2CR_MSEL14_1, + MSEL2CR_MSEL13_0, MSEL2CR_MSEL13_1, + MSEL2CR_MSEL12_0, MSEL2CR_MSEL12_1, + MSEL2CR_MSEL11_0, MSEL2CR_MSEL11_1, + MSEL2CR_MSEL10_0, MSEL2CR_MSEL10_1, + MSEL2CR_MSEL9_0, MSEL2CR_MSEL9_1, + MSEL2CR_MSEL8_0, MSEL2CR_MSEL8_1, + MSEL2CR_MSEL7_0, MSEL2CR_MSEL7_1, + MSEL2CR_MSEL6_0, MSEL2CR_MSEL6_1, + MSEL2CR_MSEL5_0, MSEL2CR_MSEL5_1, + MSEL2CR_MSEL4_0, MSEL2CR_MSEL4_1, + MSEL2CR_MSEL3_0, MSEL2CR_MSEL3_1, + MSEL2CR_MSEL2_0, MSEL2CR_MSEL2_1, + MSEL2CR_MSEL1_0, MSEL2CR_MSEL1_1, + MSEL2CR_MSEL0_0, MSEL2CR_MSEL0_1, + } + }, + { PINMUX_CFG_REG("MSEL3CR", 0xe6058020, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + MSEL3CR_MSEL28_0, MSEL3CR_MSEL28_1, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + MSEL3CR_MSEL15_0, MSEL3CR_MSEL15_1, + 0, 0, + 0, 0, + 0, 0, + MSEL3CR_MSEL11_0, MSEL3CR_MSEL11_1, + 0, 0, + MSEL3CR_MSEL9_0, MSEL3CR_MSEL9_1, + 0, 0, + 0, 0, + MSEL3CR_MSEL6_0, MSEL3CR_MSEL6_1, + 0, 0, + 0, 0, + 0, 0, + MSEL3CR_MSEL2_0, MSEL3CR_MSEL2_1, + 0, 0, + 0, 0, + } + }, + { PINMUX_CFG_REG("MSEL4CR", 0xe6058024, 32, 1) { + 0, 0, + 0, 0, + MSEL4CR_MSEL29_0, MSEL4CR_MSEL29_1, + 0, 0, + MSEL4CR_MSEL27_0, MSEL4CR_MSEL27_1, + MSEL4CR_MSEL26_0, MSEL4CR_MSEL26_1, + 0, 0, + 0, 0, + 0, 0, + MSEL4CR_MSEL22_0, MSEL4CR_MSEL22_1, + MSEL4CR_MSEL21_0, MSEL4CR_MSEL21_1, + MSEL4CR_MSEL20_0, MSEL4CR_MSEL20_1, + MSEL4CR_MSEL19_0, MSEL4CR_MSEL19_1, + 0, 0, + 0, 0, + 0, 0, + MSEL4CR_MSEL15_0, MSEL4CR_MSEL15_1, + 0, 0, + MSEL4CR_MSEL13_0, MSEL4CR_MSEL13_1, + MSEL4CR_MSEL12_0, MSEL4CR_MSEL12_1, + MSEL4CR_MSEL11_0, MSEL4CR_MSEL11_1, + MSEL4CR_MSEL10_0, MSEL4CR_MSEL10_1, + MSEL4CR_MSEL9_0, MSEL4CR_MSEL9_1, + MSEL4CR_MSEL8_0, MSEL4CR_MSEL8_1, + MSEL4CR_MSEL7_0, MSEL4CR_MSEL7_1, + 0, 0, + 0, 0, + MSEL4CR_MSEL4_0, MSEL4CR_MSEL4_1, + 0, 0, + 0, 0, + MSEL4CR_MSEL1_0, MSEL4CR_MSEL1_1, + 0, 0, + } + }, + { }, +}; + +static struct pinmux_data_reg pinmux_data_regs[] = { + { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32) { + PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA, + PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA, + PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA, + PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA, + PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA, + PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA, + PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA, + PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA } + }, + { PINMUX_DATA_REG("PORTD063_032DR", 0xe6055000, 32) { + PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA, + PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA, + PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA, + PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA, + PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA, + PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA, + PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA, + PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA } + }, + { PINMUX_DATA_REG("PORTD095_064DR", 0xe6055004, 32) { + PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA, + PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA, + PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA, + PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA, + PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA, + PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA, + PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA, + PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA } + }, + { PINMUX_DATA_REG("PORTR127_096DR", 0xe6056000, 32) { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, PORT118_DATA, PORT117_DATA, PORT116_DATA, + PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA, + PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA, + PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA, + PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA, + PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA } + }, + { PINMUX_DATA_REG("PORTR159_128DR", 0xe6056004, 32) { + PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA, + PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA, + PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA, + PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA, + PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA, + PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA, + PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA, + PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA } + }, + { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056008, 32) { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, PORT164_DATA, + PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA } + }, + { PINMUX_DATA_REG("PORTR223_192DR", 0xe605600C, 32) { + PORT223_DATA, PORT222_DATA, PORT221_DATA, PORT220_DATA, + PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA, + PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA, + PORT211_DATA, PORT210_DATA, PORT209_DATA, PORT208_DATA, + PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA, + PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA, + PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA, + PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA } + }, + { PINMUX_DATA_REG("PORTU255_224DR", 0xe6057000, 32) { + PORT255_DATA, PORT254_DATA, PORT253_DATA, PORT252_DATA, + PORT251_DATA, PORT250_DATA, PORT249_DATA, PORT248_DATA, + PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA, + PORT243_DATA, PORT242_DATA, PORT241_DATA, PORT240_DATA, + PORT239_DATA, PORT238_DATA, PORT237_DATA, PORT236_DATA, + PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA, + PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA, + PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA } + }, + { PINMUX_DATA_REG("PORTU287_256DR", 0xe6057004, 32) { + 0, 0, 0, 0, + 0, PORT282_DATA, PORT281_DATA, PORT280_DATA, + PORT279_DATA, PORT278_DATA, PORT277_DATA, PORT276_DATA, + PORT275_DATA, PORT274_DATA, PORT273_DATA, PORT272_DATA, + PORT271_DATA, PORT270_DATA, PORT269_DATA, PORT268_DATA, + PORT267_DATA, PORT266_DATA, PORT265_DATA, PORT264_DATA, + PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA, + PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA } + }, + { PINMUX_DATA_REG("PORTR319_288DR", 0xe6056010, 32) { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, PORT309_DATA, PORT308_DATA, + PORT307_DATA, PORT306_DATA, PORT305_DATA, PORT304_DATA, + PORT303_DATA, PORT302_DATA, PORT301_DATA, PORT300_DATA, + PORT299_DATA, PORT298_DATA, PORT297_DATA, PORT296_DATA, + PORT295_DATA, PORT294_DATA, PORT293_DATA, PORT292_DATA, + PORT291_DATA, PORT290_DATA, PORT289_DATA, PORT288_DATA } + }, + { }, +}; + +#if 0 +/* IRQ pins through INTCS with IRQ0->15 from 0x200 and IRQ16-31 from 0x3200 */ +#define EXT_IRQ16L(n) intcs_evt2irq(0x200 + ((n) << 5)) +#define EXT_IRQ16H(n) intcs_evt2irq(0x3200 + ((n - 16) << 5)) +#else +#define EXT_IRQ16L(n) (n) +#define EXT_IRQ16H(n) (n) +#endif + +static struct pinmux_irq pinmux_irqs[] = { + PINMUX_IRQ(EXT_IRQ16H(19), PORT9_FN0), + PINMUX_IRQ(EXT_IRQ16L(1), PORT10_FN0), + PINMUX_IRQ(EXT_IRQ16L(0), PORT11_FN0), + PINMUX_IRQ(EXT_IRQ16H(18), PORT13_FN0), + PINMUX_IRQ(EXT_IRQ16H(20), PORT14_FN0), + PINMUX_IRQ(EXT_IRQ16H(21), PORT15_FN0), + PINMUX_IRQ(EXT_IRQ16H(31), PORT26_FN0), + PINMUX_IRQ(EXT_IRQ16H(30), PORT27_FN0), + PINMUX_IRQ(EXT_IRQ16H(29), PORT28_FN0), + PINMUX_IRQ(EXT_IRQ16H(22), PORT40_FN0), + PINMUX_IRQ(EXT_IRQ16H(23), PORT53_FN0), + PINMUX_IRQ(EXT_IRQ16L(10), PORT54_FN0), + PINMUX_IRQ(EXT_IRQ16L(9), PORT56_FN0), + PINMUX_IRQ(EXT_IRQ16H(26), PORT115_FN0), + PINMUX_IRQ(EXT_IRQ16H(27), PORT116_FN0), + PINMUX_IRQ(EXT_IRQ16H(28), PORT117_FN0), + PINMUX_IRQ(EXT_IRQ16H(24), PORT118_FN0), + PINMUX_IRQ(EXT_IRQ16L(6), PORT147_FN0), + PINMUX_IRQ(EXT_IRQ16L(2), PORT149_FN0), + PINMUX_IRQ(EXT_IRQ16L(7), PORT150_FN0), + PINMUX_IRQ(EXT_IRQ16L(12), PORT156_FN0), + PINMUX_IRQ(EXT_IRQ16L(4), PORT159_FN0), + PINMUX_IRQ(EXT_IRQ16H(25), PORT164_FN0), + PINMUX_IRQ(EXT_IRQ16L(8), PORT223_FN0), + PINMUX_IRQ(EXT_IRQ16L(3), PORT224_FN0), + PINMUX_IRQ(EXT_IRQ16L(5), PORT227_FN0), + PINMUX_IRQ(EXT_IRQ16H(17), PORT234_FN0), + PINMUX_IRQ(EXT_IRQ16L(11), PORT238_FN0), + PINMUX_IRQ(EXT_IRQ16L(13), PORT239_FN0), + PINMUX_IRQ(EXT_IRQ16H(16), PORT249_FN0), + PINMUX_IRQ(EXT_IRQ16L(14), PORT251_FN0), + PINMUX_IRQ(EXT_IRQ16L(9), PORT308_FN0), +}; + +static struct pinmux_info sh73a0_pinmux_info = { + .name = "sh73a0_pfc", + .reserved_id = PINMUX_RESERVED, + .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, + .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, + .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, + .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END }, + .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, + .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + + .first_gpio = GPIO_PORT0, + .last_gpio = GPIO_FN_FSIAISLD_PU, + + .gpios = pinmux_gpios, + .cfg_regs = pinmux_config_regs, + .data_regs = pinmux_data_regs, + + .gpio_data = pinmux_data, + .gpio_data_size = ARRAY_SIZE(pinmux_data), + + .gpio_irq = pinmux_irqs, + .gpio_irq_size = ARRAY_SIZE(pinmux_irqs), +}; + +void sh73a0_pinmux_init(void) +{ + register_pinmux(&sh73a0_pinmux_info); +} diff --git a/arch/arm/cpu/armv7/rmobile/timer.c b/arch/arm/cpu/armv7/rmobile/timer.c new file mode 100644 index 0000000000..37522dcd84 --- /dev/null +++ b/arch/arm/cpu/armv7/rmobile/timer.c @@ -0,0 +1,97 @@ +/* + * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> + * (C) Copyright 2012 Renesas Solutions Corp. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch-armv7/globaltimer.h> +#include <asm/arch/rmobile.h> + +static struct globaltimer *global_timer = \ + (struct globaltimer *)GLOBAL_TIMER_BASE_ADDR; + +#define CLK2MHZ(clk) (clk / 1000 / 1000) +static u64 get_cpu_global_timer(void) +{ + u32 low, high; + u64 timer; + + u32 old = readl(&global_timer->cnt_h); + while (1) { + low = readl(&global_timer->cnt_l); + high = readl(&global_timer->cnt_h); + if (old == high) + break; + else + old = high; + } + + timer = high; + return (u64)((timer << 32) | low); +} + +static u64 get_time_us(void) +{ + u64 timer = get_cpu_global_timer(); + + timer = ((timer << 2) + (CLK2MHZ(CONFIG_SYS_CPU_CLK) >> 1)); + timer /= (u64)CLK2MHZ(CONFIG_SYS_CPU_CLK); + return timer; +} + +static ulong get_time_ms(void) +{ + return (ulong)(get_time_us() / 1000); +} + +int timer_init(void) +{ + writel(0x01, &global_timer->ctl); + return 0; +} + +void __udelay(unsigned long usec) +{ + u64 start, current; + u64 wait; + + start = get_cpu_global_timer(); + wait = (u64)((usec * CLK2MHZ(CONFIG_SYS_CPU_CLK)) >> 2); + do { + current = get_cpu_global_timer(); + } while ((current - start) < wait); +} + +ulong get_timer(ulong base) +{ + return get_time_ms() - base; +} + +unsigned long long get_ticks(void) +{ + return get_cpu_global_timer(); +} + +ulong get_tbclk(void) +{ + return (ulong)(CONFIG_SYS_CPU_CLK >> 2); +} diff --git a/arch/arm/cpu/armv7/socfpga/Makefile b/arch/arm/cpu/armv7/socfpga/Makefile new file mode 100644 index 0000000000..376a4bddee --- /dev/null +++ b/arch/arm/cpu/armv7/socfpga/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# Copyright (C) 2012 Altera Corporation <www.altera.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).o + +SOBJS := lowlevel_init.o +COBJS-y := misc.o timer.o +COBJS-$(CONFIG_SPL_BUILD) += spl.o + +COBJS := $(COBJS-y) +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/arch/arm/cpu/armv7/socfpga/config.mk b/arch/arm/cpu/armv7/socfpga/config.mk new file mode 100644 index 0000000000..b72ed1e40d --- /dev/null +++ b/arch/arm/cpu/armv7/socfpga/config.mk @@ -0,0 +1,16 @@ +# +# Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed "as is" WITHOUT ANY WARRANTY of any +# kind, whether express or implied; without even the implied warranty +# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +ifndef CONFIG_SPL_BUILD +ALL-y += $(obj)u-boot.img +endif diff --git a/arch/arm/cpu/armv7/socfpga/lowlevel_init.S b/arch/arm/cpu/armv7/socfpga/lowlevel_init.S new file mode 100644 index 0000000000..001b37d42d --- /dev/null +++ b/arch/arm/cpu/armv7/socfpga/lowlevel_init.S @@ -0,0 +1,77 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <config.h> +#include <version.h> + +/* Save the parameter pass in by previous boot loader */ +.global save_boot_params +save_boot_params: + /* save the parameter here */ + + /* + * Setup stack for exception, which is located + * at the end of on-chip RAM. We don't expect exception prior to + * relocation and if that happens, we won't worry -- it will overide + * global data region as the code will goto reset. After relocation, + * this region won't be used by other part of program. + * Hence it is safe. + */ + ldr r0, =(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE) + ldr r1, =IRQ_STACK_START_IN + str r0, [r1] + + bx lr + + +/* Set up the platform, once the cpu has been initialized */ +.globl lowlevel_init +lowlevel_init: + + /* Remap */ +#ifdef CONFIG_SPL_BUILD + /* + * SPL : configure the remap (L3 NIC-301 GPV) + * so the on-chip RAM at lower memory instead ROM. + */ + ldr r0, =SOCFPGA_L3REGS_ADDRESS + mov r1, #0x19 + str r1, [r0] +#else + /* + * U-Boot : configure the remap (L3 NIC-301 GPV) + * so the SDRAM at lower memory instead on-chip RAM. + */ + ldr r0, =SOCFPGA_L3REGS_ADDRESS + mov r1, #0x2 + str r1, [r0] + + /* Private components security */ + + /* + * U-Boot : configure private timer, global timer and cpu + * component access as non secure for kernel stage (as required + * by kernel) + */ + mrc p15,4,r0,c15,c0,0 + add r1, r0, #0x54 + ldr r2, [r1] + orr r2, r2, #0xff + orr r2, r2, #0xf00 + str r2, [r1] +#endif /* #ifdef CONFIG_SPL_BUILD */ + mov pc, lr diff --git a/arch/arm/cpu/armv7/socfpga/misc.c b/arch/arm/cpu/armv7/socfpga/misc.c new file mode 100644 index 0000000000..fa16424b6f --- /dev/null +++ b/arch/arm/cpu/armv7/socfpga/misc.c @@ -0,0 +1,54 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/reset_manager.h> + +DECLARE_GLOBAL_DATA_PTR; + +static const struct socfpga_reset_manager *reset_manager_base = + (void *)SOCFPGA_RSTMGR_ADDRESS; + +/* + * Write the reset manager register to cause reset + */ +void reset_cpu(ulong addr) +{ + /* request a warm reset */ + writel(RSTMGR_CTRL_SWWARMRSTREQ_LSB, &reset_manager_base->ctrl); + /* + * infinite loop here as watchdog will trigger and reset + * the processor + */ + while (1) + ; +} + +/* + * Release peripherals from reset based on handoff + */ +void reset_deassert_peripherals_handoff(void) +{ + writel(0, &reset_manager_base->per_mod_reset); +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); + return 0; +} diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c new file mode 100644 index 0000000000..944238bad1 --- /dev/null +++ b/arch/arm/cpu/armv7/socfpga/spl.c @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/u-boot.h> +#include <asm/utils.h> +#include <version.h> +#include <image.h> +#include <malloc.h> +#include <asm/arch/reset_manager.h> +#include <spl.h> + +DECLARE_GLOBAL_DATA_PTR; + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_RAM; +} + +/* + * Board initialization after bss clearance + */ +void spl_board_init(void) +{ + /* init timer for enabling delay function */ + timer_init(); + + /* de-assert reset for peripherals and bridges based on handoff */ + reset_deassert_peripherals_handoff(); + + /* enable console uart printing */ + preloader_console_init(); +} diff --git a/arch/arm/cpu/armv7/socfpga/timer.c b/arch/arm/cpu/armv7/socfpga/timer.c new file mode 100644 index 0000000000..321e9b4181 --- /dev/null +++ b/arch/arm/cpu/armv7/socfpga/timer.c @@ -0,0 +1,104 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/timer.h> + +DECLARE_GLOBAL_DATA_PTR; + +static const struct socfpga_timer *timer_base = (void *)CONFIG_SYS_TIMERBASE; + +/* + * Timer initialization + */ +int timer_init(void) +{ + writel(TIMER_LOAD_VAL, &timer_base->load_val); + writel(TIMER_LOAD_VAL, &timer_base->curr_val); + writel(readl(&timer_base->ctrl) | 0x3, &timer_base->ctrl); + return 0; +} + +static u32 read_timer(void) +{ + return readl(&timer_base->curr_val); +} + +/* + * Delay x useconds + */ +void __udelay(unsigned long usec) +{ + unsigned long now, last; + /* + * get the tmo value based on timer clock speed + * tmo = delay required / period of timer clock + */ + long tmo = usec * CONFIG_TIMER_CLOCK_KHZ / 1000; + + last = read_timer(); + while (tmo > 0) { + now = read_timer(); + if (last >= now) + /* normal mode (non roll) */ + tmo -= last - now; + else + /* we have overflow of the count down timer */ + tmo -= TIMER_LOAD_VAL - last + now; + last = now; + } +} + +/* + * Get the timer value + */ +ulong get_timer(ulong base) +{ + return get_timer_masked() - base; +} + +/* + * Timer : get the time difference + * Unit of tick is based on the CONFIG_SYS_HZ + */ +ulong get_timer_masked(void) +{ + /* current tick value */ + ulong now = read_timer() / (CONFIG_TIMER_CLOCK_KHZ/CONFIG_SYS_HZ); + if (gd->lastinc >= now) { + /* normal mode (non roll) */ + /* move stamp forward with absolute diff ticks */ + gd->tbl += gd->lastinc - now; + } else { + /* we have overflow of the count down timer */ + gd->tbl += TIMER_LOAD_VAL - gd->lastinc + now; + } + gd->lastinc = now; + return gd->tbl; +} + +/* + * Reset the timer + */ +void reset_timer(void) +{ + /* capture current decrementer value time */ + gd->lastinc = read_timer() / (CONFIG_TIMER_CLOCK_KHZ/CONFIG_SYS_HZ); + /* start "advancing" time stamp from 0 */ + gd->tbl = 0; +} diff --git a/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds b/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds new file mode 100644 index 0000000000..7cd409cca2 --- /dev/null +++ b/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds @@ -0,0 +1,60 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +MEMORY { .sdram : ORIGIN = (0), LENGTH = (0xffffffff) } + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + arch/arm/cpu/armv7/start.o (.text) + *(.text*) + } >.sdram + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } >.sdram + + . = ALIGN(4); + .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sdram + + . = ALIGN(4); + __image_copy_end = .; + _end = .; + + .bss : { + . = ALIGN(4); + __bss_start = .; + *(.bss*) + . = ALIGN(4); + __bss_end__ = .; + } >.sdram + + . = ALIGN(8); + __malloc_start = .; + . = . + CONFIG_SPL_MALLOC_SIZE; + __malloc_end = .; + + . = . + CONFIG_SPL_STACK_SIZE; + . = ALIGN(8); + __stack_start = .; +} diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index f26308df16..7df97c5a3a 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -360,10 +360,7 @@ ENTRY(cpu_init_crit) * basic memory. Go here to bump up clock rate and handle * wake up conditions. */ - mov ip, lr @ persevere link reg across call - bl lowlevel_init @ go setup pll,mux,memory - mov lr, ip @ restore link - mov pc, lr @ back to my caller + b lowlevel_init @ go setup pll,mux,memory ENDPROC(cpu_init_crit) #endif diff --git a/arch/arm/cpu/armv7/zynq/Makefile b/arch/arm/cpu/armv7/zynq/Makefile new file mode 100644 index 0000000000..499ace4a62 --- /dev/null +++ b/arch/arm/cpu/armv7/zynq/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2008 +# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).o + +COBJS-y := timer.o +COBJS-y += cpu.o + +COBJS := $(COBJS-y) + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/arch/arm/cpu/armv7/zynq/cpu.c b/arch/arm/cpu/armv7/zynq/cpu.c new file mode 100644 index 0000000000..ab615cc7d4 --- /dev/null +++ b/arch/arm/cpu/armv7/zynq/cpu.c @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2012 Michal Simek <monstr@monstr.eu> + * Copyright (C) 2012 Xilinx, Inc. All rights reserved. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> + +inline void lowlevel_init(void) {} + +void reset_cpu(ulong addr) +{ + while (1) + ; +} diff --git a/arch/arm/cpu/armv7/zynq/timer.c b/arch/arm/cpu/armv7/zynq/timer.c new file mode 100644 index 0000000000..323e7b5a49 --- /dev/null +++ b/arch/arm/cpu/armv7/zynq/timer.c @@ -0,0 +1,150 @@ +/* + * Copyright (C) 2012 Michal Simek <monstr@monstr.eu> + * Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved. + * + * (C) Copyright 2008 + * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de> + * + * (C) Copyright 2004 + * Philippe Robin, ARM Ltd. <philippe.robin@arm.com> + * + * (C) Copyright 2002-2004 + * Gary Jennejohn, DENX Software Engineering, <gj@denx.de> + * + * (C) Copyright 2003 + * Texas Instruments <www.ti.com> + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger@sysgo.de> + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Alex Zuepke <azu@sysgo.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <div64.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +struct scu_timer { + u32 load; /* Timer Load Register */ + u32 counter; /* Timer Counter Register */ + u32 control; /* Timer Control Register */ +}; + +static struct scu_timer *timer_base = + (struct scu_timer *) CONFIG_SCUTIMER_BASEADDR; + +#define SCUTIMER_CONTROL_PRESCALER_MASK 0x0000FF00 /* Prescaler */ +#define SCUTIMER_CONTROL_PRESCALER_SHIFT 8 +#define SCUTIMER_CONTROL_AUTO_RELOAD_MASK 0x00000002 /* Auto-reload */ +#define SCUTIMER_CONTROL_ENABLE_MASK 0x00000001 /* Timer enable */ + +#define TIMER_LOAD_VAL 0xFFFFFFFF +#define TIMER_PRESCALE 255 +#define TIMER_TICK_HZ (CONFIG_CPU_FREQ_HZ / 2 / TIMER_PRESCALE) + +int timer_init(void) +{ + const u32 emask = SCUTIMER_CONTROL_AUTO_RELOAD_MASK | + (TIMER_PRESCALE << SCUTIMER_CONTROL_PRESCALER_SHIFT) | + SCUTIMER_CONTROL_ENABLE_MASK; + + /* Load the timer counter register */ + writel(0xFFFFFFFF, &timer_base->counter); + + /* + * Start the A9Timer device + * Enable Auto reload mode, Clear prescaler control bits + * Set prescaler value, Enable the decrementer + */ + clrsetbits_le32(&timer_base->control, SCUTIMER_CONTROL_PRESCALER_MASK, + emask); + + /* Reset time */ + gd->lastinc = readl(&timer_base->counter) / + (TIMER_TICK_HZ / CONFIG_SYS_HZ); + gd->tbl = 0; + + return 0; +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value. + */ +ulong get_timer_masked(void) +{ + ulong now; + + now = readl(&timer_base->counter) / (TIMER_TICK_HZ / CONFIG_SYS_HZ); + + if (gd->lastinc >= now) { + /* Normal mode */ + gd->tbl += gd->lastinc - now; + } else { + /* We have an overflow ... */ + gd->tbl += gd->lastinc + TIMER_LOAD_VAL - now; + } + gd->lastinc = now; + + return gd->tbl; +} + +void __udelay(unsigned long usec) +{ + unsigned long long tmp; + ulong tmo; + + tmo = usec / (1000000 / CONFIG_SYS_HZ); + tmp = get_ticks() + tmo; /* Get current timestamp */ + + while (get_ticks() < tmp) { /* Loop till event */ + /* NOP */; + } +} + +/* Timer without interrupts */ +ulong get_timer(ulong base) +{ + return get_timer_masked() - base; +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk(void) +{ + return CONFIG_SYS_HZ; +} diff --git a/arch/arm/cpu/ixp/start.S b/arch/arm/cpu/ixp/start.S index 59c359a353..c12f1a7db8 100644 --- a/arch/arm/cpu/ixp/start.S +++ b/arch/arm/cpu/ixp/start.S @@ -273,6 +273,7 @@ stack_setup: adr r0, _start cmp r0, r6 + moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ beq clear_bss /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ ldr r3, _bss_start_ofs diff --git a/arch/arm/cpu/lh7a40x/start.S b/arch/arm/cpu/lh7a40x/start.S index bd68cd47cf..33b9269c70 100644 --- a/arch/arm/cpu/lh7a40x/start.S +++ b/arch/arm/cpu/lh7a40x/start.S @@ -184,6 +184,7 @@ stack_setup: adr r0, _start cmp r0, r6 + moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ beq clear_bss /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ ldr r3, _bss_start_ofs diff --git a/arch/arm/cpu/pxa/start.S b/arch/arm/cpu/pxa/start.S index 33c73f67b5..536cf5c974 100644 --- a/arch/arm/cpu/pxa/start.S +++ b/arch/arm/cpu/pxa/start.S @@ -197,6 +197,7 @@ stack_setup: adr r0, _start cmp r0, r6 + moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ beq clear_bss /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ ldr r3, _bss_start_ofs diff --git a/arch/arm/cpu/s3c44b0/start.S b/arch/arm/cpu/s3c44b0/start.S index 8daf26c4f0..323b923f13 100644 --- a/arch/arm/cpu/s3c44b0/start.S +++ b/arch/arm/cpu/s3c44b0/start.S @@ -156,6 +156,7 @@ stack_setup: adr r0, _start cmp r0, r6 + moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ beq clear_bss /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ ldr r3, _bss_start_ofs diff --git a/arch/arm/cpu/sa1100/start.S b/arch/arm/cpu/sa1100/start.S index bcea2a8deb..1ea92d1456 100644 --- a/arch/arm/cpu/sa1100/start.S +++ b/arch/arm/cpu/sa1100/start.S @@ -160,6 +160,7 @@ stack_setup: adr r0, _start cmp r0, r6 + moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ beq clear_bss /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ ldr r3, _bss_start_ofs diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c index fa1d468041..a10d12d97d 100644 --- a/arch/arm/imx-common/cpu.c +++ b/arch/arm/imx-common/cpu.c @@ -30,6 +30,7 @@ #include <asm/arch/clock.h> #include <asm/arch/sys_proto.h> #include <asm/arch/crm_regs.h> +#include <ipu_pixfmt.h> #ifdef CONFIG_FSL_ESDHC #include <fsl_esdhc.h> @@ -138,3 +139,11 @@ u32 get_ahb_clk(void) return get_periph_clk() / (ahb_podf + 1); } + +#if defined(CONFIG_VIDEO_IPUV3) +void arch_preboot_os(void) +{ + /* disable video before launching O/S */ + ipuv3_fb_shutdown(); +} +#endif diff --git a/arch/arm/include/asm/arch-am33xx/spl.h b/arch/arm/include/asm/arch-am33xx/spl.h index 70f521d269..63ed10b257 100644 --- a/arch/arm/include/asm/arch-am33xx/spl.h +++ b/arch/arm/include/asm/arch-am33xx/spl.h @@ -23,9 +23,11 @@ #ifndef _ASM_ARCH_SPL_H_ #define _ASM_SPL_H_ +#define BOOT_DEVICE_XIP 2 #define BOOT_DEVICE_NAND 5 #define BOOT_DEVICE_MMC1 8 #define BOOT_DEVICE_MMC2 9 /* eMMC or daughter card */ #define BOOT_DEVICE_UART 65 +#define BOOT_DEVICE_CPGMAC 70 #define BOOT_DEVICE_MMC2_2 0xFF #endif diff --git a/arch/arm/include/asm/arch-armv7/globaltimer.h b/arch/arm/include/asm/arch-armv7/globaltimer.h new file mode 100644 index 0000000000..0ac70fd5cd --- /dev/null +++ b/arch/arm/include/asm/arch-armv7/globaltimer.h @@ -0,0 +1,36 @@ +/* + * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> + * (C) Copyright 2012 Renesas Solutions Corp. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _GLOBALTIMER_H_ +#define _GLOBALTIMER_H_ + +struct globaltimer { + u32 cnt_l; /* 0x00 */ + u32 cnt_h; + u32 ctl; + u32 stat; + u32 cmp_l; /* 0x10 */ + u32 cmp_h; + u32 inc; +}; + +#endif /* _GLOBALTIMER_H_ */ diff --git a/arch/arm/include/asm/arch-kirkwood/cpu.h b/arch/arm/include/asm/arch-kirkwood/cpu.h index d28c51a9b6..57bfe8e78b 100644 --- a/arch/arm/include/asm/arch-kirkwood/cpu.h +++ b/arch/arm/include/asm/arch-kirkwood/cpu.h @@ -155,10 +155,10 @@ struct kwgpio_registers { /* * functions */ -void reset_cpu(unsigned long ignored); unsigned char get_random_hex(void); unsigned int kw_sdram_bar(enum memory_bank bank); unsigned int kw_sdram_bs(enum memory_bank bank); +void kw_sdram_size_adjust(enum memory_bank bank); int kw_config_adr_windows(void); void kw_config_gpio(unsigned int gpp0_oe_val, unsigned int gpp1_oe_val, unsigned int gpp0_oe, unsigned int gpp1_oe); diff --git a/arch/arm/include/asm/arch-kirkwood/mpp.h b/arch/arm/include/asm/arch-kirkwood/mpp.h index 8e50ee7f14..8ceea7bb88 100644 --- a/arch/arm/include/asm/arch-kirkwood/mpp.h +++ b/arch/arm/include/asm/arch-kirkwood/mpp.h @@ -85,7 +85,7 @@ #define MPP7_SPI_SCn MPP( 7, 0x2, 0, 1, 1, 1, 1, 1 ) #define MPP7_PTP_TRIG_GEN MPP( 7, 0x3, 0, 1, 1, 1, 1, 1 ) -#define MPP8_GPIO MPP( 8, 0x0, 1, 1, 1, 1, 1, 1 ) +#define MPP8_GPIO MPP( 8, 0x0, 1, 1, 1, 1, 1, 1 ) #define MPP8_TW_SDA MPP( 8, 0x1, 1, 1, 1, 1, 1, 1 ) #define MPP8_UART0_RTS MPP( 8, 0x2, 0, 1, 1, 1, 1, 1 ) #define MPP8_UART1_RTS MPP( 8, 0x3, 0, 1, 1, 1, 1, 1 ) diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h index d1ef15d043..46017f4ad0 100644 --- a/arch/arm/include/asm/arch-mx5/imx-regs.h +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h @@ -321,6 +321,8 @@ #define BOARD_REV_1_0 0x0 #define BOARD_REV_2_0 0x1 +#define BOARD_VER_OFFSET 0x8 + #define IMX_IIM_BASE (IIM_BASE_ADDR) #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) diff --git a/arch/arm/include/asm/arch-orion5x/cpu.h b/arch/arm/include/asm/arch-orion5x/cpu.h index 2f52ca8407..17b9b69be5 100644 --- a/arch/arm/include/asm/arch-orion5x/cpu.h +++ b/arch/arm/include/asm/arch-orion5x/cpu.h @@ -251,7 +251,6 @@ struct orion5x_ddr_addr_decode_registers { /* * functions */ -void reset_cpu(unsigned long ignored); u32 orion5x_device_id(void); u32 orion5x_device_rev(void); unsigned int orion5x_winctrl_calcsize(unsigned int sizeval); diff --git a/arch/arm/include/asm/arch-rmobile/gpio.h b/arch/arm/include/asm/arch-rmobile/gpio.h new file mode 100644 index 0000000000..6b5e4ed4eb --- /dev/null +++ b/arch/arm/include/asm/arch-rmobile/gpio.h @@ -0,0 +1,12 @@ +#ifndef __ASM_ARCH_GPIO_H +#define __ASM_ARCH_GPIO_H + +#if defined(CONFIG_SH73A0) +#include "sh73a0-gpio.h" +void sh73a0_pinmux_init(void); +#elif defined(CONFIG_R8A7740) +#include "r8a7740-gpio.h" +void r8a7740_pinmux_init(void); +#endif + +#endif /* __ASM_ARCH_GPIO_H */ diff --git a/arch/arm/include/asm/arch-rmobile/irqs.h b/arch/arm/include/asm/arch-rmobile/irqs.h new file mode 100644 index 0000000000..dcb714f4d7 --- /dev/null +++ b/arch/arm/include/asm/arch-rmobile/irqs.h @@ -0,0 +1,18 @@ +#ifndef __ASM_MACH_IRQS_H +#define __ASM_MACH_IRQS_H + +#define NR_IRQS 1024 + +/* GIC */ +#define gic_spi(nr) ((nr) + 32) + +/* INTCA */ +#define evt2irq(evt) (((evt) >> 5) - 16) +#define irq2evt(irq) (((irq) + 16) << 5) + +/* INTCS */ +#define INTCS_VECT_BASE 0x2200 +#define INTCS_VECT(n, vect) INTC_VECT((n), INTCS_VECT_BASE + (vect)) +#define intcs_evt2irq(evt) evt2irq(INTCS_VECT_BASE + (evt)) + +#endif /* __ASM_MACH_IRQS_H */ diff --git a/arch/arm/include/asm/arch-rmobile/r8a7740-gpio.h b/arch/arm/include/asm/arch-rmobile/r8a7740-gpio.h new file mode 100644 index 0000000000..9d447abb96 --- /dev/null +++ b/arch/arm/include/asm/arch-rmobile/r8a7740-gpio.h @@ -0,0 +1,584 @@ +/* + * Copyright (C) 2011 Renesas Solutions Corp. + * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __ASM_R8A7740_H__ +#define __ASM_R8A7740_H__ + +/* + * MD_CKx pin + */ +#define MD_CK2 (1 << 2) +#define MD_CK1 (1 << 1) +#define MD_CK0 (1 << 0) + +/* + * Pin Function Controller: + * GPIO_FN_xx - GPIO used to select pin function + * GPIO_PORTxx - GPIO mapped to real I/O pin on CPU + */ +enum { + /* PORT */ + GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4, + GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9, + + GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14, + GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19, + + GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24, + GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29, + + GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34, + GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39, + + GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44, + GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49, + + GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54, + GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59, + + GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64, + GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69, + + GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74, + GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79, + + GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84, + GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89, + + GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94, + GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99, + + GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104, + GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109, + + GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114, + GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118, GPIO_PORT119, + + GPIO_PORT120, GPIO_PORT121, GPIO_PORT122, GPIO_PORT123, GPIO_PORT124, + GPIO_PORT125, GPIO_PORT126, GPIO_PORT127, GPIO_PORT128, GPIO_PORT129, + + GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134, + GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139, + + GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144, + GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149, + + GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154, + GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159, + + GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164, + GPIO_PORT165, GPIO_PORT166, GPIO_PORT167, GPIO_PORT168, GPIO_PORT169, + + GPIO_PORT170, GPIO_PORT171, GPIO_PORT172, GPIO_PORT173, GPIO_PORT174, + GPIO_PORT175, GPIO_PORT176, GPIO_PORT177, GPIO_PORT178, GPIO_PORT179, + + GPIO_PORT180, GPIO_PORT181, GPIO_PORT182, GPIO_PORT183, GPIO_PORT184, + GPIO_PORT185, GPIO_PORT186, GPIO_PORT187, GPIO_PORT188, GPIO_PORT189, + + GPIO_PORT190, GPIO_PORT191, GPIO_PORT192, GPIO_PORT193, GPIO_PORT194, + GPIO_PORT195, GPIO_PORT196, GPIO_PORT197, GPIO_PORT198, GPIO_PORT199, + + GPIO_PORT200, GPIO_PORT201, GPIO_PORT202, GPIO_PORT203, GPIO_PORT204, + GPIO_PORT205, GPIO_PORT206, GPIO_PORT207, GPIO_PORT208, GPIO_PORT209, + + GPIO_PORT210, GPIO_PORT211, + + /* IRQ */ + GPIO_FN_IRQ0_PORT2, GPIO_FN_IRQ0_PORT13, + GPIO_FN_IRQ1, + GPIO_FN_IRQ2_PORT11, GPIO_FN_IRQ2_PORT12, + GPIO_FN_IRQ3_PORT10, GPIO_FN_IRQ3_PORT14, + GPIO_FN_IRQ4_PORT15, GPIO_FN_IRQ4_PORT172, + GPIO_FN_IRQ5_PORT0, GPIO_FN_IRQ5_PORT1, + GPIO_FN_IRQ6_PORT121, GPIO_FN_IRQ6_PORT173, + GPIO_FN_IRQ7_PORT120, GPIO_FN_IRQ7_PORT209, + GPIO_FN_IRQ8, + GPIO_FN_IRQ9_PORT118, GPIO_FN_IRQ9_PORT210, + GPIO_FN_IRQ10, + GPIO_FN_IRQ11, + GPIO_FN_IRQ12_PORT42, GPIO_FN_IRQ12_PORT97, + GPIO_FN_IRQ13_PORT64, GPIO_FN_IRQ13_PORT98, + GPIO_FN_IRQ14_PORT63, GPIO_FN_IRQ14_PORT99, + GPIO_FN_IRQ15_PORT62, GPIO_FN_IRQ15_PORT100, + GPIO_FN_IRQ16_PORT68, GPIO_FN_IRQ16_PORT211, + GPIO_FN_IRQ17, + GPIO_FN_IRQ18, + GPIO_FN_IRQ19, + GPIO_FN_IRQ20, + GPIO_FN_IRQ21, + GPIO_FN_IRQ22, + GPIO_FN_IRQ23, + GPIO_FN_IRQ24, + GPIO_FN_IRQ25, + GPIO_FN_IRQ26_PORT58, GPIO_FN_IRQ26_PORT81, + GPIO_FN_IRQ27_PORT57, GPIO_FN_IRQ27_PORT168, + GPIO_FN_IRQ28_PORT56, GPIO_FN_IRQ28_PORT169, + GPIO_FN_IRQ29_PORT50, GPIO_FN_IRQ29_PORT170, + GPIO_FN_IRQ30_PORT49, GPIO_FN_IRQ30_PORT171, + GPIO_FN_IRQ31_PORT41, GPIO_FN_IRQ31_PORT167, + + /* Function */ + + /* DBGT */ + GPIO_FN_DBGMDT2, GPIO_FN_DBGMDT1, GPIO_FN_DBGMDT0, + GPIO_FN_DBGMD10, GPIO_FN_DBGMD11, GPIO_FN_DBGMD20, + GPIO_FN_DBGMD21, + + /* FSI */ + GPIO_FN_FSIAISLD_PORT0, /* FSIAISLD Port 0/5 */ + GPIO_FN_FSIAISLD_PORT5, + GPIO_FN_FSIASPDIF_PORT9, /* FSIASPDIF Port 9/18 */ + GPIO_FN_FSIASPDIF_PORT18, + GPIO_FN_FSIAOSLD1, GPIO_FN_FSIAOSLD2, + GPIO_FN_FSIAOLR, GPIO_FN_FSIAOBT, + GPIO_FN_FSIAOSLD, GPIO_FN_FSIAOMC, + GPIO_FN_FSIACK, GPIO_FN_FSIAILR, + GPIO_FN_FSIAIBT, + + /* FMSI */ + GPIO_FN_FMSISLD_PORT1, /* FMSISLD Port 1/6 */ + GPIO_FN_FMSISLD_PORT6, + GPIO_FN_FMSIILR, GPIO_FN_FMSIIBT, + GPIO_FN_FMSIOLR, GPIO_FN_FMSIOBT, + GPIO_FN_FMSICK, GPIO_FN_FMSOILR, + GPIO_FN_FMSOIBT, GPIO_FN_FMSOOLR, + GPIO_FN_FMSOOBT, GPIO_FN_FMSOSLD, + GPIO_FN_FMSOCK, + + /* SCIFA0 */ + GPIO_FN_SCIFA0_SCK, GPIO_FN_SCIFA0_CTS, + GPIO_FN_SCIFA0_RTS, GPIO_FN_SCIFA0_RXD, + GPIO_FN_SCIFA0_TXD, + + /* SCIFA1 */ + GPIO_FN_SCIFA1_CTS, GPIO_FN_SCIFA1_SCK, + GPIO_FN_SCIFA1_RXD, GPIO_FN_SCIFA1_TXD, + GPIO_FN_SCIFA1_RTS, + + /* SCIFA2 */ + GPIO_FN_SCIFA2_SCK_PORT22, /* SCIFA2_SCK Port 22/199 */ + GPIO_FN_SCIFA2_SCK_PORT199, + GPIO_FN_SCIFA2_RXD, GPIO_FN_SCIFA2_TXD, + GPIO_FN_SCIFA2_CTS, GPIO_FN_SCIFA2_RTS, + + /* SCIFA3 */ + GPIO_FN_SCIFA3_RTS_PORT105, /* MSEL5CR_8_0 */ + GPIO_FN_SCIFA3_SCK_PORT116, + GPIO_FN_SCIFA3_CTS_PORT117, + GPIO_FN_SCIFA3_RXD_PORT174, + GPIO_FN_SCIFA3_TXD_PORT175, + + GPIO_FN_SCIFA3_RTS_PORT161, /* MSEL5CR_8_1 */ + GPIO_FN_SCIFA3_SCK_PORT158, + GPIO_FN_SCIFA3_CTS_PORT162, + GPIO_FN_SCIFA3_RXD_PORT159, + GPIO_FN_SCIFA3_TXD_PORT160, + + /* SCIFA4 */ + GPIO_FN_SCIFA4_RXD_PORT12, /* MSEL5CR[12:11] = 00 */ + GPIO_FN_SCIFA4_TXD_PORT13, + + GPIO_FN_SCIFA4_RXD_PORT204, /* MSEL5CR[12:11] = 01 */ + GPIO_FN_SCIFA4_TXD_PORT203, + + GPIO_FN_SCIFA4_RXD_PORT94, /* MSEL5CR[12:11] = 10 */ + GPIO_FN_SCIFA4_TXD_PORT93, + + GPIO_FN_SCIFA4_SCK_PORT21, /* SCIFA4_SCK Port 21/205 */ + GPIO_FN_SCIFA4_SCK_PORT205, + + /* SCIFA5 */ + GPIO_FN_SCIFA5_TXD_PORT20, /* MSEL5CR[15:14] = 00 */ + GPIO_FN_SCIFA5_RXD_PORT10, + + GPIO_FN_SCIFA5_RXD_PORT207, /* MSEL5CR[15:14] = 01 */ + GPIO_FN_SCIFA5_TXD_PORT208, + + GPIO_FN_SCIFA5_TXD_PORT91, /* MSEL5CR[15:14] = 10 */ + GPIO_FN_SCIFA5_RXD_PORT92, + + GPIO_FN_SCIFA5_SCK_PORT23, /* SCIFA5_SCK Port 23/206 */ + GPIO_FN_SCIFA5_SCK_PORT206, + + /* SCIFA6 */ + GPIO_FN_SCIFA6_SCK, GPIO_FN_SCIFA6_RXD, GPIO_FN_SCIFA6_TXD, + + /* SCIFA7 */ + GPIO_FN_SCIFA7_TXD, GPIO_FN_SCIFA7_RXD, + + /* SCIFAB */ + GPIO_FN_SCIFB_SCK_PORT190, /* MSEL5CR_17_0 */ + GPIO_FN_SCIFB_RXD_PORT191, + GPIO_FN_SCIFB_TXD_PORT192, + GPIO_FN_SCIFB_RTS_PORT186, + GPIO_FN_SCIFB_CTS_PORT187, + + GPIO_FN_SCIFB_SCK_PORT2, /* MSEL5CR_17_1 */ + GPIO_FN_SCIFB_RXD_PORT3, + GPIO_FN_SCIFB_TXD_PORT4, + GPIO_FN_SCIFB_RTS_PORT172, + GPIO_FN_SCIFB_CTS_PORT173, + + /* LCD0 */ + GPIO_FN_LCDC0_SELECT, + GPIO_FN_LCD0_D0, GPIO_FN_LCD0_D1, GPIO_FN_LCD0_D2, + GPIO_FN_LCD0_D3, GPIO_FN_LCD0_D4, GPIO_FN_LCD0_D5, + GPIO_FN_LCD0_D6, GPIO_FN_LCD0_D7, GPIO_FN_LCD0_D8, + GPIO_FN_LCD0_D9, GPIO_FN_LCD0_D10, GPIO_FN_LCD0_D11, + GPIO_FN_LCD0_D12, GPIO_FN_LCD0_D13, GPIO_FN_LCD0_D14, + GPIO_FN_LCD0_D15, GPIO_FN_LCD0_D16, GPIO_FN_LCD0_D17, + GPIO_FN_LCD0_DON, GPIO_FN_LCD0_VCPWC, GPIO_FN_LCD0_VEPWC, + + GPIO_FN_LCD0_DCK, GPIO_FN_LCD0_VSYN, /* for RGB */ + GPIO_FN_LCD0_HSYN, GPIO_FN_LCD0_DISP, /* for RGB */ + + GPIO_FN_LCD0_WR, GPIO_FN_LCD0_RD, /* for SYS */ + GPIO_FN_LCD0_CS, GPIO_FN_LCD0_RS, /* for SYS */ + + GPIO_FN_LCD0_D18_PORT163, GPIO_FN_LCD0_D19_PORT162, + GPIO_FN_LCD0_D20_PORT161, GPIO_FN_LCD0_D21_PORT158, + GPIO_FN_LCD0_D22_PORT160, GPIO_FN_LCD0_D23_PORT159, + GPIO_FN_LCD0_LCLK_PORT165, /* MSEL5CR_6_1 */ + + GPIO_FN_LCD0_D18_PORT40, GPIO_FN_LCD0_D19_PORT4, + GPIO_FN_LCD0_D20_PORT3, GPIO_FN_LCD0_D21_PORT2, + GPIO_FN_LCD0_D22_PORT0, GPIO_FN_LCD0_D23_PORT1, + GPIO_FN_LCD0_LCLK_PORT102, /* MSEL5CR_6_0 */ + + /* LCD1 */ + GPIO_FN_LCDC1_SELECT, + GPIO_FN_LCD1_D0, GPIO_FN_LCD1_D1, GPIO_FN_LCD1_D2, + GPIO_FN_LCD1_D3, GPIO_FN_LCD1_D4, GPIO_FN_LCD1_D5, + GPIO_FN_LCD1_D6, GPIO_FN_LCD1_D7, GPIO_FN_LCD1_D8, + GPIO_FN_LCD1_D9, GPIO_FN_LCD1_D10, GPIO_FN_LCD1_D11, + GPIO_FN_LCD1_D12, GPIO_FN_LCD1_D13, GPIO_FN_LCD1_D14, + GPIO_FN_LCD1_D15, GPIO_FN_LCD1_D16, GPIO_FN_LCD1_D17, + GPIO_FN_LCD1_D18, GPIO_FN_LCD1_D19, GPIO_FN_LCD1_D20, + GPIO_FN_LCD1_D21, GPIO_FN_LCD1_D22, GPIO_FN_LCD1_D23, + GPIO_FN_LCD1_DON, GPIO_FN_LCD1_VCPWC, + GPIO_FN_LCD1_LCLK, GPIO_FN_LCD1_VEPWC, + + GPIO_FN_LCD1_DCK, GPIO_FN_LCD1_VSYN, /* for RGB */ + GPIO_FN_LCD1_HSYN, GPIO_FN_LCD1_DISP, /* for RGB */ + + GPIO_FN_LCD1_WR, GPIO_FN_LCD1_RD, /* for SYS */ + GPIO_FN_LCD1_CS, GPIO_FN_LCD1_RS, /* for SYS */ + + /* RSPI */ + GPIO_FN_RSPI_SSL0_A, GPIO_FN_RSPI_SSL1_A, + GPIO_FN_RSPI_SSL2_A, GPIO_FN_RSPI_SSL3_A, + GPIO_FN_RSPI_MOSI_A, GPIO_FN_RSPI_MISO_A, + GPIO_FN_RSPI_CK_A, + + /* VIO CKO */ + GPIO_FN_VIO_CKO1, + GPIO_FN_VIO_CKO2, + GPIO_FN_VIO_CKO_1, + GPIO_FN_VIO_CKO, + + /* VIO0 */ + GPIO_FN_VIO0_D0, GPIO_FN_VIO0_D1, GPIO_FN_VIO0_D2, + GPIO_FN_VIO0_D3, GPIO_FN_VIO0_D4, GPIO_FN_VIO0_D5, + GPIO_FN_VIO0_D6, GPIO_FN_VIO0_D7, GPIO_FN_VIO0_D8, + GPIO_FN_VIO0_D9, GPIO_FN_VIO0_D10, GPIO_FN_VIO0_D11, + GPIO_FN_VIO0_D12, GPIO_FN_VIO0_VD, GPIO_FN_VIO0_HD, + GPIO_FN_VIO0_CLK, GPIO_FN_VIO0_FIELD, + + GPIO_FN_VIO0_D13_PORT26, /* MSEL5CR_27_0 */ + GPIO_FN_VIO0_D14_PORT25, + GPIO_FN_VIO0_D15_PORT24, + + GPIO_FN_VIO0_D13_PORT22, /* MSEL5CR_27_1 */ + GPIO_FN_VIO0_D14_PORT95, + GPIO_FN_VIO0_D15_PORT96, + + /* VIO1 */ + GPIO_FN_VIO1_D0, GPIO_FN_VIO1_D1, GPIO_FN_VIO1_D2, + GPIO_FN_VIO1_D3, GPIO_FN_VIO1_D4, GPIO_FN_VIO1_D5, + GPIO_FN_VIO1_D6, GPIO_FN_VIO1_D7, GPIO_FN_VIO1_VD, + GPIO_FN_VIO1_HD, GPIO_FN_VIO1_CLK, GPIO_FN_VIO1_FIELD, + + /* TPU0 */ + GPIO_FN_TPU0TO0, GPIO_FN_TPU0TO1, + GPIO_FN_TPU0TO3, + GPIO_FN_TPU0TO2_PORT66, /* TPU0TO2 Port 66/202 */ + GPIO_FN_TPU0TO2_PORT202, + + /* SSP1 0 */ + GPIO_FN_STP0_IPD0, GPIO_FN_STP0_IPD1, GPIO_FN_STP0_IPD2, + GPIO_FN_STP0_IPD3, GPIO_FN_STP0_IPD4, GPIO_FN_STP0_IPD5, + GPIO_FN_STP0_IPD6, GPIO_FN_STP0_IPD7, GPIO_FN_STP0_IPEN, + GPIO_FN_STP0_IPCLK, GPIO_FN_STP0_IPSYNC, + + /* SSP1 1 */ + GPIO_FN_STP1_IPD1, GPIO_FN_STP1_IPD2, GPIO_FN_STP1_IPD3, + GPIO_FN_STP1_IPD4, GPIO_FN_STP1_IPD5, GPIO_FN_STP1_IPD6, + GPIO_FN_STP1_IPD7, GPIO_FN_STP1_IPCLK, GPIO_FN_STP1_IPSYNC, + + GPIO_FN_STP1_IPD0_PORT186, /* MSEL5CR_23_0 */ + GPIO_FN_STP1_IPEN_PORT187, + + GPIO_FN_STP1_IPD0_PORT194, /* MSEL5CR_23_1 */ + GPIO_FN_STP1_IPEN_PORT193, + + /* SIM */ + GPIO_FN_SIM_RST, GPIO_FN_SIM_CLK, + GPIO_FN_SIM_D_PORT22, /* SIM_D Port 22/199 */ + GPIO_FN_SIM_D_PORT199, + + /* SDHI0 */ + GPIO_FN_SDHI0_D0, GPIO_FN_SDHI0_D1, GPIO_FN_SDHI0_D2, + GPIO_FN_SDHI0_D3, GPIO_FN_SDHI0_CD, GPIO_FN_SDHI0_WP, + GPIO_FN_SDHI0_CMD, GPIO_FN_SDHI0_CLK, + + /* SDHI1 */ + GPIO_FN_SDHI1_D0, GPIO_FN_SDHI1_D1, GPIO_FN_SDHI1_D2, + GPIO_FN_SDHI1_D3, GPIO_FN_SDHI1_CD, GPIO_FN_SDHI1_WP, + GPIO_FN_SDHI1_CMD, GPIO_FN_SDHI1_CLK, + + /* SDHI2 */ + GPIO_FN_SDHI2_D0, GPIO_FN_SDHI2_D1, GPIO_FN_SDHI2_D2, + GPIO_FN_SDHI2_D3, GPIO_FN_SDHI2_CLK, GPIO_FN_SDHI2_CMD, + + GPIO_FN_SDHI2_CD_PORT24, /* MSEL5CR_19_0 */ + GPIO_FN_SDHI2_WP_PORT25, + + GPIO_FN_SDHI2_WP_PORT177, /* MSEL5CR_19_1 */ + GPIO_FN_SDHI2_CD_PORT202, + + /* MSIOF2 */ + GPIO_FN_MSIOF2_TXD, GPIO_FN_MSIOF2_RXD, GPIO_FN_MSIOF2_TSCK, + GPIO_FN_MSIOF2_SS2, GPIO_FN_MSIOF2_TSYNC, GPIO_FN_MSIOF2_SS1, + GPIO_FN_MSIOF2_MCK1, GPIO_FN_MSIOF2_MCK0, GPIO_FN_MSIOF2_RSYNC, + GPIO_FN_MSIOF2_RSCK, + + /* KEYSC */ + GPIO_FN_KEYIN4, GPIO_FN_KEYIN5, + GPIO_FN_KEYIN6, GPIO_FN_KEYIN7, + GPIO_FN_KEYOUT0, GPIO_FN_KEYOUT1, GPIO_FN_KEYOUT2, + GPIO_FN_KEYOUT3, GPIO_FN_KEYOUT4, GPIO_FN_KEYOUT5, + GPIO_FN_KEYOUT6, GPIO_FN_KEYOUT7, + + GPIO_FN_KEYIN0_PORT43, /* MSEL4CR_18_0 */ + GPIO_FN_KEYIN1_PORT44, + GPIO_FN_KEYIN2_PORT45, + GPIO_FN_KEYIN3_PORT46, + + GPIO_FN_KEYIN0_PORT58, /* MSEL4CR_18_1 */ + GPIO_FN_KEYIN1_PORT57, + GPIO_FN_KEYIN2_PORT56, + GPIO_FN_KEYIN3_PORT55, + + /* VOU */ + GPIO_FN_DV_D0, GPIO_FN_DV_D1, GPIO_FN_DV_D2, GPIO_FN_DV_D3, + GPIO_FN_DV_D4, GPIO_FN_DV_D5, GPIO_FN_DV_D6, GPIO_FN_DV_D7, + GPIO_FN_DV_D8, GPIO_FN_DV_D9, GPIO_FN_DV_D10, GPIO_FN_DV_D11, + GPIO_FN_DV_D12, GPIO_FN_DV_D13, GPIO_FN_DV_D14, GPIO_FN_DV_D15, + GPIO_FN_DV_CLK, + GPIO_FN_DV_VSYNC, + GPIO_FN_DV_HSYNC, + + /* MEMC */ + GPIO_FN_MEMC_AD0, GPIO_FN_MEMC_AD1, GPIO_FN_MEMC_AD2, + GPIO_FN_MEMC_AD3, GPIO_FN_MEMC_AD4, GPIO_FN_MEMC_AD5, + GPIO_FN_MEMC_AD6, GPIO_FN_MEMC_AD7, GPIO_FN_MEMC_AD8, + GPIO_FN_MEMC_AD9, GPIO_FN_MEMC_AD10, GPIO_FN_MEMC_AD11, + GPIO_FN_MEMC_AD12, GPIO_FN_MEMC_AD13, GPIO_FN_MEMC_AD14, + GPIO_FN_MEMC_AD15, GPIO_FN_MEMC_CS0, GPIO_FN_MEMC_INT, + GPIO_FN_MEMC_NWE, GPIO_FN_MEMC_NOE, + + GPIO_FN_MEMC_CS1, /* MSEL4CR_6_0 */ + GPIO_FN_MEMC_ADV, + GPIO_FN_MEMC_WAIT, + GPIO_FN_MEMC_BUSCLK, + + GPIO_FN_MEMC_A1, /* MSEL4CR_6_1 */ + GPIO_FN_MEMC_DREQ0, + GPIO_FN_MEMC_DREQ1, + GPIO_FN_MEMC_A0, + + /* MMC */ + GPIO_FN_MMC0_D0_PORT68, GPIO_FN_MMC0_D1_PORT69, + GPIO_FN_MMC0_D2_PORT70, GPIO_FN_MMC0_D3_PORT71, + GPIO_FN_MMC0_D4_PORT72, GPIO_FN_MMC0_D5_PORT73, + GPIO_FN_MMC0_D6_PORT74, GPIO_FN_MMC0_D7_PORT75, + GPIO_FN_MMC0_CLK_PORT66, + GPIO_FN_MMC0_CMD_PORT67, /* MSEL4CR_15_0 */ + + GPIO_FN_MMC1_D0_PORT149, GPIO_FN_MMC1_D1_PORT148, + GPIO_FN_MMC1_D2_PORT147, GPIO_FN_MMC1_D3_PORT146, + GPIO_FN_MMC1_D4_PORT145, GPIO_FN_MMC1_D5_PORT144, + GPIO_FN_MMC1_D6_PORT143, GPIO_FN_MMC1_D7_PORT142, + GPIO_FN_MMC1_CLK_PORT103, + GPIO_FN_MMC1_CMD_PORT104, /* MSEL4CR_15_1 */ + + /* MSIOF0 */ + GPIO_FN_MSIOF0_SS1, GPIO_FN_MSIOF0_SS2, + GPIO_FN_MSIOF0_RXD, GPIO_FN_MSIOF0_TXD, + GPIO_FN_MSIOF0_MCK0, GPIO_FN_MSIOF0_MCK1, + GPIO_FN_MSIOF0_RSYNC, GPIO_FN_MSIOF0_RSCK, + GPIO_FN_MSIOF0_TSCK, GPIO_FN_MSIOF0_TSYNC, + + /* MSIOF1 */ + GPIO_FN_MSIOF1_RSCK, GPIO_FN_MSIOF1_RSYNC, + GPIO_FN_MSIOF1_MCK0, GPIO_FN_MSIOF1_MCK1, + + GPIO_FN_MSIOF1_SS2_PORT116, GPIO_FN_MSIOF1_SS1_PORT117, + GPIO_FN_MSIOF1_RXD_PORT118, GPIO_FN_MSIOF1_TXD_PORT119, + GPIO_FN_MSIOF1_TSYNC_PORT120, + GPIO_FN_MSIOF1_TSCK_PORT121, /* MSEL4CR_10_0 */ + + GPIO_FN_MSIOF1_SS1_PORT67, GPIO_FN_MSIOF1_TSCK_PORT72, + GPIO_FN_MSIOF1_TSYNC_PORT73, GPIO_FN_MSIOF1_TXD_PORT74, + GPIO_FN_MSIOF1_RXD_PORT75, + GPIO_FN_MSIOF1_SS2_PORT202, /* MSEL4CR_10_1 */ + + /* GPIO */ + GPIO_FN_GPO0, GPIO_FN_GPI0, + GPIO_FN_GPO1, GPIO_FN_GPI1, + + /* USB0 */ + GPIO_FN_USB0_OCI, GPIO_FN_USB0_PPON, GPIO_FN_VBUS, + + /* USB1 */ + GPIO_FN_USB1_OCI, GPIO_FN_USB1_PPON, + + /* BBIF1 */ + GPIO_FN_BBIF1_RXD, GPIO_FN_BBIF1_TXD, GPIO_FN_BBIF1_TSYNC, + GPIO_FN_BBIF1_TSCK, GPIO_FN_BBIF1_RSCK, GPIO_FN_BBIF1_RSYNC, + GPIO_FN_BBIF1_FLOW, GPIO_FN_BBIF1_RX_FLOW_N, + + /* BBIF2 */ + GPIO_FN_BBIF2_TXD2_PORT5, /* MSEL5CR_0_0 */ + GPIO_FN_BBIF2_RXD2_PORT60, + GPIO_FN_BBIF2_TSYNC2_PORT6, + GPIO_FN_BBIF2_TSCK2_PORT59, + + GPIO_FN_BBIF2_RXD2_PORT90, /* MSEL5CR_0_1 */ + GPIO_FN_BBIF2_TXD2_PORT183, + GPIO_FN_BBIF2_TSCK2_PORT89, + GPIO_FN_BBIF2_TSYNC2_PORT184, + + /* BSC / FLCTL / PCMCIA */ + GPIO_FN_CS0, GPIO_FN_CS2, GPIO_FN_CS4, + GPIO_FN_CS5B, GPIO_FN_CS6A, + GPIO_FN_CS5A_PORT105, /* CS5A PORT 19/105 */ + GPIO_FN_CS5A_PORT19, + GPIO_FN_IOIS16, /* ? */ + + GPIO_FN_A0, GPIO_FN_A1, GPIO_FN_A2, GPIO_FN_A3, + GPIO_FN_A4_FOE, /* share with FLCTL */ + GPIO_FN_A5_FCDE, /* share with FLCTL */ + GPIO_FN_A6, GPIO_FN_A7, GPIO_FN_A8, GPIO_FN_A9, + GPIO_FN_A10, GPIO_FN_A11, GPIO_FN_A12, GPIO_FN_A13, + GPIO_FN_A14, GPIO_FN_A15, GPIO_FN_A16, GPIO_FN_A17, + GPIO_FN_A18, GPIO_FN_A19, GPIO_FN_A20, GPIO_FN_A21, + GPIO_FN_A22, GPIO_FN_A23, GPIO_FN_A24, GPIO_FN_A25, + GPIO_FN_A26, + + GPIO_FN_D0_NAF0, GPIO_FN_D1_NAF1, /* share with FLCTL */ + GPIO_FN_D2_NAF2, GPIO_FN_D3_NAF3, /* share with FLCTL */ + GPIO_FN_D4_NAF4, GPIO_FN_D5_NAF5, /* share with FLCTL */ + GPIO_FN_D6_NAF6, GPIO_FN_D7_NAF7, /* share with FLCTL */ + GPIO_FN_D8_NAF8, GPIO_FN_D9_NAF9, /* share with FLCTL */ + GPIO_FN_D10_NAF10, GPIO_FN_D11_NAF11, /* share with FLCTL */ + GPIO_FN_D12_NAF12, GPIO_FN_D13_NAF13, /* share with FLCTL */ + GPIO_FN_D14_NAF14, GPIO_FN_D15_NAF15, /* share with FLCTL */ + + GPIO_FN_D16, GPIO_FN_D17, GPIO_FN_D18, GPIO_FN_D19, + GPIO_FN_D20, GPIO_FN_D21, GPIO_FN_D22, GPIO_FN_D23, + GPIO_FN_D24, GPIO_FN_D25, GPIO_FN_D26, GPIO_FN_D27, + GPIO_FN_D28, GPIO_FN_D29, GPIO_FN_D30, GPIO_FN_D31, + + GPIO_FN_WE0_FWE, /* share with FLCTL */ + GPIO_FN_WE1, + GPIO_FN_WE2_ICIORD, /* share with PCMCIA */ + GPIO_FN_WE3_ICIOWR, /* share with PCMCIA */ + GPIO_FN_CKO, GPIO_FN_BS, GPIO_FN_RDWR, + GPIO_FN_RD_FSC, /* share with FLCTL */ + GPIO_FN_WAIT_PORT177, /* WAIT Port 90/177 */ + GPIO_FN_WAIT_PORT90, + + GPIO_FN_FCE0, GPIO_FN_FCE1, GPIO_FN_FRB, /* FLCTL */ + + /* IRDA */ + GPIO_FN_IRDA_FIRSEL, GPIO_FN_IRDA_IN, GPIO_FN_IRDA_OUT, + + /* ATAPI */ + GPIO_FN_IDE_D0, GPIO_FN_IDE_D1, GPIO_FN_IDE_D2, + GPIO_FN_IDE_D3, GPIO_FN_IDE_D4, GPIO_FN_IDE_D5, + GPIO_FN_IDE_D6, GPIO_FN_IDE_D7, GPIO_FN_IDE_D8, + GPIO_FN_IDE_D9, GPIO_FN_IDE_D10, GPIO_FN_IDE_D11, + GPIO_FN_IDE_D12, GPIO_FN_IDE_D13, GPIO_FN_IDE_D14, + GPIO_FN_IDE_D15, GPIO_FN_IDE_A0, GPIO_FN_IDE_A1, + GPIO_FN_IDE_A2, GPIO_FN_IDE_CS0, GPIO_FN_IDE_CS1, + GPIO_FN_IDE_IOWR, GPIO_FN_IDE_IORD, GPIO_FN_IDE_IORDY, + GPIO_FN_IDE_INT, GPIO_FN_IDE_RST, GPIO_FN_IDE_DIRECTION, + GPIO_FN_IDE_EXBUF_ENB, GPIO_FN_IDE_IODACK, GPIO_FN_IDE_IODREQ, + + /* RMII */ + GPIO_FN_RMII_CRS_DV, GPIO_FN_RMII_RX_ER, GPIO_FN_RMII_RXD0, + GPIO_FN_RMII_RXD1, GPIO_FN_RMII_TX_EN, GPIO_FN_RMII_TXD0, + GPIO_FN_RMII_MDC, GPIO_FN_RMII_TXD1, GPIO_FN_RMII_MDIO, + GPIO_FN_RMII_REF50CK, /* for RMII */ + GPIO_FN_RMII_REF125CK, /* for GMII */ + + /* GEther */ + GPIO_FN_ET_TX_CLK, GPIO_FN_ET_TX_EN, GPIO_FN_ET_ETXD0, + GPIO_FN_ET_ETXD1, GPIO_FN_ET_ETXD2, GPIO_FN_ET_ETXD3, + GPIO_FN_ET_ETXD4, GPIO_FN_ET_ETXD5, /* for GEther */ + GPIO_FN_ET_ETXD6, GPIO_FN_ET_ETXD7, /* for GEther */ + GPIO_FN_ET_COL, GPIO_FN_ET_TX_ER, + GPIO_FN_ET_RX_CLK, GPIO_FN_ET_RX_DV, + GPIO_FN_ET_ERXD0, GPIO_FN_ET_ERXD1, + GPIO_FN_ET_ERXD2, GPIO_FN_ET_ERXD3, + GPIO_FN_ET_ERXD4, GPIO_FN_ET_ERXD5, /* for GEther */ + GPIO_FN_ET_ERXD6, GPIO_FN_ET_ERXD7, /* for GEther */ + GPIO_FN_ET_RX_ER, GPIO_FN_ET_CRS, + GPIO_FN_ET_MDC, GPIO_FN_ET_MDIO, + GPIO_FN_ET_LINK, GPIO_FN_ET_PHY_INT, + GPIO_FN_ET_WOL, GPIO_FN_ET_GTX_CLK, + + /* DMA0 */ + GPIO_FN_DREQ0, GPIO_FN_DACK0, + + /* DMA1 */ + GPIO_FN_DREQ1, GPIO_FN_DACK1, + + /* SYSC */ + GPIO_FN_RESETOUTS, + GPIO_FN_RESETP_PULLUP, + GPIO_FN_RESETP_PLAIN, + + /* SDENC */ + GPIO_FN_SDENC_CPG, + GPIO_FN_SDENC_DV_CLKI, + + /* IRREM */ + GPIO_FN_IROUT, + + /* DEBUG */ + GPIO_FN_EDEBGREQ_PULLDOWN, + GPIO_FN_EDEBGREQ_PULLUP, + + GPIO_FN_TRACEAUD_FROM_VIO, + GPIO_FN_TRACEAUD_FROM_LCDC0, + GPIO_FN_TRACEAUD_FROM_MEMC, +}; + +#endif /* __ASM_R8A7740_H__ */ diff --git a/arch/arm/include/asm/arch-rmobile/r8a7740.h b/arch/arm/include/asm/arch-rmobile/r8a7740.h new file mode 100644 index 0000000000..8f179505d0 --- /dev/null +++ b/arch/arm/include/asm/arch-rmobile/r8a7740.h @@ -0,0 +1,287 @@ +/* + * Copyright (C) 2012 Renesas Solutions Corp. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#ifndef __ASM_ARCH_R8A7740_H +#define __ASM_ARCH_R8A7740_H + +/* + * R8A7740 I/O Addresses + */ + +#define MERAM_BASE 0xE5580000 +#define DDRP_BASE 0xC12A0000 +#define HPB_BASE 0xE6000000 +#define RWDT0_BASE 0xE6020000 +#define RWDT1_BASE 0xE6030000 +#define GPIO_BASE 0xE6050000 +#define CMT1_BASE 0xE6138000 +#define CPG_BASE 0xE6150000 +#define SYSC_BASE 0xE6180000 +#define SDHI0_BASE 0xE6850000 +#define SDHI1_BASE 0xE6860000 +#define MMCIF_BASE 0xE6BD0000 +#define SCIF5_BASE 0xE6CB0000 +#define SCIF6_BASE 0xE6CC0000 +#define DBSC_BASE 0xFE400000 +#define BSC_BASE 0xFEC10000 +#define I2C0_BASE 0xFFF20000 +#define I2C1_BASE 0xE6C20000 +#define TMU_BASE 0xFFF80000 + +#ifndef __ASSEMBLY__ +#include <asm/types.h> + +/* RWDT */ +struct r8a7740_rwdt { + u16 rwtcnt0; /* 0x00 */ + u16 dummy0; /* 0x02 */ + u16 rwtcsra0; /* 0x04 */ + u16 dummy1; /* 0x06 */ + u16 rwtcsrb0; /* 0x08 */ + u16 dummy2; /* 0x0A */ +}; + +/* HPB Semaphore Control Registers */ +struct r8a7740_hpb { + u32 hpbctrl0; + u32 hpbctrl1; + u32 hpbctrl2; + u32 cccr; + u32 dummy0; /* 0x20 */ + u32 hpbctrl4; + u32 hpbctrl5; +}; + +/* CPG */ +struct r8a7740_cpg { + u32 frqcra; + u32 frqcrb; + u32 vclkcr1; + u32 vclkcr2; + u32 fmsickcr; + u32 fmsockcr; + u32 fsiackcr; + u32 dummy0; /* 0x1c */ + u32 rtstbcr; + u32 systbcr; + u32 pllc01cr; + u32 pllc2cr; + u32 mstpsr0; + u32 dummy1; /* 0x34 */ + u32 mstpsr1; + u32 mstpsr5; + u32 mstpsr2; + u32 dummy2; /* 0x44 */ + u32 mstpsr3; + u32 mstpsr4; + u32 dummy3; /* 0x50 */ + u32 astat; + u32 dummy4[4]; /* 0x58 .. 0x64 */ + u32 ztrckcr; + u32 dummy5[5]; /* 0x6c .. 0x7c */ + u32 subckcr; + u32 spuckcr; + u32 vouckcr; + u32 usbckcr; + u32 dummy6[3]; /* 0x90 .. 0x98 */ + u32 stprckcr; + u32 srcr0; + u32 dummy7; /* 0xa4 */ + u32 srcr1; + u32 dummy8; /* 0xac */ + u32 srcr2; + u32 dummy9; /* 0xb4 */ + u32 srcr3; + u32 srcr4; + u32 dummy10; /* 0xc0 */ + u32 srcr5; + u32 pllc01stpcr; + u32 dummy11[5]; /* 0xcc .. 0xdc */ + u32 frqcrc; + u32 frqcrd; + u32 dummy12[10]; /* 0xe8 .. 0x10c */ + u32 rmstpcr0; + u32 rmstpcr1; + u32 rmstpcr2; + u32 rmstpcr3; + u32 rmstpcr4; + u32 rmstpcr5; + u32 dummy13[2]; /* 0x128 .. 0x12c */ + u32 smstpcr0; + u32 smstpcr1; + u32 smstpcr2; + u32 smstpcr3; + u32 smstpcr4; + u32 smstpcr5; +}; + +/* BSC */ +struct r8a7740_bsc { + u32 cmncr; + u32 cs0bcr; + u32 cs2bcr; + u32 dummy0; /* 0x0c */ + u32 cs4bcr; + u32 cs5abcr; + u32 cs5bbcr; + u32 cs6abcr; + u32 dummy1; /* 0x20 */ + u32 cs0wcr; + u32 cs2wcr; + u32 dummy2; /* 0x2c */ + u32 cs4wcr; + u32 cs5awcr; + u32 cs5bwcr; + u32 cs6awcr; + u32 dummy3[5]; /* 0x40 .. 0x50 */ + u32 rbwtcnt; + u32 busycr; + u32 dummy4[5]; /* 0x5c .. 0x6c */ + u32 bromtimcr; + u32 dummy5[7]; /* 0x74 .. 0x8c */ + u32 bptcr00; + u32 bptcr01; + u32 bptcr02; + u32 bptcr03; + u32 bptcr04; + u32 bptcr05; + u32 bptcr06; + u32 bptcr07; + u32 bptcr08; + u32 bptcr09; + u32 bptcr10; + u32 bptcr11; + u32 bptcr12; + u32 bptcr13; + u32 bptcr14; + u32 bptcr15; + u32 bptcr16; + u32 bptcr17; + u32 bptcr18; + u32 bptcr19; + u32 bptcr20; + u32 bptcr21; + u32 bptcr22; + u32 bptcr23; + u32 bptcr24; + u32 bptcr25; + u32 bptcr26; + u32 bptcr27; + u32 bptcr28; + u32 bptcr29; + u32 bptcr30; + u32 bptcr31; + u32 bswcr; + u32 dummy6[68]; /* 0x114 .. 0x220 */ + u32 cs0wcr2; + u32 cs2wcr2; + u32 dummy7; /* 0x22c */ + u32 cs4wcr2; +}; + +#define CS0WCR2 0xFEC10224 +#define CS2WCR2 0xFEC10228 +#define CS4WCR2 0xFEC10230 + +/* DDRP */ +struct r8a7740_ddrp { + u32 funcctrl; + u32 dllctrl; + u32 zqcalctrl; + u32 zqodtctrl; + u32 rdctrl; + u32 rdtmg; + u32 fifoinit; + u32 outctrl; + u32 dummy0[50]; /* 0x20 .. 0xe4 */ + u32 dqcalofs1; + u32 dqcalofs2; + u32 dummy1[2]; /* 0xf0 .. 0xf4 */ + u32 dqcalexp; +}; + +#define DDRPNCNT 0xE605803C +#define DDRVREFCNT 0xE61500EC + +/* DBSC */ +struct r8a7740_dbsc { + u32 dummy0; + u32 dbsvcr; + u32 dbstate0; + u32 dbstate1; + u32 dbacen; + u32 dbrfen; + u32 dbcmd; + u32 dbwait; + u32 dbkind; + u32 dbconf0; + u32 dummy1[2]; /* 0x28 .. 0x2c */ + u32 dbphytype; + u32 dummy2[3]; /* 0x34 .. 0x3c */ + u32 dbtr0; + u32 dbtr1; + u32 dbtr2; + u32 dummy3; /* 0x4c */ + u32 dbtr3; + u32 dbtr4; + u32 dbtr5; + u32 dbtr6; + u32 dbtr7; + u32 dbtr8; + u32 dbtr9; + u32 dbtr10; + u32 dbtr11; + u32 dbtr12; + u32 dbtr13; + u32 dbtr14; + u32 dbtr15; + u32 dbtr16; + u32 dbtr17; + u32 dbtr18; + u32 dbtr19; + u32 dummy4[7]; /* 0x94 .. 0xac */ + u32 dbbl; + u32 dummy5[3]; /* 0xb4 .. 0xbc */ + u32 dbadj0; + u32 dbadj1; + u32 dbadj2; + u32 dummy6[5]; /* 0xcc .. 0xdc */ + u32 dbrfcnf0; + u32 dbrfcnf1; + u32 dbrfcnf2; + u32 dbrfcnf3; + u32 dummy7; /* 0xf0 */ + u32 dbcalcnf; + u32 dbcaltr; + u32 dummy8; /* 0xfc */; + u32 dbrnk0; + u32 dummy9[31]; /* 0x104 .. 0x17C */ + u32 dbpdncnf; + u32 dummy10[7]; /* 0x184 .. 0x19C */ + u32 dbmrrdr; + u32 dummy11[39]; /* 0x1A4 .. 0x23C */ + u32 dbdfistat; + u32 dbdficnt; + u32 dummy12[46]; /* 0x248 .. 0x2FC */ + u32 dbbs0cnt0; + u32 dbbs0cnt1; +}; + +#endif + +#endif /* __ASM_ARCH_R8A7740_H */ diff --git a/arch/arm/include/asm/arch-rmobile/rmobile.h b/arch/arm/include/asm/arch-rmobile/rmobile.h new file mode 100644 index 0000000000..ac175617cd --- /dev/null +++ b/arch/arm/include/asm/arch-rmobile/rmobile.h @@ -0,0 +1,14 @@ +#ifndef __ASM_ARCH_RMOBILE_H +#define __ASM_ARCH_RMOBILE_H + +#if defined(CONFIG_RMOBILE) +#if defined(CONFIG_SH73A0) +#include <asm/arch/sh73a0.h> +#elif defined(CONFIG_R8A7740) +#include <asm/arch/r8a7740.h> +#else +#error "SOC Name not defined" +#endif +#endif /* CONFIG_RMOBILE */ + +#endif /* __ASM_ARCH_RMOBILE_H */ diff --git a/arch/arm/include/asm/arch-rmobile/sh73a0-gpio.h b/arch/arm/include/asm/arch-rmobile/sh73a0-gpio.h new file mode 100644 index 0000000000..398e2c1091 --- /dev/null +++ b/arch/arm/include/asm/arch-rmobile/sh73a0-gpio.h @@ -0,0 +1,553 @@ +#ifndef __ASM_SH73A0_H__ +#define __ASM_SH73A0_H__ + +/* Pin Function Controller: + * GPIO_FN_xx - GPIO used to select pin function and MSEL switch + * GPIO_PORTxx - GPIO mapped to real I/O pin on CPU + */ +enum { + /* Hardware manual Table 25-1 (GPIO) */ + GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4, + GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9, + + GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14, + GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19, + + GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24, + GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29, + + GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34, + GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39, + + GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44, + GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49, + + GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54, + GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59, + + GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64, + GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69, + + GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74, + GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79, + + GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84, + GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89, + + GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94, + GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99, + + GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104, + GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109, + + GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114, + GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118, + + GPIO_PORT128, GPIO_PORT129, + + GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134, + GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139, + + GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144, + GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149, + + GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154, + GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159, + + GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164, + + GPIO_PORT192, GPIO_PORT193, GPIO_PORT194, + GPIO_PORT195, GPIO_PORT196, GPIO_PORT197, GPIO_PORT198, GPIO_PORT199, + + GPIO_PORT200, GPIO_PORT201, GPIO_PORT202, GPIO_PORT203, GPIO_PORT204, + GPIO_PORT205, GPIO_PORT206, GPIO_PORT207, GPIO_PORT208, GPIO_PORT209, + + GPIO_PORT210, GPIO_PORT211, GPIO_PORT212, GPIO_PORT213, GPIO_PORT214, + GPIO_PORT215, GPIO_PORT216, GPIO_PORT217, GPIO_PORT218, GPIO_PORT219, + + GPIO_PORT220, GPIO_PORT221, GPIO_PORT222, GPIO_PORT223, GPIO_PORT224, + GPIO_PORT225, GPIO_PORT226, GPIO_PORT227, GPIO_PORT228, GPIO_PORT229, + + GPIO_PORT230, GPIO_PORT231, GPIO_PORT232, GPIO_PORT233, GPIO_PORT234, + GPIO_PORT235, GPIO_PORT236, GPIO_PORT237, GPIO_PORT238, GPIO_PORT239, + + GPIO_PORT240, GPIO_PORT241, GPIO_PORT242, GPIO_PORT243, GPIO_PORT244, + GPIO_PORT245, GPIO_PORT246, GPIO_PORT247, GPIO_PORT248, GPIO_PORT249, + + GPIO_PORT250, GPIO_PORT251, GPIO_PORT252, GPIO_PORT253, GPIO_PORT254, + GPIO_PORT255, GPIO_PORT256, GPIO_PORT257, GPIO_PORT258, GPIO_PORT259, + + GPIO_PORT260, GPIO_PORT261, GPIO_PORT262, GPIO_PORT263, GPIO_PORT264, + GPIO_PORT265, GPIO_PORT266, GPIO_PORT267, GPIO_PORT268, GPIO_PORT269, + + GPIO_PORT270, GPIO_PORT271, GPIO_PORT272, GPIO_PORT273, GPIO_PORT274, + GPIO_PORT275, GPIO_PORT276, GPIO_PORT277, GPIO_PORT278, GPIO_PORT279, + + GPIO_PORT280, GPIO_PORT281, GPIO_PORT282, + + GPIO_PORT288, GPIO_PORT289, + + GPIO_PORT290, GPIO_PORT291, GPIO_PORT292, GPIO_PORT293, GPIO_PORT294, + GPIO_PORT295, GPIO_PORT296, GPIO_PORT297, GPIO_PORT298, GPIO_PORT299, + + GPIO_PORT300, GPIO_PORT301, GPIO_PORT302, GPIO_PORT303, GPIO_PORT304, + GPIO_PORT305, GPIO_PORT306, GPIO_PORT307, GPIO_PORT308, GPIO_PORT309, + + /* Table 25-1 (Function 0-7) */ + GPIO_FN_VBUS_0, + GPIO_FN_GPI0, + GPIO_FN_GPI1, + GPIO_FN_GPI2, + GPIO_FN_GPI3, + GPIO_FN_GPI4, + GPIO_FN_GPI5, + GPIO_FN_GPI6, + GPIO_FN_GPI7, + GPIO_FN_SCIFA7_RXD, + GPIO_FN_SCIFA7_CTS_, + GPIO_FN_GPO7, GPIO_FN_MFG0_OUT2, + GPIO_FN_GPO6, GPIO_FN_MFG1_OUT2, + GPIO_FN_GPO5, GPIO_FN_SCIFA0_SCK, GPIO_FN_FSICOSLDT3, \ + GPIO_FN_PORT16_VIO_CKOR, + GPIO_FN_SCIFA0_TXD, + GPIO_FN_SCIFA7_TXD, + GPIO_FN_SCIFA7_RTS_, GPIO_FN_PORT19_VIO_CKO2, + GPIO_FN_GPO0, + GPIO_FN_GPO1, + GPIO_FN_GPO2, GPIO_FN_STATUS0, + GPIO_FN_GPO3, GPIO_FN_STATUS1, + GPIO_FN_GPO4, GPIO_FN_STATUS2, + GPIO_FN_VINT, + GPIO_FN_TCKON, + GPIO_FN_XDVFS1, GPIO_FN_PORT27_I2C_SCL2, GPIO_FN_PORT27_I2C_SCL3, \ + GPIO_FN_MFG0_OUT1, GPIO_FN_PORT27_IROUT, + GPIO_FN_XDVFS2, GPIO_FN_PORT28_I2C_SDA2, GPIO_FN_PORT28_I2C_SDA3, \ + GPIO_FN_PORT28_TPU1TO1, + GPIO_FN_SIM_RST, GPIO_FN_PORT29_TPU1TO1, + GPIO_FN_SIM_CLK, GPIO_FN_PORT30_VIO_CKOR, + GPIO_FN_SIM_D, GPIO_FN_PORT31_IROUT, + GPIO_FN_SCIFA4_TXD, + GPIO_FN_SCIFA4_RXD, GPIO_FN_XWUP, + GPIO_FN_SCIFA4_RTS_, + GPIO_FN_SCIFA4_CTS_, + GPIO_FN_FSIBOBT, GPIO_FN_FSIBIBT, + GPIO_FN_FSIBOLR, GPIO_FN_FSIBILR, + GPIO_FN_FSIBOSLD, + GPIO_FN_FSIBISLD, + GPIO_FN_VACK, + GPIO_FN_XTAL1L, + GPIO_FN_SCIFA0_RTS_, GPIO_FN_FSICOSLDT2, + GPIO_FN_SCIFA0_RXD, + GPIO_FN_SCIFA0_CTS_, GPIO_FN_FSICOSLDT1, + GPIO_FN_FSICOBT, GPIO_FN_FSICIBT, GPIO_FN_FSIDOBT, GPIO_FN_FSIDIBT, + GPIO_FN_FSICOLR, GPIO_FN_FSICILR, GPIO_FN_FSIDOLR, GPIO_FN_FSIDILR, + GPIO_FN_FSICOSLD, GPIO_FN_PORT47_FSICSPDIF, + GPIO_FN_FSICISLD, GPIO_FN_FSIDISLD, + GPIO_FN_FSIACK, GPIO_FN_PORT49_IRDA_OUT, GPIO_FN_PORT49_IROUT, \ + GPIO_FN_FSIAOMC, + GPIO_FN_FSIAOLR, GPIO_FN_BBIF2_TSYNC2, GPIO_FN_TPU2TO2, GPIO_FN_FSIAILR, + + GPIO_FN_FSIAOBT, GPIO_FN_BBIF2_TSCK2, GPIO_FN_TPU2TO3, GPIO_FN_FSIAIBT, + GPIO_FN_FSIAOSLD, GPIO_FN_BBIF2_TXD2, + GPIO_FN_FSIASPDIF, GPIO_FN_PORT53_IRDA_IN, GPIO_FN_TPU3TO3, \ + GPIO_FN_FSIBSPDIF, GPIO_FN_PORT53_FSICSPDIF, + GPIO_FN_FSIBCK, GPIO_FN_PORT54_IRDA_FIRSEL, GPIO_FN_TPU3TO2, \ + GPIO_FN_FSIBOMC, GPIO_FN_FSICCK, GPIO_FN_FSICOMC, + GPIO_FN_FSIAISLD, GPIO_FN_TPU0TO0, + GPIO_FN_A0, GPIO_FN_BS_, + GPIO_FN_A12, GPIO_FN_PORT58_KEYOUT7, GPIO_FN_TPU4TO2, + GPIO_FN_A13, GPIO_FN_PORT59_KEYOUT6, GPIO_FN_TPU0TO1, + GPIO_FN_A14, GPIO_FN_KEYOUT5, + GPIO_FN_A15, GPIO_FN_KEYOUT4, + GPIO_FN_A16, GPIO_FN_KEYOUT3, GPIO_FN_MSIOF0_SS1, + GPIO_FN_A17, GPIO_FN_KEYOUT2, GPIO_FN_MSIOF0_TSYNC, + GPIO_FN_A18, GPIO_FN_KEYOUT1, GPIO_FN_MSIOF0_TSCK, + GPIO_FN_A19, GPIO_FN_KEYOUT0, GPIO_FN_MSIOF0_TXD, + GPIO_FN_A20, GPIO_FN_KEYIN0, GPIO_FN_MSIOF0_RSCK, + GPIO_FN_A21, GPIO_FN_KEYIN1, GPIO_FN_MSIOF0_RSYNC, + GPIO_FN_A22, GPIO_FN_KEYIN2, GPIO_FN_MSIOF0_MCK0, + GPIO_FN_A23, GPIO_FN_KEYIN3, GPIO_FN_MSIOF0_MCK1, + GPIO_FN_A24, GPIO_FN_KEYIN4, GPIO_FN_MSIOF0_RXD, + GPIO_FN_A25, GPIO_FN_KEYIN5, GPIO_FN_MSIOF0_SS2, + GPIO_FN_A26, GPIO_FN_KEYIN6, + GPIO_FN_KEYIN7, + GPIO_FN_D0_NAF0, + GPIO_FN_D1_NAF1, + GPIO_FN_D2_NAF2, + GPIO_FN_D3_NAF3, + GPIO_FN_D4_NAF4, + GPIO_FN_D5_NAF5, + GPIO_FN_D6_NAF6, + GPIO_FN_D7_NAF7, + GPIO_FN_D8_NAF8, + GPIO_FN_D9_NAF9, + GPIO_FN_D10_NAF10, + GPIO_FN_D11_NAF11, + GPIO_FN_D12_NAF12, + GPIO_FN_D13_NAF13, + GPIO_FN_D14_NAF14, + GPIO_FN_D15_NAF15, + GPIO_FN_CS4_, + GPIO_FN_CS5A_, GPIO_FN_PORT91_RDWR, + GPIO_FN_CS5B_, GPIO_FN_FCE1_, + GPIO_FN_CS6B_, GPIO_FN_DACK0, + GPIO_FN_FCE0_, GPIO_FN_CS6A_, + GPIO_FN_WAIT_, GPIO_FN_DREQ0, + GPIO_FN_RD__FSC, + GPIO_FN_WE0__FWE, GPIO_FN_RDWR_FWE, + GPIO_FN_WE1_, + GPIO_FN_FRB, + GPIO_FN_CKO, + GPIO_FN_NBRSTOUT_, + GPIO_FN_NBRST_, + GPIO_FN_BBIF2_TXD, + GPIO_FN_BBIF2_RXD, + GPIO_FN_BBIF2_SYNC, + GPIO_FN_BBIF2_SCK, + GPIO_FN_SCIFA3_CTS_, GPIO_FN_MFG3_IN2, + GPIO_FN_SCIFA3_RXD, GPIO_FN_MFG3_IN1, + GPIO_FN_BBIF1_SS2, GPIO_FN_SCIFA3_RTS_, GPIO_FN_MFG3_OUT1, + GPIO_FN_SCIFA3_TXD, + GPIO_FN_HSI_RX_DATA, GPIO_FN_BBIF1_RXD, + GPIO_FN_HSI_TX_WAKE, GPIO_FN_BBIF1_TSCK, + GPIO_FN_HSI_TX_DATA, GPIO_FN_BBIF1_TSYNC, + GPIO_FN_HSI_TX_READY, GPIO_FN_BBIF1_TXD, + GPIO_FN_HSI_RX_READY, GPIO_FN_BBIF1_RSCK, GPIO_FN_PORT115_I2C_SCL2, \ + GPIO_FN_PORT115_I2C_SCL3, + GPIO_FN_HSI_RX_WAKE, GPIO_FN_BBIF1_RSYNC, GPIO_FN_PORT116_I2C_SDA2, \ + GPIO_FN_PORT116_I2C_SDA3, + GPIO_FN_HSI_RX_FLAG, GPIO_FN_BBIF1_SS1, GPIO_FN_BBIF1_FLOW, + GPIO_FN_HSI_TX_FLAG, + GPIO_FN_VIO_VD, GPIO_FN_PORT128_LCD2VSYN, GPIO_FN_VIO2_VD, \ + GPIO_FN_LCD2D0, + + GPIO_FN_VIO_HD, GPIO_FN_PORT129_LCD2HSYN, GPIO_FN_PORT129_LCD2CS_, \ + GPIO_FN_VIO2_HD, GPIO_FN_LCD2D1, + GPIO_FN_VIO_D0, GPIO_FN_PORT130_MSIOF2_RXD, GPIO_FN_LCD2D10, + GPIO_FN_VIO_D1, GPIO_FN_PORT131_KEYOUT6, GPIO_FN_PORT131_MSIOF2_SS1, \ + GPIO_FN_PORT131_KEYOUT11, GPIO_FN_LCD2D11, + GPIO_FN_VIO_D2, GPIO_FN_PORT132_KEYOUT7, GPIO_FN_PORT132_MSIOF2_SS2, \ + GPIO_FN_PORT132_KEYOUT10, GPIO_FN_LCD2D12, + GPIO_FN_VIO_D3, GPIO_FN_MSIOF2_TSYNC, GPIO_FN_LCD2D13, + GPIO_FN_VIO_D4, GPIO_FN_MSIOF2_TXD, GPIO_FN_LCD2D14, + GPIO_FN_VIO_D5, GPIO_FN_MSIOF2_TSCK, GPIO_FN_LCD2D15, + GPIO_FN_VIO_D6, GPIO_FN_PORT136_KEYOUT8, GPIO_FN_LCD2D16, + GPIO_FN_VIO_D7, GPIO_FN_PORT137_KEYOUT9, GPIO_FN_LCD2D17, + GPIO_FN_VIO_D8, GPIO_FN_PORT138_KEYOUT8, GPIO_FN_VIO2_D0, \ + GPIO_FN_LCD2D6, + GPIO_FN_VIO_D9, GPIO_FN_PORT139_KEYOUT9, GPIO_FN_VIO2_D1, \ + GPIO_FN_LCD2D7, + GPIO_FN_VIO_D10, GPIO_FN_TPU0TO2, GPIO_FN_VIO2_D2, GPIO_FN_LCD2D8, + GPIO_FN_VIO_D11, GPIO_FN_TPU0TO3, GPIO_FN_VIO2_D3, GPIO_FN_LCD2D9, + GPIO_FN_VIO_D12, GPIO_FN_PORT142_KEYOUT10, GPIO_FN_VIO2_D4, \ + GPIO_FN_LCD2D2, + GPIO_FN_VIO_D13, GPIO_FN_PORT143_KEYOUT11, GPIO_FN_PORT143_KEYOUT6, \ + GPIO_FN_VIO2_D5, GPIO_FN_LCD2D3, + GPIO_FN_VIO_D14, GPIO_FN_PORT144_KEYOUT7, GPIO_FN_VIO2_D6, \ + GPIO_FN_LCD2D4, + GPIO_FN_VIO_D15, GPIO_FN_TPU1TO3, GPIO_FN_PORT145_LCD2DISP, \ + GPIO_FN_PORT145_LCD2RS, GPIO_FN_VIO2_D7, GPIO_FN_LCD2D5, + GPIO_FN_VIO_CLK, GPIO_FN_LCD2DCK, GPIO_FN_PORT146_LCD2WR_, \ + GPIO_FN_VIO2_CLK, GPIO_FN_LCD2D18, + GPIO_FN_VIO_FIELD, GPIO_FN_LCD2RD_, GPIO_FN_VIO2_FIELD, GPIO_FN_LCD2D19, + GPIO_FN_VIO_CKO, + GPIO_FN_A27, GPIO_FN_PORT149_RDWR, GPIO_FN_MFG0_IN1, \ + GPIO_FN_PORT149_KEYOUT9, + GPIO_FN_MFG0_IN2, + GPIO_FN_TS_SPSYNC3, GPIO_FN_MSIOF2_RSCK, + GPIO_FN_TS_SDAT3, GPIO_FN_MSIOF2_RSYNC, + GPIO_FN_TPU1TO2, GPIO_FN_TS_SDEN3, GPIO_FN_PORT153_MSIOF2_SS1, + GPIO_FN_SCIFA2_TXD1, GPIO_FN_MSIOF2_MCK0, + GPIO_FN_SCIFA2_RXD1, GPIO_FN_MSIOF2_MCK1, + GPIO_FN_SCIFA2_RTS1_, GPIO_FN_PORT156_MSIOF2_SS2, + GPIO_FN_SCIFA2_CTS1_, GPIO_FN_PORT157_MSIOF2_RXD, + GPIO_FN_DINT_, GPIO_FN_SCIFA2_SCK1, GPIO_FN_TS_SCK3, + GPIO_FN_PORT159_SCIFB_SCK, GPIO_FN_PORT159_SCIFA5_SCK, GPIO_FN_NMI, + GPIO_FN_PORT160_SCIFB_TXD, GPIO_FN_PORT160_SCIFA5_TXD, + GPIO_FN_PORT161_SCIFB_CTS_, GPIO_FN_PORT161_SCIFA5_CTS_, + GPIO_FN_PORT162_SCIFB_RXD, GPIO_FN_PORT162_SCIFA5_RXD, + GPIO_FN_PORT163_SCIFB_RTS_, GPIO_FN_PORT163_SCIFA5_RTS_, \ + GPIO_FN_TPU3TO0, + GPIO_FN_LCDD0, + GPIO_FN_LCDD1, GPIO_FN_PORT193_SCIFA5_CTS_, GPIO_FN_BBIF2_TSYNC1, + GPIO_FN_LCDD2, GPIO_FN_PORT194_SCIFA5_RTS_, GPIO_FN_BBIF2_TSCK1, + GPIO_FN_LCDD3, GPIO_FN_PORT195_SCIFA5_RXD, GPIO_FN_BBIF2_TXD1, + GPIO_FN_LCDD4, GPIO_FN_PORT196_SCIFA5_TXD, + GPIO_FN_LCDD5, GPIO_FN_PORT197_SCIFA5_SCK, GPIO_FN_MFG2_OUT2, \ + GPIO_FN_TPU2TO1, + GPIO_FN_LCDD6, + GPIO_FN_LCDD7, GPIO_FN_TPU4TO1, GPIO_FN_MFG4_OUT2, + GPIO_FN_LCDD8, GPIO_FN_D16, + GPIO_FN_LCDD9, GPIO_FN_D17, + GPIO_FN_LCDD10, GPIO_FN_D18, + GPIO_FN_LCDD11, GPIO_FN_D19, + GPIO_FN_LCDD12, GPIO_FN_D20, + GPIO_FN_LCDD13, GPIO_FN_D21, + GPIO_FN_LCDD14, GPIO_FN_D22, + GPIO_FN_LCDD15, GPIO_FN_PORT207_MSIOF0L_SS1, GPIO_FN_D23, + GPIO_FN_LCDD16, GPIO_FN_PORT208_MSIOF0L_SS2, GPIO_FN_D24, + GPIO_FN_LCDD17, GPIO_FN_D25, + GPIO_FN_LCDD18, GPIO_FN_DREQ2, GPIO_FN_PORT210_MSIOF0L_SS1, GPIO_FN_D26, + GPIO_FN_LCDD19, GPIO_FN_PORT211_MSIOF0L_SS2, GPIO_FN_D27, + GPIO_FN_LCDD20, GPIO_FN_TS_SPSYNC1, GPIO_FN_MSIOF0L_MCK0, GPIO_FN_D28, + GPIO_FN_LCDD21, GPIO_FN_TS_SDAT1, GPIO_FN_MSIOF0L_MCK1, GPIO_FN_D29, + GPIO_FN_LCDD22, GPIO_FN_TS_SDEN1, GPIO_FN_MSIOF0L_RSCK, GPIO_FN_D30, + GPIO_FN_LCDD23, GPIO_FN_TS_SCK1, GPIO_FN_MSIOF0L_RSYNC, GPIO_FN_D31, + GPIO_FN_LCDDCK, GPIO_FN_LCDWR_, + GPIO_FN_LCDRD_, GPIO_FN_DACK2, GPIO_FN_PORT217_LCD2RS, \ + GPIO_FN_MSIOF0L_TSYNC, GPIO_FN_VIO2_FIELD3, GPIO_FN_PORT217_LCD2DISP, + GPIO_FN_LCDHSYN, GPIO_FN_LCDCS_, GPIO_FN_LCDCS2_, GPIO_FN_DACK3, \ + GPIO_FN_PORT218_VIO_CKOR, + GPIO_FN_LCDDISP, GPIO_FN_LCDRS, GPIO_FN_PORT219_LCD2WR_, \ + GPIO_FN_DREQ3, GPIO_FN_MSIOF0L_TSCK, GPIO_FN_VIO2_CLK3, \ + GPIO_FN_LCD2DCK_2, + GPIO_FN_LCDVSYN, GPIO_FN_LCDVSYN2, + GPIO_FN_LCDLCLK, GPIO_FN_DREQ1, GPIO_FN_PORT221_LCD2CS_, \ + GPIO_FN_PWEN, GPIO_FN_MSIOF0L_RXD, GPIO_FN_VIO2_HD3, \ + GPIO_FN_PORT221_LCD2HSYN, + GPIO_FN_LCDDON, GPIO_FN_LCDDON2, GPIO_FN_DACK1, GPIO_FN_OVCN, \ + GPIO_FN_MSIOF0L_TXD, GPIO_FN_VIO2_VD3, GPIO_FN_PORT222_LCD2VSYN, + + GPIO_FN_SCIFA1_TXD, GPIO_FN_OVCN2, + GPIO_FN_EXTLP, GPIO_FN_SCIFA1_SCK, GPIO_FN_PORT226_VIO_CKO2, + GPIO_FN_SCIFA1_RTS_, GPIO_FN_IDIN, + GPIO_FN_SCIFA1_RXD, + GPIO_FN_SCIFA1_CTS_, GPIO_FN_MFG1_IN1, + GPIO_FN_MSIOF1_TXD, GPIO_FN_SCIFA2_TXD2, + GPIO_FN_MSIOF1_TSYNC, GPIO_FN_SCIFA2_CTS2_, + GPIO_FN_MSIOF1_TSCK, GPIO_FN_SCIFA2_SCK2, + GPIO_FN_MSIOF1_RXD, GPIO_FN_SCIFA2_RXD2, + GPIO_FN_MSIOF1_RSCK, GPIO_FN_SCIFA2_RTS2_, GPIO_FN_VIO2_CLK2, \ + GPIO_FN_LCD2D20, + GPIO_FN_MSIOF1_RSYNC, GPIO_FN_MFG1_IN2, GPIO_FN_VIO2_VD2, \ + GPIO_FN_LCD2D21, + GPIO_FN_MSIOF1_MCK0, GPIO_FN_PORT236_I2C_SDA2, + GPIO_FN_MSIOF1_MCK1, GPIO_FN_PORT237_I2C_SCL2, + GPIO_FN_MSIOF1_SS1, GPIO_FN_VIO2_FIELD2, GPIO_FN_LCD2D22, + GPIO_FN_MSIOF1_SS2, GPIO_FN_VIO2_HD2, GPIO_FN_LCD2D23, + GPIO_FN_SCIFA6_TXD, + GPIO_FN_PORT241_IRDA_OUT, GPIO_FN_PORT241_IROUT, GPIO_FN_MFG4_OUT1, \ + GPIO_FN_TPU4TO0, + GPIO_FN_PORT242_IRDA_IN, GPIO_FN_MFG4_IN2, + GPIO_FN_PORT243_IRDA_FIRSEL, GPIO_FN_PORT243_VIO_CKO2, + GPIO_FN_PORT244_SCIFA5_CTS_, GPIO_FN_MFG2_IN1, \ + GPIO_FN_PORT244_SCIFB_CTS_, GPIO_FN_MSIOF2R_RXD, + GPIO_FN_PORT245_SCIFA5_RTS_, GPIO_FN_MFG2_IN2, \ + GPIO_FN_PORT245_SCIFB_RTS_, GPIO_FN_MSIOF2R_TXD, + GPIO_FN_PORT246_SCIFA5_RXD, GPIO_FN_MFG1_OUT1, \ + GPIO_FN_PORT246_SCIFB_RXD, GPIO_FN_TPU1TO0, + GPIO_FN_PORT247_SCIFA5_TXD, GPIO_FN_MFG3_OUT2, \ + GPIO_FN_PORT247_SCIFB_TXD, GPIO_FN_TPU3TO1, + GPIO_FN_PORT248_SCIFA5_SCK, GPIO_FN_MFG2_OUT1, \ + GPIO_FN_PORT248_SCIFB_SCK, GPIO_FN_TPU2TO0, \ + GPIO_FN_PORT248_I2C_SCL3, GPIO_FN_MSIOF2R_TSCK, + GPIO_FN_PORT249_IROUT, GPIO_FN_MFG4_IN1, \ + GPIO_FN_PORT249_I2C_SDA3, GPIO_FN_MSIOF2R_TSYNC, + GPIO_FN_SDHICLK0, + GPIO_FN_SDHICD0, + GPIO_FN_SDHID0_0, + GPIO_FN_SDHID0_1, + GPIO_FN_SDHID0_2, + GPIO_FN_SDHID0_3, + GPIO_FN_SDHICMD0, + GPIO_FN_SDHIWP0, + GPIO_FN_SDHICLK1, + GPIO_FN_SDHID1_0, GPIO_FN_TS_SPSYNC2, + GPIO_FN_SDHID1_1, GPIO_FN_TS_SDAT2, + GPIO_FN_SDHID1_2, GPIO_FN_TS_SDEN2, + GPIO_FN_SDHID1_3, GPIO_FN_TS_SCK2, + GPIO_FN_SDHICMD1, + GPIO_FN_SDHICLK2, + GPIO_FN_SDHID2_0, GPIO_FN_TS_SPSYNC4, + GPIO_FN_SDHID2_1, GPIO_FN_TS_SDAT4, + GPIO_FN_SDHID2_2, GPIO_FN_TS_SDEN4, + GPIO_FN_SDHID2_3, GPIO_FN_TS_SCK4, + GPIO_FN_SDHICMD2, + GPIO_FN_MMCCLK0, + GPIO_FN_MMCD0_0, + GPIO_FN_MMCD0_1, + GPIO_FN_MMCD0_2, + GPIO_FN_MMCD0_3, + GPIO_FN_MMCD0_4, GPIO_FN_TS_SPSYNC5, + GPIO_FN_MMCD0_5, GPIO_FN_TS_SDAT5, + GPIO_FN_MMCD0_6, GPIO_FN_TS_SDEN5, + GPIO_FN_MMCD0_7, GPIO_FN_TS_SCK5, + GPIO_FN_MMCCMD0, + GPIO_FN_RESETOUTS_, GPIO_FN_EXTAL2OUT, + GPIO_FN_MCP_WAIT__MCP_FRB, + GPIO_FN_MCP_CKO, GPIO_FN_MMCCLK1, + GPIO_FN_MCP_D15_MCP_NAF15, + GPIO_FN_MCP_D14_MCP_NAF14, + GPIO_FN_MCP_D13_MCP_NAF13, + GPIO_FN_MCP_D12_MCP_NAF12, + GPIO_FN_MCP_D11_MCP_NAF11, + GPIO_FN_MCP_D10_MCP_NAF10, + GPIO_FN_MCP_D9_MCP_NAF9, + GPIO_FN_MCP_D8_MCP_NAF8, GPIO_FN_MMCCMD1, + GPIO_FN_MCP_D7_MCP_NAF7, GPIO_FN_MMCD1_7, + + GPIO_FN_MCP_D6_MCP_NAF6, GPIO_FN_MMCD1_6, + GPIO_FN_MCP_D5_MCP_NAF5, GPIO_FN_MMCD1_5, + GPIO_FN_MCP_D4_MCP_NAF4, GPIO_FN_MMCD1_4, + GPIO_FN_MCP_D3_MCP_NAF3, GPIO_FN_MMCD1_3, + GPIO_FN_MCP_D2_MCP_NAF2, GPIO_FN_MMCD1_2, + GPIO_FN_MCP_D1_MCP_NAF1, GPIO_FN_MMCD1_1, + GPIO_FN_MCP_D0_MCP_NAF0, GPIO_FN_MMCD1_0, + GPIO_FN_MCP_NBRSTOUT_, + GPIO_FN_MCP_WE0__MCP_FWE, GPIO_FN_MCP_RDWR_MCP_FWE, + + /* MSEL2 special case */ + GPIO_FN_TSIF2_TS_XX1, + GPIO_FN_TSIF2_TS_XX2, + GPIO_FN_TSIF2_TS_XX3, + GPIO_FN_TSIF2_TS_XX4, + GPIO_FN_TSIF2_TS_XX5, + GPIO_FN_TSIF1_TS_XX1, + GPIO_FN_TSIF1_TS_XX2, + GPIO_FN_TSIF1_TS_XX3, + GPIO_FN_TSIF1_TS_XX4, + GPIO_FN_TSIF1_TS_XX5, + GPIO_FN_TSIF0_TS_XX1, + GPIO_FN_TSIF0_TS_XX2, + GPIO_FN_TSIF0_TS_XX3, + GPIO_FN_TSIF0_TS_XX4, + GPIO_FN_TSIF0_TS_XX5, + GPIO_FN_MST1_TS_XX1, + GPIO_FN_MST1_TS_XX2, + GPIO_FN_MST1_TS_XX3, + GPIO_FN_MST1_TS_XX4, + GPIO_FN_MST1_TS_XX5, + GPIO_FN_MST0_TS_XX1, + GPIO_FN_MST0_TS_XX2, + GPIO_FN_MST0_TS_XX3, + GPIO_FN_MST0_TS_XX4, + GPIO_FN_MST0_TS_XX5, + + /* MSEL3 special cases */ + GPIO_FN_SDHI0_VCCQ_MC0_ON, + GPIO_FN_SDHI0_VCCQ_MC0_OFF, + GPIO_FN_DEBUG_MON_VIO, + GPIO_FN_DEBUG_MON_LCDD, + GPIO_FN_LCDC_LCDC0, + GPIO_FN_LCDC_LCDC1, + + /* MSEL4 special cases */ + GPIO_FN_IRQ9_MEM_INT, + GPIO_FN_IRQ9_MCP_INT, + GPIO_FN_A11, + GPIO_FN_KEYOUT8, + GPIO_FN_TPU4TO3, + GPIO_FN_RESETA_N_PU_ON, + GPIO_FN_RESETA_N_PU_OFF, + GPIO_FN_EDBGREQ_PD, + GPIO_FN_EDBGREQ_PU, + + /* Functions with pull-ups */ + GPIO_FN_KEYIN0_PU, + GPIO_FN_KEYIN1_PU, + GPIO_FN_KEYIN2_PU, + GPIO_FN_KEYIN3_PU, + GPIO_FN_KEYIN4_PU, + GPIO_FN_KEYIN5_PU, + GPIO_FN_KEYIN6_PU, + GPIO_FN_KEYIN7_PU, + GPIO_FN_SDHICD0_PU, + GPIO_FN_SDHID0_0_PU, + GPIO_FN_SDHID0_1_PU, + GPIO_FN_SDHID0_2_PU, + GPIO_FN_SDHID0_3_PU, + GPIO_FN_SDHICMD0_PU, + GPIO_FN_SDHIWP0_PU, + GPIO_FN_SDHID1_0_PU, + GPIO_FN_SDHID1_1_PU, + GPIO_FN_SDHID1_2_PU, + GPIO_FN_SDHID1_3_PU, + GPIO_FN_SDHICMD1_PU, + GPIO_FN_SDHID2_0_PU, + GPIO_FN_SDHID2_1_PU, + GPIO_FN_SDHID2_2_PU, + GPIO_FN_SDHID2_3_PU, + GPIO_FN_SDHICMD2_PU, + GPIO_FN_MMCCMD0_PU, + GPIO_FN_MMCCMD1_PU, + GPIO_FN_MMCD0_0_PU, + GPIO_FN_MMCD0_1_PU, + GPIO_FN_MMCD0_2_PU, + GPIO_FN_MMCD0_3_PU, + GPIO_FN_MMCD0_4_PU, + GPIO_FN_MMCD0_5_PU, + GPIO_FN_MMCD0_6_PU, + GPIO_FN_MMCD0_7_PU, + GPIO_FN_FSIACK_PU, + GPIO_FN_FSIAILR_PU, + GPIO_FN_FSIAIBT_PU, + GPIO_FN_FSIAISLD_PU, + + /* end of GPIO */ + GPIO_NR, +}; + +/* DMA slave IDs */ +enum { + SHDMA_SLAVE_INVALID, + SHDMA_SLAVE_SCIF0_TX, + SHDMA_SLAVE_SCIF0_RX, + SHDMA_SLAVE_SCIF1_TX, + SHDMA_SLAVE_SCIF1_RX, + SHDMA_SLAVE_SCIF2_TX, + SHDMA_SLAVE_SCIF2_RX, + SHDMA_SLAVE_SCIF3_TX, + SHDMA_SLAVE_SCIF3_RX, + SHDMA_SLAVE_SCIF4_TX, + SHDMA_SLAVE_SCIF4_RX, + SHDMA_SLAVE_SCIF5_TX, + SHDMA_SLAVE_SCIF5_RX, + SHDMA_SLAVE_SCIF6_TX, + SHDMA_SLAVE_SCIF6_RX, + SHDMA_SLAVE_SCIF7_TX, + SHDMA_SLAVE_SCIF7_RX, + SHDMA_SLAVE_SCIF8_TX, + SHDMA_SLAVE_SCIF8_RX, + SHDMA_SLAVE_SDHI0_TX, + SHDMA_SLAVE_SDHI0_RX, + SHDMA_SLAVE_SDHI1_TX, + SHDMA_SLAVE_SDHI1_RX, + SHDMA_SLAVE_SDHI2_TX, + SHDMA_SLAVE_SDHI2_RX, + SHDMA_SLAVE_MMCIF_TX, + SHDMA_SLAVE_MMCIF_RX, +}; + +/* + * SH73A0 IRQ LOCATION TABLE + * + * 416 ----------------------------------------- + * IRQ0-IRQ15 + * 431 ----------------------------------------- + * ... + * 448 ----------------------------------------- + * sh73a0-intcs + * sh73a0-intca-irq-pins + * 680 ----------------------------------------- + * ... + * 700 ----------------------------------------- + * sh73a0-pint0 + * 731 ----------------------------------------- + * 732 ----------------------------------------- + * sh73a0-pint1 + * 739 ----------------------------------------- + * ... + * 800 ----------------------------------------- + * IRQ16-IRQ31 + * 815 ----------------------------------------- + * ... + * 928 ----------------------------------------- + * sh73a0-intca-irq-pins + * 943 ----------------------------------------- + */ + +/* PINT interrupts are located at Linux IRQ 700 and up */ +#define SH73A0_PINT0_IRQ(irq) ((irq) + 700) +#define SH73A0_PINT1_IRQ(irq) ((irq) + 732) + +#endif /* __ASM_SH73A0_H__ */ diff --git a/arch/arm/include/asm/arch-rmobile/sh73a0.h b/arch/arm/include/asm/arch-rmobile/sh73a0.h new file mode 100644 index 0000000000..bdbb408642 --- /dev/null +++ b/arch/arm/include/asm/arch-rmobile/sh73a0.h @@ -0,0 +1,289 @@ +#ifndef __ASM_ARCH_RMOBILE_SH73A0_H +#define __ASM_ARCH_RMOBILE_SH73A0_H + +/* Global Timer */ +#define GLOBAL_TIMER_BASE_ADDR (0xF0000200) +#define MERAM_BASE (0xE5580000) + +/* GIC */ +#define GIC_BASE (0xF0000100) +#define ICCICR GIC_BASE + +/* Secure control register */ +#define LIFEC_SEC_SRC (0xE6110008) + +/* RWDT */ +#define RWDT_BASE (0xE6020000) + +/* HPB Semaphore Control Registers */ +#define HPB_BASE (0xE6001010) + +/* Bus Semaphore Control Registers */ +#define HPBSCR_BASE (0xE6001600) + +/* SBSC1 */ +#define SBSC1_BASE (0xFE400000) +#define SDMRA1A (SBSC1_BASE + 0x100000) +#define SDMRA2A (SBSC1_BASE + 0x1C0000) +#define SDMRA3A (SBSC1_BASE + 0x104000) + +/* SBSC2 */ +#define SBSC2_BASE (0xFB400000) +#define SDMRA1B (SBSC2_BASE + 0x100000) +#define SDMRA2B (SBSC2_BASE + 0x1C0000) +#define SDMRA3B (SBSC2_BASE + 0x104000) + +/* CPG */ +#define CPG_BASE (0xE6150000) +#define CPG_SRCR_BASE (CPG_BASE + 0x80A0) +#define WUPCR (CPG_BASE + 0x1010) +#define SRESCR (CPG_BASE + 0x1018) +#define PCLKCR (CPG_BASE + 0x1020) + +/* SYSC */ +#define SYSC_BASE (0xE6180000) +#define RESCNT2 (SYSC_BASE + 0x8020) + +/* BSC */ +#define BSC_BASE (0xFEC10000) + +/* SCIF */ +#define SCIF0_BASE (0xE6C40000) +#define SCIF1_BASE (0xE6C50000) +#define SCIF2_BASE (0xE6C60000) +#define SCIF3_BASE (0xE6C70000) +#define SCIF4_BASE (0xE6C80000) +#define SCIF5_BASE (0xE6CB0000) +#define SCIF6_BASE (0xE6CC0000) +#define SCIF7_BASE (0xE6CD0000) + +#ifndef __ASSEMBLY__ +#include <asm/types.h> + +/* RWDT */ +struct sh73a0_rwdt { + u16 rwtcnt0; /* 0x00 */ + u16 dummy0; /* 0x02 */ + u16 rwtcsra0; /* 0x04 */ + u16 dummy1; /* 0x06 */ + u16 rwtcsrb0; /* 0x08 */ +}; + +/* HPB Semaphore Control Registers */ +struct sh73a0_hpb { + u32 hpbctrl0; + u32 hpbctrl1; + u32 hpbctrl2; + u32 cccr; + u32 dummy0; /* 0x20 */ + u32 hpbctrl4; + u32 hpbctrl5; + u32 dummy1; /* 0x2C */ + u32 hpbctrl6; +}; + +/* Bus Semaphore Control Registers */ +struct sh73a0_hpb_bscr { + u32 mpsrc; /* 0x00 */ + u32 mpacctl; /* 0x04 */ + u32 dummy0[6]; + u32 smgpiosrc; /* 0x20 */ + u32 smgpioerr; + u32 smgpiotime; + u32 smgpiocnt; + u32 dummy1[4]; /* 0x30 .. 0x3C */ + u32 smcmt2src; + u32 smcmt2err; + u32 smcmt2time; + u32 smcmt2cnt; + u32 smcpgsrc; + u32 smcpgerr; + u32 smcpgtime; + u32 smcpgcnt; + u32 dummy2[4]; /* 0x60 - 0x6C */ + u32 smsyscsrc; + u32 smsyscerr; + u32 smsysctime; + u32 smsysccnt; +}; + +/* SBSC */ +struct sh73a0_sbsc { + u32 dummy0[2]; /* 0x00, 0x04 */ + u32 sdcr0; + u32 sdcr1; + u32 sdpcr; + u32 dummy1; /* 0x14 */ + u32 sdcr0s; + u32 sdcr1s; + u32 rtcsr; + u32 dummy2; /* 0x24 */ + u32 rtcor; + u32 rtcorh; + u32 rtcors; + u32 rtcorsh; + u32 dummy3[2]; /* 0x38, 0x3C */ + u32 sdwcrc0; + u32 sdwcrc1; + u32 sdwcr00; + u32 sdwcr01; + u32 sdwcr10; + u32 sdwcr11; + u32 sdpdcr0; + u32 dummy4; /* 0x5C */ + u32 sdwcr2; + u32 sdwcrc2; + u32 zqccr; + u32 dummy5[6]; /* 0x6C .. 0x80 */ + u32 sdmracr0; + u32 dummy6; /* 0x88 */ + u32 sdmrtmpcr; + u32 dummy7; /* 0x90 */ + u32 sdmrtmpmsk; + u32 dummy8; /* 0x98 */ + u32 sdgencnt; + u32 dphycnt0; + u32 dphycnt1; + u32 dphycnt2; + u32 dummy9[2]; /* 0xAC .. 0xB0 */ + u32 sddrvcr0; + u32 dummy10[14]; /* 0xB8 .. 0xEC */ + u32 dptdivcr0; + u32 dptdivcr1; + u32 dptdivcr2; + u32 dummy11; /* 0xFC */ + u32 sdptcr0; + u32 sdptcr1; + u32 sdptcr2; + u32 sdptcr3; /* 0x10C */ + u32 dummy12[145]; /* 0x110 .. 0x350 */ + u32 dllcnt0; /* 0x354 */ + u32 sbscmon0; +}; + +/* CPG */ +struct sh73a0_sbsc_cpg { + u32 frqcra; /* 0x00 */ + u32 frqcrb; + u32 vclkcr1; + u32 vclkcr2; + u32 zbckcr; + u32 flckcr; + u32 fsiackcr; + u32 vclkcr3; + u32 rtstbcr; + u32 systbcr; + u32 pll1cr; + u32 pll2cr; + u32 mstpsr0; + u32 dummy0; /* 0x34 */ + u32 mstpsr1; + u32 mstpsr5; + u32 mstpsr2; + u32 dummy1; /* 0x44 */ + u32 mstpsr3; + u32 mstpsr4; + u32 dummy2; /* 0x50 */ + u32 astat; + u32 dvfscr0; + u32 dvfscr1; + u32 dsitckcr; + u32 dsi0pckcr; + u32 dsi1pckcr; + u32 dsi0phycr; + u32 dsi1phycr; + u32 sd0ckcr; + u32 sd1ckcr; + u32 sd2ckcr; + u32 subckcr; + u32 spuackcr; + u32 msuckcr; + u32 hsickcr; + u32 fsibckcr; + u32 spuvckcr; + u32 mfck1cr; + u32 mfck2cr; + u32 dummy3[8]; /* 0xA0 .. 0xBC */ + u32 ckscr; + u32 dummy4; /* 0xC4 */ + u32 pll1stpcr; + u32 mpmode; + u32 pllecr; + u32 dummy5; /* 0xD4 */ + u32 pll0cr; + u32 pll3cr; + u32 dummy6; /* 0xE0 */ + u32 frqcrd; + u32 dummyi7; /* 0xE8 */ + u32 vrefcr; + u32 pll0stpcr; + u32 dummy8; /* 0xF4 */ + u32 pll2stpcr; + u32 pll3stpcr; + u32 dummy9[4]; /* 0x100 .. 0x10c */ + u32 rmstpcr0; + u32 rmstpcr1; + u32 rmstpcr2; + u32 rmstpcr3; + u32 rmstpcr4; + u32 rmstpcr5; + u32 dummy10[2]; /* 0x128 .. 0x12c */ + u32 smstpcr0; + u32 smstpcr1; + u32 smstpcr2; + u32 smstpcr3; + u32 smstpcr4; + u32 smstpcr5; + u32 dummy11[2]; /* 0x148 .. 0x14c */ + u32 cpgxxcs4; + u32 dummy12[7]; /* 0x154 .. 0x16c */ + u32 dvfscr2; + u32 dvfscr3; + u32 dvfscr4; + u32 dvfscr5; /* 0x17C */ +}; + +/* CPG SRCR part OK */ +struct sh73a0_sbsc_cpg_srcr { + u32 srcr0; + u32 dummy0; /* 0xA4 */ + u32 srcr1; + u32 dummy1; /* 0xAC */ + u32 srcr2; + u32 dummy2; /* 0xB4 */ + u32 srcr3; + u32 srcr4; + u32 dummy3; /* 0xC0 */ + u32 srcr5; +}; + +/* BSC */ +struct sh73a0_bsc { + u32 cmncr; + u32 cs0bcr; + u32 cs2bcr; + u32 dummy0; /* 0x0C */ + u32 cs4bcr; + u32 cs5abcr; + u32 cs5bbcr; + u32 cs6abcr; + u32 cs6bbcr; + u32 cs0wcr; + u32 cs2wcr; + u32 dummy1; /* 0x2C */ + u32 cs4wcr; + u32 cs5awcr; + u32 cs5bwcr; + u32 cs6awcr; + u32 cs6bwcr; + u32 rbwtcnt; + u32 busycr; + u32 dummy2; /* 0x5c */ + u32 cs7abcr; + u32 cs7awcr; + u32 dummy3[2]; /* 0x68, 0x6C */ + u32 bromtimcr; +}; +#endif /* __ASSEMBLY__ */ + +#endif /* __ASM_ARCH_RMOBILE_SH73A0_H */ diff --git a/arch/arm/include/asm/arch-rmobile/sys_proto.h b/arch/arm/include/asm/arch-rmobile/sys_proto.h new file mode 100644 index 0000000000..fad4e4e784 --- /dev/null +++ b/arch/arm/include/asm/arch-rmobile/sys_proto.h @@ -0,0 +1,29 @@ +/* + * (C) Copyright 2010 + * Texas Instruments, <www.ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _SYS_PROTO_H_ +#define _SYS_PROTO_H_ + +struct rmobile_sysinfo { + char *board_string; +}; +extern const struct rmobile_sysinfo sysinfo; + +#endif diff --git a/arch/arm/include/asm/arch-s3c24x0/gpio.h b/arch/arm/include/asm/arch-s3c24x0/gpio.h new file mode 100644 index 0000000000..76bc52cb57 --- /dev/null +++ b/arch/arm/include/asm/arch-s3c24x0/gpio.h @@ -0,0 +1,171 @@ +/* + * Copyright (c) 2012. + * + * Gabriel Huau <contact@huau-gabriel.fr> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _S3C24X0_GPIO_H_ +#define _S3C24X0_GPIO_H_ + +enum s3c2440_gpio { + GPA0, + GPA1, + GPA2, + GPA3, + GPA4, + GPA5, + GPA6, + GPA7, + GPA8, + GPA9, + GPA10, + GPA11, + GPA12, + GPA13, + GPA14, + GPA15, + GPA16, + GPA17, + GPA18, + GPA19, + GPA20, + GPA21, + GPA22, + GPA23, + GPA24, + + GPB0 = 32, + GPB1, + GPB2, + GPB3, + GPB4, + GPB5, + GPB6, + GPB7, + GPB8, + GPB9, + GPB10, + + GPC0 = 64, + GPC1, + GPC2, + GPC3, + GPC4, + GPC5, + GPC6, + GPC7, + GPC8, + GPC9, + GPC10, + GPC11, + GPC12, + GPC13, + GPC14, + GPC15, + + GPD0 = 96, + GPD1, + GPD2, + GPD3, + GPD4, + GPD5, + GPD6, + GPD7, + GPD8, + GPD9, + GPD10, + GPD11, + GPD12, + GPD13, + GPD14, + GPD15, + + GPE0 = 128, + GPE1, + GPE2, + GPE3, + GPE4, + GPE5, + GPE6, + GPE7, + GPE8, + GPE9, + GPE10, + GPE11, + GPE12, + GPE13, + GPE14, + GPE15, + + GPF0 = 160, + GPF1, + GPF2, + GPF3, + GPF4, + GPF5, + GPF6, + GPF7, + + GPG0 = 192, + GPG1, + GPG2, + GPG3, + GPG4, + GPG5, + GPG6, + GPG7, + GPG8, + GPG9, + GPG10, + GPG11, + GPG12, + GPG13, + GPG14, + GPG15, + + GPH0 = 224, + GPH1, + GPH2, + GPH3, + GPH4, + GPH5, + GPH6, + GPH7, + GPH8, + GPH9, + GPH10, + + GPJ0 = 256, + GPJ1, + GPJ2, + GPJ3, + GPJ4, + GPJ5, + GPJ6, + GPJ7, + GPJ8, + GPJ9, + GPJ10, + GPJ11, + GPJ12, +}; + +#endif diff --git a/arch/arm/include/asm/arch-s3c24x0/iomux.h b/arch/arm/include/asm/arch-s3c24x0/iomux.h new file mode 100644 index 0000000000..cc22de749e --- /dev/null +++ b/arch/arm/include/asm/arch-s3c24x0/iomux.h @@ -0,0 +1,200 @@ +/* + * Copyright (c) 2012 + * + * Gabriel Huau <contact@huau-gabriel.fr> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _S3C24X0_IOMUX_H_ +#define _S3C24X0_IOMUX_H_ + +enum s3c2440_iomux_func { + /* PORT A */ + IOMUXA_ADDR0 = 1, + IOMUXA_ADDR16 = (1 << 1), + IOMUXA_ADDR17 = (1 << 2), + IOMUXA_ADDR18 = (1 << 3), + IOMUXA_ADDR19 = (1 << 4), + IOMUXA_ADDR20 = (1 << 5), + IOMUXA_ADDR21 = (1 << 6), + IOMUXA_ADDR22 = (1 << 7), + IOMUXA_ADDR23 = (1 << 8), + IOMUXA_ADDR24 = (1 << 9), + IOMUXA_ADDR25 = (1 << 10), + IOMUXA_ADDR26 = (1 << 11), + IOMUXA_nGCS1 = (1 << 12), + IOMUXA_nGCS2 = (1 << 13), + IOMUXA_nGCS3 = (1 << 14), + IOMUXA_nGCS4 = (1 << 15), + IOMUXA_nGCS5 = (1 << 16), + IOMUXA_CLE = (1 << 17), + IOMUXA_ALE = (1 << 18), + IOMUXA_nFWE = (1 << 19), + IOMUXA_nFRE = (1 << 20), + IOMUXA_nRSTOUT = (1 << 21), + IOMUXA_nFCE = (1 << 22), + + /* PORT B */ + IOMUXB_nXDREQ0 = (2 << 20), + IOMUXB_nXDACK0 = (2 << 18), + IOMUXB_nXDREQ1 = (2 << 16), + IOMUXB_nXDACK1 = (2 << 14), + IOMUXB_nXBREQ = (2 << 12), + IOMUXB_nXBACK = (2 << 10), + IOMUXB_TCLK0 = (2 << 8), + IOMUXB_TOUT3 = (2 << 6), + IOMUXB_TOUT2 = (2 << 4), + IOMUXB_TOUT1 = (2 << 2), + IOMUXB_TOUT0 = 2, + + /* PORT C */ + IOMUXC_VS7 = (2 << 30), + IOMUXC_VS6 = (2 << 28), + IOMUXC_VS5 = (2 << 26), + IOMUXC_VS4 = (2 << 24), + IOMUXC_VS3 = (2 << 22), + IOMUXC_VS2 = (2 << 20), + IOMUXC_VS1 = (2 << 18), + IOMUXC_VS0 = (2 << 16), + IOMUXC_LCD_LPCREVB = (2 << 14), + IOMUXC_LCD_LPCREV = (2 << 12), + IOMUXC_LCD_LPCOE = (2 << 10), + IOMUXC_VM = (2 << 8), + IOMUXC_VFRAME = (2 << 6), + IOMUXC_VLINE = (2 << 4), + IOMUXC_VCLK = (2 << 2), + IOMUXC_LEND = 2, + IOMUXC_I2SSDI = (3 << 8), + + /* PORT D */ + IOMUXD_VS23 = (2 << 30), + IOMUXD_VS22 = (2 << 28), + IOMUXD_VS21 = (2 << 26), + IOMUXD_VS20 = (2 << 24), + IOMUXD_VS19 = (2 << 22), + IOMUXD_VS18 = (2 << 20), + IOMUXD_VS17 = (2 << 18), + IOMUXD_VS16 = (2 << 16), + IOMUXD_VS15 = (2 << 14), + IOMUXD_VS14 = (2 << 12), + IOMUXD_VS13 = (2 << 10), + IOMUXD_VS12 = (2 << 8), + IOMUXD_VS11 = (2 << 6), + IOMUXD_VS10 = (2 << 4), + IOMUXD_VS9 = (2 << 2), + IOMUXD_VS8 = 2, + IOMUXD_nSS0 = (3 << 30), + IOMUXD_nSS1 = (3 << 28), + IOMUXD_SPICLK1 = (3 << 20), + IOMUXD_SPIMOSI1 = (3 << 18), + IOMUXD_SPIMISO1 = (3 << 16), + + /* PORT E */ + IOMUXE_IICSDA = (2 << 30), + IOMUXE_IICSCL = (2 << 28), + IOMUXE_SPICLK0 = (2 << 26), + IOMUXE_SPIMOSI0 = (2 << 24), + IOMUXE_SPIMISO0 = (2 << 22), + IOMUXE_SDDAT3 = (2 << 20), + IOMUXE_SDDAT2 = (2 << 18), + IOMUXE_SDDAT1 = (2 << 16), + IOMUXE_SDDAT0 = (2 << 14), + IOMUXE_SDCMD = (2 << 12), + IOMUXE_SDCLK = (2 << 10), + IOMUXE_I2SDO = (2 << 8), + IOMUXE_I2SDI = (2 << 6), + IOMUXE_CDCLK = (2 << 4), + IOMUXE_I2SSCLK = (2 << 2), + IOMUXE_I2SLRCK = 2, + IOMUXE_AC_SDATA_OUT = (3 << 8), + IOMUXE_AC_SDATA_IN = (3 << 6), + IOMUXE_AC_nRESET = (3 << 4), + IOMUXE_AC_BIT_CLK = (3 << 2), + IOMUXE_AC_SYNC = 3, + + /* PORT F */ + IOMUXF_EINT7 = (2 << 14), + IOMUXF_EINT6 = (2 << 12), + IOMUXF_EINT5 = (2 << 10), + IOMUXF_EINT4 = (2 << 8), + IOMUXF_EINT3 = (2 << 6), + IOMUXF_EINT2 = (2 << 4), + IOMUXF_EINT1 = (2 << 2), + IOMUXF_EINT0 = 2, + + /* PORT G */ + IOMUXG_EINT23 = (2 << 30), + IOMUXG_EINT22 = (2 << 28), + IOMUXG_EINT21 = (2 << 26), + IOMUXG_EINT20 = (2 << 24), + IOMUXG_EINT19 = (2 << 22), + IOMUXG_EINT18 = (2 << 20), + IOMUXG_EINT17 = (2 << 18), + IOMUXG_EINT16 = (2 << 16), + IOMUXG_EINT15 = (2 << 14), + IOMUXG_EINT14 = (2 << 12), + IOMUXG_EINT13 = (2 << 10), + IOMUXG_EINT12 = (2 << 8), + IOMUXG_EINT11 = (2 << 6), + IOMUXG_EINT10 = (2 << 4), + IOMUXG_EINT9 = (2 << 2), + IOMUXG_EINT8 = 2, + IOMUXG_TCLK1 = (3 << 22), + IOMUXG_nCTS1 = (3 << 20), + IOMUXG_nRTS1 = (3 << 18), + IOMUXG_SPICLK1 = (3 << 14), + IOMUXG_SPIMOSI1 = (3 << 12), + IOMUXG_SPIMISO1 = (3 << 10), + IOMUXG_LCD_PWRDN = (3 << 8), + IOMUXG_nSS1 = (3 << 6), + IOMUXG_nSS0 = (3 << 4), + + /* PORT H */ + IOMUXH_CLKOUT1 = (2 << 20), + IOMUXH_CLKOUT0 = (2 << 18), + IOMUXH_UEXTCLK = (2 << 16), + IOMUXH_RXD2 = (2 << 14), + IOMUXH_TXD2 = (2 << 12), + IOMUXH_RXD1 = (2 << 10), + IOMUXH_TXD1 = (2 << 8), + IOMUXH_RXD0 = (2 << 6), + IOMUXH_TXD0 = (2 << 4), + IOMUXH_nRTS0 = (2 << 2), + IOMUXH_nCTS0 = 2, + IOMUXH_nCTS1 = (3 << 14), + IOMUXH_nRTS1 = (3 << 12), + + /* PORT J */ + IOMUXJ_CAMRESET = (2 << 24), + IOMUXJ_CAMCLKOUT = (2 << 22), + IOMUXJ_CAMHREF = (2 << 20), + IOMUXJ_CAMVSYNC = (2 << 18), + IOMUXJ_CAMPCLK = (2 << 16), + IOMUXJ_CAMDATA7 = (2 << 14), + IOMUXJ_CAMDATA6 = (2 << 12), + IOMUXJ_CAMDATA5 = (2 << 10), + IOMUXJ_CAMDATA4 = (2 << 8), + IOMUXJ_CAMDATA3 = (2 << 6), + IOMUXJ_CAMDATA2 = (2 << 4), + IOMUXJ_CAMDATA1 = (2 << 2), + IOMUXJ_CAMDATA0 = 2 +}; + +#endif diff --git a/arch/arm/include/asm/arch-socfpga/reset_manager.h b/arch/arm/include/asm/arch-socfpga/reset_manager.h new file mode 100644 index 0000000000..d9d2c1c56f --- /dev/null +++ b/arch/arm/include/asm/arch-socfpga/reset_manager.h @@ -0,0 +1,37 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _RESET_MANAGER_H_ +#define _RESET_MANAGER_H_ + +void reset_cpu(ulong addr); +void reset_deassert_peripherals_handoff(void); + +struct socfpga_reset_manager { + u32 padding1; + u32 ctrl; + u32 padding2; + u32 padding3; + u32 mpu_mod_reset; + u32 per_mod_reset; + u32 per2_mod_reset; + u32 brg_mod_reset; +}; + +#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1 + +#endif /* _RESET_MANAGER_H_ */ diff --git a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h new file mode 100644 index 0000000000..f353eb261c --- /dev/null +++ b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _SOCFPGA_BASE_ADDRS_H_ +#define _SOCFPGA_BASE_ADDRS_H_ + +#define SOCFPGA_L3REGS_ADDRESS 0xff800000 +#define SOCFPGA_UART0_ADDRESS 0xffc02000 +#define SOCFPGA_UART1_ADDRESS 0xffc03000 +#define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000 +#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000 + +#endif /* _SOCFPGA_BASE_ADDRS_H_ */ diff --git a/arch/arm/include/asm/arch-socfpga/spl.h b/arch/arm/include/asm/arch-socfpga/spl.h new file mode 100644 index 0000000000..efd0c060ce --- /dev/null +++ b/arch/arm/include/asm/arch-socfpga/spl.h @@ -0,0 +1,26 @@ +/* + * Copyright (C) 2012 Pavel Machek <pavel@denx.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _SOCFPGA_SPL_H_ +#define _SOCFPGA_SPL_H_ + +/* Symbols from linker script */ +extern char __malloc_start, __malloc_end, __stack_start; + +#define BOOT_DEVICE_RAM 1 + +#endif diff --git a/arch/arm/include/asm/arch-socfpga/timer.h b/arch/arm/include/asm/arch-socfpga/timer.h new file mode 100644 index 0000000000..830c94a275 --- /dev/null +++ b/arch/arm/include/asm/arch-socfpga/timer.h @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _SOCFPGA_TIMER_H_ +#define _SOCFPGA_TIMER_H_ + +struct socfpga_timer { + u32 load_val; + u32 curr_val; + u32 ctrl; + u32 eoi; + u32 int_stat; +}; + +#endif diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h index 2d5c3bc376..a676b6d905 100644 --- a/arch/arm/include/asm/mach-types.h +++ b/arch/arm/include/asm/mach-types.h @@ -1105,6 +1105,8 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_UBISYS_P9D_EVP 3493 #define MACH_TYPE_ATDGP318 3494 #define MACH_TYPE_OMAP5_SEVM 3777 +#define MACH_TYPE_ARMADILLO_800EVA 3863 +#define MACH_TYPE_KZM9G 4140 #ifdef CONFIG_ARCH_EBSA110 # ifdef machine_arch_type @@ -14222,6 +14224,30 @@ extern unsigned int __machine_arch_type; # define machine_is_omap5_sevm() (0) #endif +#ifdef CONFIG_MACH_ARMADILLO800EVA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARMADILLO800EVA +# endif +# define machine_is_armadillo800eva() (machine_arch_type == MACH_TYPE_ARMADILLO800EVA) +#else +# define machine_is_armadillo800eva() (0) +#endif + +#ifdef CONFIG_MACH_KZM9G +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KZM9G +# endif +# define machine_is_kzm9g() (machine_arch_type == MACH_TYPE_KZM9G) +#else +# define machine_is_kzm9g() (0) +#endif + /* * These have not yet been registered */ diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index 599547d2c8..a9070d5445 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -69,8 +69,8 @@ void arch_lmb_reserve(struct lmb *lmb) sp = get_sp(); debug("## Current stack ends at 0x%08lx ", sp); - /* adjust sp by 1K to be safe */ - sp -= 1024; + /* adjust sp by 4K to be safe */ + sp -= 4096; lmb_reserve(lmb, sp, gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size - sp); } @@ -258,6 +258,9 @@ static int create_fdt(bootm_headers_t *images) fixup_memory_node(*of_flat_tree); fdt_fixup_ethernet(*of_flat_tree); fdt_initrd(*of_flat_tree, *initrd_start, *initrd_end, 1); +#ifdef CONFIG_OF_BOARD_SETUP + ft_board_setup(*of_flat_tree, gd->bd); +#endif return 0; } |
