diff options
Diffstat (limited to 'arch/arm/include')
| -rw-r--r-- | arch/arm/include/asm/arch-armada100/armada100.h | 121 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-armada100/cpu.h | 53 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-armada100/mfp.h | 67 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-davinci/davinci_misc.h | 69 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-davinci/hardware.h | 37 |
5 files changed, 345 insertions, 2 deletions
diff --git a/arch/arm/include/asm/arch-armada100/armada100.h b/arch/arm/include/asm/arch-armada100/armada100.h new file mode 100644 index 0000000000..d5d125a963 --- /dev/null +++ b/arch/arm/include/asm/arch-armada100/armada100.h @@ -0,0 +1,121 @@ +/* + * (C) Copyright 2010 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar <prafulla@marvell.com> + * Contributor: Mahavir Jain <mjain@marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _ASM_ARCH_ARMADA100_H +#define _ASM_ARCH_ARMADA100_H + +#ifndef __ASSEMBLY__ +#include <asm/types.h> +#include <asm/io.h> +#endif /* __ASSEMBLY__ */ + +#if defined (CONFIG_ARMADA100) +#include <asm/arch/cpu.h> + +/* Common APB clock register bit definitions */ +#define APBC_APBCLK (1<<0) /* APB Bus Clock Enable */ +#define APBC_FNCLK (1<<1) /* Functional Clock Enable */ +#define APBC_RST (1<<2) /* Reset Generation */ +/* Functional Clock Selection Mask */ +#define APBC_FNCLKSEL(x) (((x) & 0xf) << 4) + +/* Register Base Addresses */ +#define ARMD1_DRAM_BASE 0xB0000000 +#define ARMD1_TIMER_BASE 0xD4014000 +#define ARMD1_APBC1_BASE 0xD4015000 +#define ARMD1_APBC2_BASE 0xD4015800 +#define ARMD1_UART1_BASE 0xD4017000 +#define ARMD1_UART2_BASE 0xD4018000 +#define ARMD1_GPIO_BASE 0xD4019000 +#define ARMD1_SSP1_BASE 0xD401B000 +#define ARMD1_SSP2_BASE 0xD401C000 +#define ARMD1_MFPR_BASE 0xD401E000 +#define ARMD1_SSP3_BASE 0xD401F000 +#define ARMD1_SSP4_BASE 0xD4020000 +#define ARMD1_SSP5_BASE 0xD4021000 +#define ARMD1_UART3_BASE 0xD4026000 +#define ARMD1_MPMU_BASE 0xD4050000 +#define ARMD1_APMU_BASE 0xD4282800 +#define ARMD1_CPU_BASE 0xD4282C00 + +/* + * Main Power Management (MPMU) Registers + * Refer Datasheet Appendix A.8 + */ +struct armd1mpmu_registers { + u8 pad0[0x08 - 0x00]; + u32 fccr; /*0x0008*/ + u32 pocr; /*0x000c*/ + u32 posr; /*0x0010*/ + u32 succr; /*0x0014*/ + u8 pad1[0x030 - 0x014 - 4]; + u32 gpcr; /*0x0030*/ + u8 pad2[0x200 - 0x030 - 4]; + u32 wdtpcr; /*0x0200*/ + u8 pad3[0x1000 - 0x200 - 4]; + u32 apcr; /*0x1000*/ + u32 apsr; /*0x1004*/ + u8 pad4[0x1020 - 0x1004 - 4]; + u32 aprr; /*0x1020*/ + u32 acgr; /*0x1024*/ + u32 arsr; /*0x1028*/ +}; + +/* + * APB1 Clock Reset/Control Registers + * Refer Datasheet Appendix A.10 + */ +struct armd1apb1_registers { + u32 uart1; /*0x000*/ + u32 uart2; /*0x004*/ + u32 gpio; /*0x008*/ + u32 pwm1; /*0x00c*/ + u32 pwm2; /*0x010*/ + u32 pwm3; /*0x014*/ + u32 pwm4; /*0x018*/ + u8 pad0[0x028 - 0x018 - 4]; + u32 rtc; /*0x028*/ + u32 twsi0; /*0x02c*/ + u32 kpc; /*0x030*/ + u32 timers; /*0x034*/ + u8 pad1[0x03c - 0x034 - 4]; + u32 aib; /*0x03c*/ + u32 sw_jtag; /*0x040*/ + u32 timer1; /*0x044*/ + u32 onewire; /*0x048*/ + u8 pad2[0x050 - 0x048 - 4]; + u32 asfar; /*0x050 AIB Secure First Access Reg*/ + u32 assar; /*0x054 AIB Secure Second Access Reg*/ + u8 pad3[0x06c - 0x054 - 4]; + u32 twsi1; /*0x06c*/ + u32 uart3; /*0x070*/ + u8 pad4[0x07c - 0x070 - 4]; + u32 timer2; /*0x07C*/ + u8 pad5[0x084 - 0x07c - 4]; + u32 ac97; /*0x084*/ +}; + +#endif /* CONFIG_ARMADA100 */ +#endif /* _ASM_ARCH_ARMADA100_H */ diff --git a/arch/arm/include/asm/arch-armada100/cpu.h b/arch/arm/include/asm/arch-armada100/cpu.h new file mode 100644 index 0000000000..0518a6a4b0 --- /dev/null +++ b/arch/arm/include/asm/arch-armada100/cpu.h @@ -0,0 +1,53 @@ +/* + * (C) Copyright 2010 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar <prafulla@marvell.com>, Contributor: Mahavir Jain <mjain@marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _ARMADA100CPU_H +#define _ARMADA100CPU_H + +#include <asm/io.h> +#include <asm/system.h> + +/* + * CPU Interface Registers + * Refer Datasheet Appendix A.2 + */ +struct armd1cpu_registers { + u32 chip_id; /* Chip Id Reg */ + u32 pad; + u32 cpu_conf; /* CPU Conf Reg */ + u32 pad1; + u32 cpu_sram_spd; /* CPU SRAM Speed Reg */ + u32 pad2; + u32 cpu_l2c_spd; /* CPU L2cache Speed Conf */ + u32 mcb_conf; /* MCB Conf Reg */ + u32 sys_boot_ctl; /* Sytem Boot Control */ +}; + +/* + * Functions + */ +u32 armd1_sdram_base(int); +u32 armd1_sdram_size(int); + +#endif /* _ARMADA100CPU_H */ diff --git a/arch/arm/include/asm/arch-armada100/mfp.h b/arch/arm/include/asm/arch-armada100/mfp.h new file mode 100644 index 0000000000..d21a79fa1f --- /dev/null +++ b/arch/arm/include/asm/arch-armada100/mfp.h @@ -0,0 +1,67 @@ +/* + * Based on linux/arch/arm/mach-mpp/include/mfp-pxa168.h + * (C) Copyright 2007 + * Marvell Semiconductor <www.marvell.com> + * 2007-08-21: eric miao <eric.miao@marvell.com> + * + * (C) Copyright 2010 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar <prafulla@marvell.com> + * Contributor: Mahavir Jain <mjain@marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef __ARMADA100_MFP_H +#define __ARMADA100_MFP_H + +/* + * Frequently used MFP Configuration macros for all ARMADA100 family of SoCs + * + * offset, pull,pF, drv,dF, edge,eF ,afn,aF + */ +/* UART1 */ +#define MFP107_UART1_TXD MFP_REG(0x01ac) | MFP_AF1 | MFP_DRIVE_FAST +#define MFP107_UART1_RXD MFP_REG(0x01ac) | MFP_AF2 | MFP_DRIVE_FAST +#define MFP108_UART1_RXD MFP_REG(0x01b0) | MFP_AF1 | MFP_DRIVE_FAST +#define MFP108_UART1_TXD MFP_REG(0x01b0) | MFP_AF2 | MFP_DRIVE_FAST +#define MFP109_UART1_CTS MFP_REG(0x01b4) | MFP_AF1 | MFP_DRIVE_MEDIUM +#define MFP109_UART1_RTS MFP_REG(0x01b4) | MFP_AF2 | MFP_DRIVE_MEDIUM +#define MFP110_UART1_RTS MFP_REG(0x01b8) | MFP_AF1 | MFP_DRIVE_MEDIUM +#define MFP110_UART1_CTS MFP_REG(0x01b8) | MFP_AF2 | MFP_DRIVE_MEDIUM +#define MFP111_UART1_RI MFP_REG(0x01bc) | MFP_AF1 | MFP_DRIVE_MEDIUM +#define MFP111_UART1_DSR MFP_REG(0x01bc) | MFP_AF2 | MFP_DRIVE_MEDIUM +#define MFP112_UART1_DTR MFP_REG(0x01c0) | MFP_AF1 | MFP_DRIVE_MEDIUM +#define MFP112_UART1_DCD MFP_REG(0x01c0) | MFP_AF2 | MFP_DRIVE_MEDIUM + +/* UART2 */ +#define MFP47_UART2_RXD MFP_REG(0x0028) | MFP_AF6 | MFP_DRIVE_MEDIUM +#define MFP48_UART2_TXD MFP_REG(0x002c) | MFP_AF6 | MFP_DRIVE_MEDIUM +#define MFP88_UART2_RXD MFP_REG(0x0160) | MFP_AF2 | MFP_DRIVE_MEDIUM +#define MFP89_UART2_TXD MFP_REG(0x0164) | MFP_AF2 | MFP_DRIVE_MEDIUM + +/* UART3 */ +#define MFPO8_UART3_RXD MFP_REG(0x06c) | MFP_AF2 | MFP_DRIVE_MEDIUM +#define MFPO9_UART3_TXD MFP_REG(0x070) | MFP_AF2 | MFP_DRIVE_MEDIUM + +/* More macros can be defined here... */ + +#define MFP_PIN_MAX 117 + +#endif /* __ARMADA100_MFP_H */ diff --git a/arch/arm/include/asm/arch-davinci/davinci_misc.h b/arch/arm/include/asm/arch-davinci/davinci_misc.h new file mode 100644 index 0000000000..347aa89e39 --- /dev/null +++ b/arch/arm/include/asm/arch-davinci/davinci_misc.h @@ -0,0 +1,69 @@ +/* + * Copyright (C) 2008 Lyrtech <www.lyrtech.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __MISC_H +#define __MISC_H + +/* pin muxer definitions */ +#define PIN_MUX_NUM_FIELDS 8 /* Per register */ +#define PIN_MUX_FIELD_SIZE 4 /* n in bits */ +#define PIN_MUX_FIELD_MASK ((1 << PIN_MUX_FIELD_SIZE) - 1) + +/* pin definition */ +struct pinmux_config { + dv_reg *mux; /* Address of mux register */ + unsigned char value; /* Value to set in field */ + unsigned char field; /* field number */ +}; + +/* pin table definition */ +struct pinmux_resource { + const struct pinmux_config *pins; + const int n_pins; +}; + +#define PINMUX_ITEM(item) { \ + .pins = item, \ + .n_pins = ARRAY_SIZE(item) \ + } + +#define HAWKBOARD_KICK0_UNLOCK 0x83e70b13 +#define HAWKBOARD_KICK1_UNLOCK 0x95a4f1e0 + +struct lpsc_resource { + const int lpsc_no; +}; + +int dvevm_read_mac_address(uint8_t *buf); +void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr); +int davinci_configure_pin_mux(const struct pinmux_config *pins, int n_pins); +int davinci_configure_pin_mux_items(const struct pinmux_resource *item, + int n_items); +#if defined(CONFIG_DRIVER_TI_EMAC) && defined(CONFIG_MACH_DAVINCI_DA850_EVM) +void davinci_emac_mii_mode_sel(int mode_sel); +#endif +#if defined(CONFIG_SOC_DA8XX) +void irq_init(void); +int da8xx_configure_lpsc_items(const struct lpsc_resource *item, + const int n_items); +#endif + +#endif /* __MISC_H */ diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h index 3520cf8822..b95fa97bac 100644 --- a/arch/arm/include/asm/arch-davinci/hardware.h +++ b/arch/arm/include/asm/arch-davinci/hardware.h @@ -133,7 +133,8 @@ typedef volatile unsigned int * dv_reg_p; #define DAVINCI_PSC1_BASE 0x01e27000 #define DAVINCI_SPI0_BASE 0x01c41000 #define DAVINCI_USB_OTG_BASE 0x01e00000 -#define DAVINCI_SPI1_BASE 0x01e12000 +#define DAVINCI_SPI1_BASE (cpu_is_da830() ? \ + 0x01e12000 : 0x01f0e000) #define DAVINCI_GPIO_BASE 0x01e26000 #define DAVINCI_EMAC_CNTRL_REGS_BASE 0x01e23000 #define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE 0x01e22000 @@ -149,7 +150,12 @@ typedef volatile unsigned int * dv_reg_p; #define DAVINCI_DDR_EMIF_DATA_BASE 0xc0000000 #define DAVINCI_INTC_BASE 0xfffee000 #define DAVINCI_BOOTCFG_BASE 0x01c14000 +#define JTAG_ID_REG (DAVINCI_BOOTCFG_BASE + 0x18) +#define GPIO_BANK2_REG_DIR_ADDR (DAVINCI_GPIO_BASE + 0x38) +#define GPIO_BANK2_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x3c) +#define GPIO_BANK2_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x40) +#define GPIO_BANK2_REG_CLR_ADDR (DAVINCI_GPIO_BASE + 0x44) #endif /* CONFIG_SOC_DA8XX */ /* Power and Sleep Controller (PSC) Domains */ @@ -363,6 +369,9 @@ struct davinci_pllc_regs { #define davinci_pllc_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL0_BASE) #define DAVINCI_PLLC_DIV_MASK 0x1f +#define ASYNC3 get_async3_src() +#define PLL1_SYSCLK2 ((1 << 16) | 0x2) +#define DAVINCI_SPI1_CLKID (cpu_is_da830() ? 2 : ASYNC3) /* Clock IDs */ enum davinci_clk_ids { DAVINCI_SPI0_CLKID = 2, @@ -379,7 +388,10 @@ int clk_get(enum davinci_clk_ids id); /* Boot config */ struct davinci_syscfg_regs { dv_reg revid; - dv_reg rsvd[71]; + dv_reg rsvd[13]; + dv_reg kick0; + dv_reg kick1; + dv_reg rsvd1[56]; dv_reg pinmux[20]; dv_reg suspsrc; dv_reg chipsig; @@ -442,6 +454,27 @@ struct davinci_uart_ctrl_regs { #define DAVINCI_UART_PWREMU_MGMT_URRST (1 << 13) #define DAVINCI_UART_PWREMU_MGMT_UTRST (1 << 14) +static inline int cpu_is_da830(void) +{ + unsigned int jtag_id = REG(JTAG_ID_REG); + unsigned short part_no = (jtag_id >> 12) & 0xffff; + + return ((part_no == 0xb7df) ? 1 : 0); +} +static inline int cpu_is_da850(void) +{ + unsigned int jtag_id = REG(JTAG_ID_REG); + unsigned short part_no = (jtag_id >> 12) & 0xffff; + + return ((part_no == 0xb7d1) ? 1 : 0); +} + +static inline int get_async3_src(void) +{ + return (REG(&davinci_syscfg_regs->cfgchip3) & 0x10) ? + PLL1_SYSCLK2 : 2; +} + #endif /* CONFIG_SOC_DA8XX */ #endif /* __ASM_ARCH_HARDWARE_H */ |
