diff options
Diffstat (limited to 'arch/arm/cpu/armv7/mx6/soc.c')
| -rw-r--r-- | arch/arm/cpu/armv7/mx6/soc.c | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 543b2cc6d8..90f208809b 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -77,10 +77,40 @@ void init_aips(void) writel(0x00000000, &aips2->opacr4); } +/* + * Set the VDDSOC + * + * Mask out the REG_CORE[22:18] bits (REG2_TRIG) and set + * them to the specified millivolt level. + * Possible values are from 0.725V to 1.450V in steps of + * 0.025V (25mV). + */ +void set_vddsoc(u32 mv) +{ + struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; + u32 val, reg = readl(&anatop->reg_core); + + if (mv < 725) + val = 0x00; /* Power gated off */ + else if (mv > 1450) + val = 0x1F; /* Power FET switched full on. No regulation */ + else + val = (mv - 700) / 25; + + /* + * Mask out the REG_CORE[22:18] bits (REG2_TRIG) + * and set them to the calculated value (0.7V + val * 0.25V) + */ + reg = (reg & ~(0x1F << 18)) | (val << 18); + writel(reg, &anatop->reg_core); +} + int arch_cpu_init(void) { init_aips(); + set_vddsoc(1200); /* Set VDDSOC to 1.2V */ + return 0; } #endif |
