diff options
Diffstat (limited to 'arch/arm/cpu/arm926ejs/at91/clock.c')
| -rw-r--r-- | arch/arm/cpu/arm926ejs/at91/clock.c | 55 |
1 files changed, 27 insertions, 28 deletions
diff --git a/arch/arm/cpu/arm926ejs/at91/clock.c b/arch/arm/cpu/arm926ejs/at91/clock.c index ecf91f5187..7a10a77877 100644 --- a/arch/arm/cpu/arm926ejs/at91/clock.c +++ b/arch/arm/cpu/arm926ejs/at91/clock.c @@ -11,47 +11,46 @@ * (at your option) any later version. */ -#include <config.h> +#include <common.h> #include <asm/arch/hardware.h> #include <asm/arch/io.h> #include <asm/arch/at91_pmc.h> #include <asm/arch/clk.h> -static unsigned long cpu_clk_rate_hz; -static unsigned long main_clk_rate_hz; -static unsigned long mck_rate_hz; -static unsigned long plla_rate_hz; -static unsigned long pllb_rate_hz; -static u32 at91_pllb_usb_init; +#if !defined(CONFIG_AT91FAMILY) +# error You need to define CONFIG_AT91FAMILY in your board config! +#endif + +DECLARE_GLOBAL_DATA_PTR; unsigned long get_cpu_clk_rate(void) { - return cpu_clk_rate_hz; + return gd->cpu_clk_rate_hz; } unsigned long get_main_clk_rate(void) { - return main_clk_rate_hz; + return gd->main_clk_rate_hz; } unsigned long get_mck_clk_rate(void) { - return mck_rate_hz; + return gd->mck_rate_hz; } unsigned long get_plla_clk_rate(void) { - return plla_rate_hz; + return gd->plla_rate_hz; } unsigned long get_pllb_clk_rate(void) { - return pllb_rate_hz; + return gd->pllb_rate_hz; } u32 get_pllb_init(void) { - return at91_pllb_usb_init; + return gd->at91_pllb_usb_init; } static unsigned long at91_css_to_rate(unsigned long css) @@ -60,11 +59,11 @@ static unsigned long at91_css_to_rate(unsigned long css) case AT91_PMC_MCKR_CSS_SLOW: return AT91_SLOW_CLOCK; case AT91_PMC_MCKR_CSS_MAIN: - return main_clk_rate_hz; + return gd->main_clk_rate_hz; case AT91_PMC_MCKR_CSS_PLLA: - return plla_rate_hz; + return gd->plla_rate_hz; case AT91_PMC_MCKR_CSS_PLLB: - return pllb_rate_hz; + return gd->pllb_rate_hz; } return 0; @@ -163,10 +162,10 @@ int at91_clock_init(unsigned long main_clock) main_clock = tmp * (AT91_SLOW_CLOCK / 16); } #endif - main_clk_rate_hz = main_clock; + gd->main_clk_rate_hz = main_clock; /* report if PLLA is more than mildly overclocked */ - plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar)); + gd->plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar)); #ifdef CONFIG_USB_ATMEL /* @@ -175,9 +174,9 @@ int at91_clock_init(unsigned long main_clock) * * REVISIT: assumes MCK doesn't derive from PLLB! */ - at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | + gd->at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_PLLBR_USBDIV_2; - pllb_rate_hz = at91_pll_rate(main_clock, at91_pllb_usb_init); + gd->pllb_rate_hz = at91_pll_rate(main_clock, gd->at91_pllb_usb_init); #endif /* @@ -187,30 +186,30 @@ int at91_clock_init(unsigned long main_clock) mckr = readl(&pmc->mckr); #if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) /* plla divisor by 2 */ - plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12)); + gd->plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12)); #endif - mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK); - freq = mck_rate_hz; + gd->mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK); + freq = gd->mck_rate_hz; freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2)); /* prescale */ #if defined(CONFIG_AT91RM9200) /* mdiv */ - mck_rate_hz = freq / (1 + ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8)); + gd->mck_rate_hz = freq / (1 + ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8)); #elif defined(CONFIG_AT91SAM9G20) /* mdiv ; (x >> 7) = ((x >> 8) * 2) */ - mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ? + gd->mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ? freq / ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 7) : freq; if (mckr & AT91_PMC_MCKR_MDIV_MASK) freq /= 2; /* processor clock division */ #elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) - mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) == + gd->mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) == (AT91_PMC_MCKR_MDIV_2 | AT91_PMC_MCKR_MDIV_4) ? freq / 3 : freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8)); #else - mck_rate_hz = freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8)); + gd->mck_rate_hz = freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8)); #endif - cpu_clk_rate_hz = freq; + gd->cpu_clk_rate_hz = freq; return 0; } |
