diff options
30 files changed, 1510 insertions, 153 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index e00322687c..785fccf56c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -548,6 +548,7 @@ Stefano Babic <sbabic@denx.de> polaris xscale trizepsiv xscale mx51evk i.MX51 + vision2 i.MX51 Dirk Behme <dirk.behme@gmail.com> diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index ae20299db7..7743fefdbe 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -27,6 +27,7 @@ LIB = $(obj)lib$(CPU).a START := start.o COBJS := cpu.o +COBJS += syslib.o SRCS := $(START:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) @@ -44,4 +45,4 @@ include $(SRCTREE)/rules.mk sinclude $(obj).depend -#########################################################################
\ No newline at end of file +######################################################################### diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile index caee7263b1..aedea7b95b 100644 --- a/arch/arm/cpu/armv7/omap-common/Makefile +++ b/arch/arm/cpu/armv7/omap-common/Makefile @@ -28,7 +28,6 @@ LIB = $(obj)libomap-common.a SOBJS := reset.o COBJS := timer.o -COBJS += syslib.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/arch/arm/cpu/armv7/omap-common/syslib.c b/arch/arm/cpu/armv7/syslib.c index f9ed9a307b..f9ed9a307b 100644 --- a/arch/arm/cpu/armv7/omap-common/syslib.c +++ b/arch/arm/cpu/armv7/syslib.c diff --git a/arch/arm/include/asm/arch-mx31/mx31-regs.h b/arch/arm/include/asm/arch-mx31/mx31-regs.h index d72585c8a0..f05e743d76 100644 --- a/arch/arm/include/asm/arch-mx31/mx31-regs.h +++ b/arch/arm/include/asm/arch-mx31/mx31-regs.h @@ -57,6 +57,14 @@ struct clock_control_regs { u32 pdr2; }; +/* GPIO Registers */ +struct gpio_regs { + u32 gpio_dr; + u32 gpio_dir; + u32 gpio_psr; +}; + + /* Bit definitions for RCSR register in CCM */ #define CCM_RCSR_NF16B (1 << 31) #define CCM_RCSR_NFMS (1 << 30) @@ -153,9 +161,9 @@ struct clock_control_regs { /* * GPIO */ -#define GPIO1_BASE 0x53FCC000 -#define GPIO2_BASE 0x53FD0000 -#define GPIO3_BASE 0x53FA4000 +#define GPIO1_BASE_ADDR 0x53FCC000 +#define GPIO2_BASE_ADDR 0x53FD0000 +#define GPIO3_BASE_ADDR 0x53FA4000 #define GPIO_DR 0x00000000 /* data register */ #define GPIO_GDIR 0x00000004 /* direction register */ #define GPIO_PSR 0x00000008 /* pad status register */ diff --git a/arch/arm/include/asm/arch-mx31/mx31.h b/arch/arm/include/asm/arch-mx31/mx31.h index f702d260f1..5a5aa114a7 100644 --- a/arch/arm/include/asm/arch-mx31/mx31.h +++ b/arch/arm/include/asm/arch-mx31/mx31.h @@ -28,31 +28,6 @@ extern u32 mx31_get_ipg_clk(void); #define imx_get_uartclk mx31_get_ipg_clk extern void mx31_gpio_mux(unsigned long mode); -enum mx31_gpio_direction { - MX31_GPIO_DIRECTION_IN, - MX31_GPIO_DIRECTION_OUT, -}; - -#ifdef CONFIG_MX31_GPIO -extern int mx31_gpio_direction(unsigned int gpio, - enum mx31_gpio_direction direction); -extern void mx31_gpio_set(unsigned int gpio, unsigned int value); -extern int mx31_gpio_get(unsigned int gpio); -#else -static inline int mx31_gpio_direction(unsigned int gpio, - enum mx31_gpio_direction direction) -{ - return 1; -} -static inline int mx31_gpio_get(unsigned int gpio) -{ - return 1; -} -static inline void mx31_gpio_set(unsigned int gpio, unsigned int value) -{ -} -#endif - void mx31_uart1_hw_init(void); void mx31_spi2_hw_init(void); diff --git a/arch/arm/include/asm/arch-mx51/imx-regs.h b/arch/arm/include/asm/arch-mx51/imx-regs.h index 3887d3cec4..3ddda401f3 100644 --- a/arch/arm/include/asm/arch-mx51/imx-regs.h +++ b/arch/arm/include/asm/arch-mx51/imx-regs.h @@ -23,9 +23,6 @@ #ifndef __ASM_ARCH_MXC_MX51_H__ #define __ASM_ARCH_MXC_MX51_H__ -#define __REG(x) (*((volatile u32 *)(x))) -#define __REG16(x) (*((volatile u16 *)(x))) -#define __REG8(x) (*((volatile u8 *)(x))) /* * IRAM */ @@ -207,7 +204,12 @@ #define BOARD_REV_1_0 0x0 #define BOARD_REV_2_0 0x1 -#ifndef __ASSEMBLY__ +#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) +#include <asm/types.h> + +#define __REG(x) (*((volatile u32 *)(x))) +#define __REG16(x) (*((volatile u16 *)(x))) +#define __REG8(x) (*((volatile u8 *)(x))) struct clkctl { u32 ccr; @@ -256,6 +258,22 @@ struct weim { u32 cswcr2; }; +/* GPIO Registers */ +struct gpio_regs { + u32 gpio_dr; + u32 gpio_dir; + u32 gpio_psr; +}; + +/* System Reset Controller (SRC) */ +struct src { + u32 scr; + u32 sbmr; + u32 srsr; + u32 reserved1[2]; + u32 sisr; + u32 simr; +}; #endif /* __ASSEMBLER__*/ #endif /* __ASM_ARCH_MXC_MX51_H__ */ diff --git a/arch/arm/include/asm/arch-mx51/mx51_pins.h b/arch/arm/include/asm/arch-mx51/mx51_pins.h index ca26f4166b..b44ff252bf 100644 --- a/arch/arm/include/asm/arch-mx51/mx51_pins.h +++ b/arch/arm/include/asm/arch-mx51/mx51_pins.h @@ -368,6 +368,50 @@ enum iomux_pins { MX51_PIN_GPIO1_7 = _MXC_BUILD_GPIO_PIN(0, 7, 0, 0x3E4, 0x810), MX51_PIN_GPIO1_8 = _MXC_BUILD_GPIO_PIN(0, 8, 0, 0x3E8, 0x814), MX51_PIN_GPIO1_9 = _MXC_BUILD_GPIO_PIN(0, 9, 0, 0x3EC, 0x818), + + /* The following are PADS used for drive strength */ + + MX51_PIN_CTL_GRP_DDRPKS = _MXC_BUILD_NON_GPIO_PIN(0, 0x820), + MX51_PIN_CTL_GRP_PKEDDR = _MXC_BUILD_NON_GPIO_PIN(0, 0x838), + MX51_PIN_CTL_GRP_PKEADDR = _MXC_BUILD_NON_GPIO_PIN(0, 0x890), + MX51_PIN_CTL_GRP_DDRAPKS = _MXC_BUILD_NON_GPIO_PIN(0, 0x87C), + MX51_PIN_CTL_GRP_DDRAPUS = _MXC_BUILD_NON_GPIO_PIN(0, 0x84C), + MX51_PIN_CTL_GRP_DDRPUS = _MXC_BUILD_NON_GPIO_PIN(0, 0x884), + MX51_PIN_CTL_GRP_HYSDDR0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x85C), + MX51_PIN_CTL_GRP_HYSDDR1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x864), + MX51_PIN_CTL_GRP_HYSDDR2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x86C), + MX51_PIN_CTL_GRP_HYSDDR3 = _MXC_BUILD_NON_GPIO_PIN(0, 0x874), + MX51_PIN_CTL_GRP_DDR_SR_B0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x878), + MX51_PIN_CTL_GRP_DDR_SR_B1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x880), + MX51_PIN_CTL_GRP_DDR_SR_B2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x88C), + MX51_PIN_CTL_GRP_DDR_SR_B4 = _MXC_BUILD_NON_GPIO_PIN(0, 0x89C), + MX51_PIN_CTL_GRP_DRAM_B0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8A4), + MX51_PIN_CTL_GRP_DRAM_B1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8AC), + MX51_PIN_CTL_GRP_DRAM_B2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8B8), + MX51_PIN_CTL_GRP_DRAM_B4 = _MXC_BUILD_NON_GPIO_PIN(0, 0x82C), + MX51_PIN_CTL_GRP_INMODE1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8A0), + MX51_PIN_CTL_GRP_DDR_SR_A0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8B0), + MX51_PIN_CTL_GRP_EMI_DS5 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8B4), + MX51_PIN_CTL_GRP_DDR_SR_A1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8BC), + MX51_PIN_CTL_GRP_DDR_A0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x83C), + MX51_PIN_CTL_GRP_DDR_A1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x848), + MX51_PIN_CTL_GRP_DISP_PKE0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x868), + MX51_PIN_CTL_DRAM_RAS = _MXC_BUILD_NON_GPIO_PIN(0, 0x4A4), + MX51_PIN_CTL_DRAM_CAS = _MXC_BUILD_NON_GPIO_PIN(0, 0x4A8), + MX51_PIN_CTL_DRAM_SDWE = _MXC_BUILD_NON_GPIO_PIN(0, 0x4Ac), + MX51_PIN_CTL_DRAM_SDCKE0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4B0), + MX51_PIN_CTL_DRAM_SDCKE1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4B4), + MX51_PIN_CTL_DRAM_SDCLK = _MXC_BUILD_NON_GPIO_PIN(0, 0x4B8), + MX51_PIN_CTL_DRAM_SDQS0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4BC), + MX51_PIN_CTL_DRAM_SDQS1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4C0), + MX51_PIN_CTL_DRAM_SDQS2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4C4), + MX51_PIN_CTL_DRAM_SDQS3 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4C8), + MX51_PIN_CTL_DRAM_CS0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4CC), + MX51_PIN_CTL_DRAM_CS1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4D0), + MX51_PIN_CTL_DRAM_DQM0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4D4), + MX51_PIN_CTL_DRAM_DQM1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4D8), + MX51_PIN_CTL_DRAM_DQM2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4DC), + MX51_PIN_CTL_DRAM_DQM3 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4E0), }; #endif /* __ASSEMBLY__ */ diff --git a/arch/arm/include/asm/arch-mx51/sys_proto.h b/arch/arm/include/asm/arch-mx51/sys_proto.h index bf500a8b32..f687503cad 100644 --- a/arch/arm/include/asm/arch-mx51/sys_proto.h +++ b/arch/arm/include/asm/arch-mx51/sys_proto.h @@ -26,5 +26,6 @@ u32 get_cpu_rev(void); #define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev) +void sdelay(unsigned long); #endif diff --git a/board/davedenx/qong/qong.c b/board/davedenx/qong/qong.c index e509383e8f..9abc29c5f7 100644 --- a/board/davedenx/qong/qong.c +++ b/board/davedenx/qong/qong.c @@ -27,6 +27,7 @@ #include <asm/arch/mx31-regs.h> #include <nand.h> #include <fsl_pmic.h> +#include <mxc_gpio.h> #include "qong_fpga.h" DECLARE_GLOBAL_DATA_PTR; @@ -41,9 +42,9 @@ int dram_init (void) static void qong_fpga_reset(void) { - mx31_gpio_set(QONG_FPGA_RST_PIN, 0); + mxc_gpio_set(QONG_FPGA_RST_PIN, 0); udelay(30); - mx31_gpio_set(QONG_FPGA_RST_PIN, 1); + mxc_gpio_set(QONG_FPGA_RST_PIN, 1); udelay(300); } @@ -66,11 +67,11 @@ int board_early_init_f (void) /* FPGA reset Pin */ /* rstn = 0 */ - mx31_gpio_set(QONG_FPGA_RST_PIN, 0); - mx31_gpio_direction(QONG_FPGA_RST_PIN, MX31_GPIO_DIRECTION_OUT); + mxc_gpio_set(QONG_FPGA_RST_PIN, 0); + mxc_gpio_direction(QONG_FPGA_RST_PIN, MXC_GPIO_DIRECTION_OUT); /* set interrupt pin as input */ - mx31_gpio_direction(QONG_FPGA_IRQ_PIN, MX31_GPIO_DIRECTION_IN); + mxc_gpio_direction(QONG_FPGA_IRQ_PIN, MXC_GPIO_DIRECTION_IN); #endif @@ -206,27 +207,27 @@ static void board_nand_setup(void) qong_fpga_reset(); /* Enable NAND flash */ - mx31_gpio_set(15, 1); - mx31_gpio_set(14, 1); - mx31_gpio_direction(15, MX31_GPIO_DIRECTION_OUT); - mx31_gpio_direction(16, MX31_GPIO_DIRECTION_IN); - mx31_gpio_direction(14, MX31_GPIO_DIRECTION_IN); - mx31_gpio_set(15, 0); + mxc_gpio_set(15, 1); + mxc_gpio_set(14, 1); + mxc_gpio_direction(15, MXC_GPIO_DIRECTION_OUT); + mxc_gpio_direction(16, MXC_GPIO_DIRECTION_IN); + mxc_gpio_direction(14, MXC_GPIO_DIRECTION_IN); + mxc_gpio_set(15, 0); } int qong_nand_rdy(void *chip) { udelay(1); - return mx31_gpio_get(16); + return mxc_gpio_get(16); } void qong_nand_select_chip(struct mtd_info *mtd, int chip) { if (chip >= 0) - mx31_gpio_set(15, 0); + mxc_gpio_set(15, 0); else - mx31_gpio_set(15, 1); + mxc_gpio_set(15, 1); } diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c index 75d642bf42..84386e6c8f 100644 --- a/board/freescale/mx51evk/mx51evk.c +++ b/board/freescale/mx51evk/mx51evk.c @@ -33,12 +33,10 @@ #include <fsl_esdhc.h> #include <fsl_pmic.h> #include <mc13892.h> -#include "mx51evk.h" DECLARE_GLOBAL_DATA_PTR; static u32 system_rev; -struct io_board_ctrl *mx51_io_board; #ifdef CONFIG_FSL_ESDHC struct fsl_esdhc_cfg esdhc_cfg[2] = { diff --git a/board/ttcontrol/vision2/Makefile b/board/ttcontrol/vision2/Makefile new file mode 100644 index 0000000000..309e3a3df6 --- /dev/null +++ b/board/ttcontrol/vision2/Makefile @@ -0,0 +1,48 @@ +# +# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> +# +# (C) Copyright 2009 Freescale Semiconductor, Inc. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := vision2.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/ttcontrol/vision2/config.mk b/board/ttcontrol/vision2/config.mk new file mode 100644 index 0000000000..59f3367cfc --- /dev/null +++ b/board/ttcontrol/vision2/config.mk @@ -0,0 +1,25 @@ +# +# Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +LDSCRIPT = $(CPUDIR)/$(SOC)/u-boot.lds +TEXT_BASE = 0x97800000 +IMX_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/imximage_hynix.cfg diff --git a/board/ttcontrol/vision2/imximage_hynix.cfg b/board/ttcontrol/vision2/imximage_hynix.cfg new file mode 100644 index 0000000000..ed531db0bc --- /dev/null +++ b/board/ttcontrol/vision2/imximage_hynix.cfg @@ -0,0 +1,209 @@ +# +# (C) Copyright 2009 +# Stefano Babic DENX Software Engineering sbabic@denx.de. +# +# (C) Copyright 2010 +# Klaus Steinhammer TTECH Control Gmbh kst@tttech.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not write to the Free Software +# Foundation Inc. 51 Franklin Street Fifth Floor Boston, +# MA 02110-1301 USA +# +# Refer docs/README.imxmage for more details about how-to configure +# and create imximage boot image +# +# The syntax is taken as close as possible with the kwbimage + +# Boot Device : one of +# spi, nand, onenand, sd + +BOOT_FROM spi + +# Device Configuration Data (DCD) +# +# Each entry must have the format: +# Addr-type Address Value +# +# where: +# Addr-type register length (1,2 or 4 bytes) +# Address absolute address of the register +# value value to be stored in the register + +####################### +### Disable WDOG ### +####################### +DATA 2 0x73f98000 0x30 + +####################### +### SET DDR Clk ### +####################### + +# CCM: CBMCR - ddr_clk_sel: axi_b (133MHz) +DATA 4 0x73FD4018 0x000024C0 + +# DOUBLE SPI CLK (13MHz->26 MHz Clock) +DATA 4 0x73FD4038 0x2010241 + +#IOMUXC_SW_PAD_CTL_PAD_CSPI1_MOSI HYS_ENABLE | DRV_MAX | SRE_FAST +DATA 4 0x73fa8600 0x00000107 +#IOMUXC_SW_PAD_CTL_PAD_CSPI1_MISO HYS_ENABLE | DRV_MAX | SRE_FAST +DATA 4 0x73fa8604 0x00000107 +#IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS0 HYS_ENABLE | PKE_ENABLE | DRV_MAX | SRE_FAST +DATA 4 0x73fa8608 0x00000187 +#IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS1 HYS_ENABLE | PKE_ENABLE | DRV_MAX | SRE_FAST +DATA 4 0x73fa860c 0x00000187 +#IOMUXC_SW_PAD_CTL_PAD_CSPI1_SCLK HYS_ENABLE | DRV_MAX | SRE_FAST +DATA 4 0x73fa8614 0x00000107 +#IOMUXC_SW_PAD_CTL_PAD_DI1_PIN11 HYS_ENABLE | DRV_MAX | SRE_FAST (CSPI1_SS2) +DATA 4 0x73fa86a8 0x00000187 + +####################### +### Settings IOMUXC ### +####################### + +# DDR IOMUX configuration +# Control, Data, Address pads are in their default state: HIGH DS, FAST SR. +# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK MAX DS +DATA 4 0x73fa84b8 0x000000e7 +# PVTC MAX (at GPC, PGR reg) +#DATA 4 0x73FD8004 0x1fc00000 + +#DQM0 DS high slew rate slow +DATA 4 0x73fa84d4 0x000000e4 +#DQM1 DS high slew rate slow +DATA 4 0x73fa84d8 0x000000e4 +#DQM2 DS high slew rate slow +DATA 4 0x73fa84dc 0x000000e4 +#DQM3 DS high slew rate slow +DATA 4 0x73fa84e0 0x000000e4 + +#IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 DS high & SLEW slow +DATA 4 0x73fa84bc 0x000000c4 +#IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 DS high & SLEW slow +DATA 4 0x73fa84c0 0x000000c4 +#IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 DS high & SLEW slow +DATA 4 0x73fa84c4 0x000000c4 +#IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 DS high & SLEW slow +DATA 4 0x73fa84c8 0x000000c4 + +#DRAM_DATA B0 +DATA 4 0x73fa88a4 0x00000004 +#DRAM_DATA B1 +DATA 4 0x73fa88ac 0x00000004 +#DRAM_DATA B2 +DATA 4 0x73fa88b8 0x00000004 +#DRAM_DATA B3 +DATA 4 0x73fa882c 0x00000004 + +#DRAM_DATA B0 slew rate +DATA 4 0x73fa8878 0x00000000 +#DRAM_DATA B1 slew rate +DATA 4 0x73fa8880 0x00000000 +#DRAM_DATA B2 slew rate +DATA 4 0x73fa888c 0x00000000 +#DRAM_DATA B3 slew rate +DATA 4 0x73fa889c 0x00000000 + +####################### +### Configure SDRAM ### +####################### + +# Configure CS0 +####################### + +# ESDCTL0: Enable controller +DATA 4 0x83fd9000 0x83220000 + +# Init DRAM on CS0 +# ESDSCR: Precharge command +DATA 4 0x83fd9014 0x04008008 +# ESDSCR: Refresh command +DATA 4 0x83fd9014 0x00008010 +# ESDSCR: Refresh command +DATA 4 0x83fd9014 0x00008010 +# ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8) +DATA 4 0x83fd9014 0x00338018 +# ESDSCR: EMR with half Drive strength (= medium strength @ i.MX51) +DATA 4 0x83fd9014 0x0020801a +# ESDSCR +DATA 4 0x83fd9014 0x00008000 + +# ESDSCR: EMR with full Drive strength +#DATA 4 0x83fd9014 0x0000801a + +# ESDCTL0: 14 ROW, 10 COL, 32Bit, SREF=8 +DATA 4 0x83fd9000 0xC3220000 + +# ESDCFG0: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks +# tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks +#DATA 4 0x83fd9004 0xC33574AA + +#micron mDDR +# ESDCFG0: tRFC:11clks, tXSR:19clks, tXP:1clks, tWTR:2clk, tRP:3clks, tMRD:2clks +# tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks +#DATA 4 0x83FD9004 0x101564a8 + +#hynix mDDR +# ESDCFG0: tRFC:17clks, tXSR:21clks, tXP:3clks, tWTR:1clk, tRP:3clks, tMRD:2clks +# tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks +DATA 4 0x83FD9004 0x704564a8 + +# ESDMISC: AP=10, Bank interleaving on, MIF3 en, RALAT=2 +DATA 4 0x83fd9010 0x000a1700 + +# Configure CS1 +####################### + +# ESDCTL1: Enable controller +DATA 4 0x83fd9008 0x83220000 + +# Init DRAM on CS1 +# ESDSCR: Precharge command +DATA 4 0x83fd9014 0x0400800c +# ESDSCR: Refresh command +DATA 4 0x83fd9014 0x00008014 +# ESDSCR: Refresh command +DATA 4 0x83fd9014 0x00008014 +# ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8) +DATA 4 0x83fd9014 0x0033801c +# ESDSCR: EMR with half Drive strength (= medium strength @ i.MX51) +DATA 4 0x83fd9014 0x0020801e +# ESDSCR +DATA 4 0x83fd9014 0x00008004 + +# ESDCTL1: 14 ROW, 10 COL, 32Bit, SREF=8 +DATA 4 0x83fd9008 0xC3220000 + +# ESDCFG1: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks +# tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks +#DATA 4 0x83fd900c 0xC33574AA + +#micron mDDR +# ESDCFG1: tRFC:11clks, tXSR:19clks, tXP:1clks, tWTR:2clk, tRP:3clks, tMRD:2clks +# tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks +#DATA 4 0x83FD900C 0x101564a8 + +#hynix mDDR +# ESDCFG0: tRFC:17clks, tXSR:21clks, tXP:3clks, tWTR:1clk, tRP:3clks, tMRD:2clks +# tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks +DATA 4 0x83FD900C 0x704564a8 + +# ESDSCR (mDRAM configuration finished) +DATA 4 0x83FD9014 0x00000004 + +# ESDSCR - clear "configuration request" bit +DATA 4 0x83fd9014 0x00000000 diff --git a/board/ttcontrol/vision2/vision2.c b/board/ttcontrol/vision2/vision2.c new file mode 100644 index 0000000000..c991ee271e --- /dev/null +++ b/board/ttcontrol/vision2/vision2.c @@ -0,0 +1,711 @@ +/* + * (C) Copyright 2010 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de. + * + * (C) Copyright 2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/mx51_pins.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/iomux.h> +#include <mxc_gpio.h> +#include <asm/arch/sys_proto.h> +#include <asm/errno.h> +#include <i2c.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include <fsl_pmic.h> +#include <mc13892.h> + +DECLARE_GLOBAL_DATA_PTR; + +static u32 system_rev; + +#ifdef CONFIG_HW_WATCHDOG +#include <watchdog.h> + +void hw_watchdog_reset(void) +{ + int val; + + /* toggle watchdog trigger pin */ + val = mxc_gpio_get(66); + val = val ? 0 : 1; + mxc_gpio_set(66, val); +} +#endif + +static void init_drive_strength(void) +{ + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_DDR_INPUT_CMOS); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEADDR, PAD_CTL_PKE_ENABLE); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPKS, PAD_CTL_PUE_KEEPER); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPUS, PAD_CTL_100K_PU); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_A1, PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A0, PAD_CTL_DRV_HIGH); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A1, PAD_CTL_DRV_HIGH); + mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_RAS, + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CAS, + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_PKE_ENABLE); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPKS, PAD_CTL_PUE_KEEPER); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR0, PAD_CTL_HYS_NONE); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR1, PAD_CTL_HYS_NONE); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR2, PAD_CTL_HYS_NONE); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR3, PAD_CTL_HYS_NONE); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B0, PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B1, PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B2, PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B4, PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPUS, PAD_CTL_100K_PU); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_INMODE1, PAD_CTL_DDR_INPUT_CMOS); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B0, PAD_CTL_DRV_MEDIUM); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B1, PAD_CTL_DRV_MEDIUM); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B2, PAD_CTL_DRV_MEDIUM); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B4, PAD_CTL_DRV_MEDIUM); + + /* Setting pad options */ + mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDWE, + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE0, + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE1, + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCLK, + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS0, + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS1, + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS2, + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS3, + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS0, + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS1, + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM0, + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM1, + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM2, + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM3, + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); +} + +u32 get_board_rev(void) +{ + system_rev = get_cpu_rev(); + + return system_rev; +} + +int dram_init(void) +{ +#ifdef CONFIG_SYS_ARM_WITHOUT_RELOC + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1, + PHYS_SDRAM_1_SIZE); +#if (CONFIG_NR_DRAM_BANKS > 1) + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2, + PHYS_SDRAM_2_SIZE); +#endif +#else + gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, + PHYS_SDRAM_1_SIZE); +#endif + + return 0; +} + +static void setup_weim(void) +{ + struct weim *pweim = (struct weim *)WEIM_BASE_ADDR; + + pweim->csgcr1 = 0x004100b9; + pweim->csgcr2 = 0x00000001; + pweim->csrcr1 = 0x0a018000; + pweim->csrcr2 = 0; + pweim->cswcr1 = 0x0704a240; +} + +static void setup_uart(void) +{ + unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST; + /* console RX on Pin EIM_D25 */ + mxc_request_iomux(MX51_PIN_EIM_D25, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_EIM_D25, pad); + /* console TX on Pin EIM_D26 */ + mxc_request_iomux(MX51_PIN_EIM_D26, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_EIM_D26, pad); +} + +#ifdef CONFIG_MXC_SPI +void spi_io_init(void) +{ + /* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */ + mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); + + /* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */ + mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); + + /* 000: Select mux mode: ALT0 mux port: SS0 of instance: ecspi1. */ + mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0, + PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | + PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); + + /* + * SS1 will be used as GPIO because of uninterrupted + * long SPI transmissions (GPIO4_25) + */ + mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_CSPI1_SS1, + PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | + PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); + + /* 000: Select mux mode: ALT0 mux port: SS2 of instance: ecspi1. */ + mxc_request_iomux(MX51_PIN_DI1_PIN11, IOMUX_CONFIG_ALT7); + mxc_iomux_set_pad(MX51_PIN_DI1_PIN11, + PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | + PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); + + /* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */ + mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); +} + +static void reset_peripherals(int reset) +{ + if (reset) { + + /* reset_n is on NANDF_D15 */ + mxc_gpio_set(89, 0); + mxc_gpio_direction(89, MXC_GPIO_DIRECTION_OUT); + +#ifdef CONFIG_VISION2_HW_1_0 + /* + * set FEC Configuration lines + * set levels of FEC config lines + */ + mxc_gpio_set(75, 0); + mxc_gpio_set(74, 1); + mxc_gpio_set(95, 1); + mxc_gpio_direction(75, MXC_GPIO_DIRECTION_OUT); + mxc_gpio_direction(74, MXC_GPIO_DIRECTION_OUT); + mxc_gpio_direction(95, MXC_GPIO_DIRECTION_OUT); + + /* set direction of FEC config lines */ + mxc_gpio_set(59, 0); + mxc_gpio_set(60, 0); + mxc_gpio_set(61, 0); + mxc_gpio_set(55, 1); + mxc_gpio_direction(59, MXC_GPIO_DIRECTION_OUT); + mxc_gpio_direction(60, MXC_GPIO_DIRECTION_OUT); + mxc_gpio_direction(61, MXC_GPIO_DIRECTION_OUT); + mxc_gpio_direction(55, MXC_GPIO_DIRECTION_OUT); + + /* FEC_RXD1 - sel GPIO (2-23) for configuration -> 1 */ + mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT1); + /* FEC_RXD2 - sel GPIO (2-27) for configuration -> 0 */ + mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT1); + /* FEC_RXD3 - sel GPIO (2-28) for configuration -> 0 */ + mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT1); + /* FEC_RXER - sel GPIO (2-29) for configuration -> 0 */ + mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT1); + /* FEC_COL - sel GPIO (3-10) for configuration -> 1 */ + mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT3); + /* FEC_RCLK - sel GPIO (3-11) for configuration -> 0 */ + mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT3); + /* FEC_RXD0 - sel GPIO (3-31) for configuration -> 1 */ + mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT3); +#endif + + /* + * activate reset_n pin + * Select mux mode: ALT3 mux port: NAND D15 + */ + mxc_request_iomux(MX51_PIN_NANDF_D15, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_NANDF_D15, + PAD_CTL_DRV_VOT_HIGH | PAD_CTL_DRV_MAX); + } else { + /* set FEC Control lines */ + mxc_gpio_direction(89, MXC_GPIO_DIRECTION_IN); + udelay(500); + +#ifdef CONFIG_VISION2_HW_1_0 + /* FEC RDATA[3] */ + mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180); + + /* FEC RDATA[2] */ + mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180); + + /* FEC RDATA[1] */ + mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180); + + /* FEC RDATA[0] */ + mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180); + + /* FEC RX_CLK */ + mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180); + + /* FEC RX_ER */ + mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180); + + /* FEC COL */ + mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180); +#endif + } +} + +static void power_init_mx51(void) +{ + unsigned int val; + + /* Write needed to Power Gate 2 register */ + val = pmic_reg_read(REG_POWER_MISC); + + /* enable VCAM with 2.775V to enable read from PMIC */ + val = VCAMCONFIG | VCAMEN; + pmic_reg_write(REG_MODE_1, val); + + /* + * Set switchers in Auto in NORMAL mode & STANDBY mode + * Setup the switcher mode for SW1 & SW2 + */ + val = pmic_reg_read(REG_SW_4); + val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) | + (SWMODE_MASK << SWMODE2_SHIFT))); + val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) | + (SWMODE_AUTO_AUTO << SWMODE2_SHIFT); + pmic_reg_write(REG_SW_4, val); + + /* Setup the switcher mode for SW3 & SW4 */ + val = pmic_reg_read(REG_SW_5); + val &= ~((SWMODE_MASK << SWMODE4_SHIFT) | + (SWMODE_MASK << SWMODE3_SHIFT)); + val |= (SWMODE_AUTO_AUTO << SWMODE4_SHIFT) | + (SWMODE_AUTO_AUTO << SWMODE3_SHIFT); + pmic_reg_write(REG_SW_5, val); + + + /* Set VGEN3 to 1.8V, VCAM to 3.0V */ + val = pmic_reg_read(REG_SETTING_0); + val &= ~(VCAM_MASK | VGEN3_MASK); + val |= VCAM_3_0; + pmic_reg_write(REG_SETTING_0, val); + + /* Set VVIDEO to 2.775V, VAUDIO to 3V0, VSD to 1.8V */ + val = pmic_reg_read(REG_SETTING_1); + val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK); + val |= VVIDEO_2_775 | VAUDIO_3_0 | VSD_1_8; + pmic_reg_write(REG_SETTING_1, val); + + /* Configure VGEN3 and VCAM regulators to use external PNP */ + val = VGEN3CONFIG | VCAMCONFIG; + pmic_reg_write(REG_MODE_1, val); + udelay(200); + + /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */ + val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG | + VVIDEOEN | VAUDIOEN | VSDEN; + pmic_reg_write(REG_MODE_1, val); + + val = pmic_reg_read(REG_POWER_CTL2); + val |= WDIRESET; + pmic_reg_write(REG_POWER_CTL2, val); + + udelay(2500); + +} +#endif + +static void setup_gpios(void) +{ + unsigned int i; + + /* CAM_SUP_DISn, GPIO1_7 */ + mxc_request_iomux(MX51_PIN_GPIO1_7, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_GPIO1_7, 0x82); + + /* DAB Display EN, GPIO3_1 */ + mxc_request_iomux(MX51_PIN_DI1_PIN12, IOMUX_CONFIG_ALT4); + mxc_iomux_set_pad(MX51_PIN_DI1_PIN12, 0x82); + + /* WDOG_TRIGGER, GPIO3_2 */ + mxc_request_iomux(MX51_PIN_DI1_PIN13, IOMUX_CONFIG_ALT4); + mxc_iomux_set_pad(MX51_PIN_DI1_PIN13, 0x82); + + /* Now we need to trigger the watchdog */ + WATCHDOG_RESET(); + + /* Display2 TxEN, GPIO3_3 */ + mxc_request_iomux(MX51_PIN_DI1_D0_CS, IOMUX_CONFIG_ALT4); + mxc_iomux_set_pad(MX51_PIN_DI1_D0_CS, 0x82); + + /* DAB Light EN, GPIO3_4 */ + mxc_request_iomux(MX51_PIN_DI1_D1_CS, IOMUX_CONFIG_ALT4); + mxc_iomux_set_pad(MX51_PIN_DI1_D1_CS, 0x82); + + /* AUDIO_MUTE, GPIO3_5 */ + mxc_request_iomux(MX51_PIN_DISPB2_SER_DIN, IOMUX_CONFIG_ALT4); + mxc_iomux_set_pad(MX51_PIN_DISPB2_SER_DIN, 0x82); + + /* SPARE_OUT, GPIO3_6 */ + mxc_request_iomux(MX51_PIN_DISPB2_SER_DIO, IOMUX_CONFIG_ALT4); + mxc_iomux_set_pad(MX51_PIN_DISPB2_SER_DIO, 0x82); + + /* BEEPER_EN, GPIO3_26 */ + mxc_request_iomux(MX51_PIN_NANDF_D14, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_NANDF_D14, 0x82); + + /* POWER_OFF, GPIO3_27 */ + mxc_request_iomux(MX51_PIN_NANDF_D13, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_NANDF_D13, 0x82); + + /* FRAM_WE, GPIO3_30 */ + mxc_request_iomux(MX51_PIN_NANDF_D10, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_NANDF_D10, 0x82); + + /* EXPANSION_EN, GPIO4_26 */ + mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, 0x82); + + /* + * Set GPIO1_4 to high and output; it is used to reset + * the system on reboot + */ + mxc_gpio_set(4, 1); + mxc_gpio_direction(4, MXC_GPIO_DIRECTION_OUT); + + mxc_gpio_set(7, 0); + mxc_gpio_direction(7, MXC_GPIO_DIRECTION_OUT); + for (i = 65; i < 71; i++) { + mxc_gpio_set(i, 0); + mxc_gpio_direction(i, MXC_GPIO_DIRECTION_OUT); + } + + mxc_gpio_set(94, 0); + mxc_gpio_direction(94, MXC_GPIO_DIRECTION_OUT); + + /* Set POWER_OFF high */ + mxc_gpio_set(91, 1); + mxc_gpio_direction(91, MXC_GPIO_DIRECTION_OUT); + + mxc_gpio_set(90, 0); + mxc_gpio_direction(90, MXC_GPIO_DIRECTION_OUT); + + mxc_gpio_set(122, 0); + mxc_gpio_direction(122, MXC_GPIO_DIRECTION_OUT); + + mxc_gpio_set(121, 1); + mxc_gpio_direction(121, MXC_GPIO_DIRECTION_OUT); + + WATCHDOG_RESET(); +} + +static void setup_fec(void) +{ + /*FEC_MDIO*/ + mxc_request_iomux(MX51_PIN_EIM_EB2, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_EIM_EB2, 0x1FD); + + /*FEC_MDC*/ + mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, 0x2004); + + /* FEC RDATA[3] */ + mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180); + + /* FEC RDATA[2] */ + mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180); + + /* FEC RDATA[1] */ + mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180); + + /* FEC RDATA[0] */ + mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180); + + /* FEC TDATA[3] */ + mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, 0x2004); + + /* FEC TDATA[2] */ + mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, 0x2004); + + /* FEC TDATA[1] */ + mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, 0x2004); + + /* FEC TDATA[0] */ + mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_NANDF_D8, 0x2004); + + /* FEC TX_EN */ + mxc_request_iomux(MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_CS7, 0x2004); + + /* FEC TX_ER */ + mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, 0x2004); + + /* FEC TX_CLK */ + mxc_request_iomux(MX51_PIN_NANDF_RDY_INT, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_RDY_INT, 0x2180); + + /* FEC TX_COL */ + mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180); + + /* FEC RX_CLK */ + mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180); + + /* FEC RX_CRS */ + mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_EIM_CS5, 0x180); + + /* FEC RX_ER */ + mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180); + + /* FEC RX_DV */ + mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX51_PIN_NANDF_D11, 0x2180); +} + +struct fsl_esdhc_cfg esdhc_cfg[1] = { + {MMC_SDHC1_BASE_ADDR, 1}, +}; + +int get_mmc_getcd(u8 *cd, struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + + if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) + *cd = mxc_gpio_get(0); + else + *cd = 0; + + return 0; +} + +#ifdef CONFIG_FSL_ESDHC +int board_mmc_init(bd_t *bis) +{ + mxc_request_iomux(MX51_PIN_SD1_CMD, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX51_PIN_SD1_CLK, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX51_PIN_SD1_DATA0, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX51_PIN_SD1_DATA1, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX51_PIN_SD1_DATA2, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_request_iomux(MX51_PIN_SD1_DATA3, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_iomux_set_pad(MX51_PIN_SD1_CMD, + PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | + PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_SD1_CLK, + PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_NONE | PAD_CTL_47K_PU | + PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_SD1_DATA0, + PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | + PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_SD1_DATA1, + PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | + PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_SD1_DATA2, + PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | + PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_SD1_DATA3, + PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | + PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD | + PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + mxc_request_iomux(MX51_PIN_GPIO1_0, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_iomux_set_pad(MX51_PIN_GPIO1_0, + PAD_CTL_HYS_ENABLE); + mxc_request_iomux(MX51_PIN_GPIO1_1, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_iomux_set_pad(MX51_PIN_GPIO1_1, + PAD_CTL_HYS_ENABLE); + + return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); +} +#endif + +int board_early_init_f(void) +{ + + + init_drive_strength(); + + /* Setup debug led */ + mxc_gpio_set(6, 0); + mxc_gpio_direction(6, MXC_GPIO_DIRECTION_OUT); + mxc_request_iomux(MX51_PIN_GPIO1_6, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_GPIO1_6, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); + + /* wait a little while to give the pll time to settle */ + sdelay(100000); + + setup_weim(); + setup_uart(); + setup_fec(); + setup_gpios(); + + spi_io_init(); + + return 0; +} + +int board_init(void) +{ +#ifdef CONFIG_SYS_ARM_WITHOUT_RELOC + board_early_init_f(); +#endif + gd->bd->bi_arch_number = MACH_TYPE_TTC_VISION2; /* board id for linux */ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + return 0; +} + +int board_late_init(void) +{ + power_init_mx51(); + + reset_peripherals(1); + udelay(2000); + reset_peripherals(0); + udelay(2000); + + /* Early revisions require a second reset */ +#ifdef CONFIG_VISION2_HW_1_0 + reset_peripherals(1); + udelay(2000); + reset_peripherals(0); + udelay(2000); +#endif + + return 0; +} + +int checkboard(void) +{ + u32 system_rev = get_cpu_rev(); + u32 cause; + struct src *src_regs = (struct src *)SRC_BASE_ADDR; + + puts("Board: TTControl Vision II CPU V"); + + switch (system_rev & 0xff) { + case CHIP_REV_3_0: + puts("3.0 ["); + break; + case CHIP_REV_2_5: + puts("2.5 ["); + break; + case CHIP_REV_2_0: + puts("2.0 ["); + break; + case CHIP_REV_1_1: + puts("1.1 ["); + break; + case CHIP_REV_1_0: + default: + puts("1.0 ["); + break; + } + + cause = src_regs->srsr; + switch (cause) { + case 0x0001: + puts("POR"); + break; + case 0x0009: + puts("RST"); + break; + case 0x0010: + case 0x0011: + puts("WDOG"); + break; + default: + printf("unknown 0x%x", cause); + } + puts("]\n"); + + return 0; +} + diff --git a/boards.cfg b/boards.cfg index 202de1a188..62ffa420ee 100644 --- a/boards.cfg +++ b/boards.cfg @@ -47,6 +47,7 @@ jadecpu arm arm926ejs jadecpu syteco mb86r0x suen3 arm arm926ejs km_arm keymile kirkwood rd6281a arm arm926ejs - Marvell kirkwood mx51evk arm armv7 mx51evk freescale mx51 +vision2 arm armv7 vision2 ttcontrol mx51 actux1 arm ixp actux2 arm ixp actux3 arm ixp diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 07d395d898..a0f455223b 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -27,7 +27,7 @@ LIB := $(obj)libgpio.a COBJS-$(CONFIG_AT91_GPIO) += at91_gpio.o COBJS-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o -COBJS-$(CONFIG_MX31_GPIO) += mx31_gpio.o +COBJS-$(CONFIG_MXC_GPIO) += mxc_gpio.o COBJS-$(CONFIG_PCA953X) += pca953x.o COBJS-$(CONFIG_S5P) += s5p_gpio.o diff --git a/drivers/gpio/mx31_gpio.c b/drivers/gpio/mxc_gpio.c index b07f038156..663141f1b4 100644 --- a/drivers/gpio/mx31_gpio.c +++ b/drivers/gpio/mxc_gpio.c @@ -21,19 +21,29 @@ * MA 02111-1307 USA */ #include <common.h> -#include <asm/arch/mx31.h> +#ifdef CONFIG_MX31 #include <asm/arch/mx31-regs.h> +#endif +#ifdef CONFIG_MX51 +#include <asm/arch/imx-regs.h> +#endif +#include <asm/io.h> +#include <mxc_gpio.h> /* GPIO port description */ static unsigned long gpio_ports[] = { - [0] = GPIO1_BASE, - [1] = GPIO2_BASE, - [2] = GPIO3_BASE, + [0] = GPIO1_BASE_ADDR, + [1] = GPIO2_BASE_ADDR, + [2] = GPIO3_BASE_ADDR, +#ifdef CONFIG_MX51 + [3] = GPIO4_BASE_ADDR, +#endif }; -int mx31_gpio_direction(unsigned int gpio, enum mx31_gpio_direction direction) +int mxc_gpio_direction(unsigned int gpio, enum mxc_gpio_direction direction) { unsigned int port = gpio >> 5; + struct gpio_regs *regs; u32 l; if (port >= ARRAY_SIZE(gpio_ports)) @@ -41,22 +51,26 @@ int mx31_gpio_direction(unsigned int gpio, enum mx31_gpio_direction direction) gpio &= 0x1f; - l = __REG(gpio_ports[port] + GPIO_GDIR); + regs = (struct gpio_regs *)gpio_ports[port]; + + l = readl(®s->gpio_dir); + switch (direction) { - case MX31_GPIO_DIRECTION_OUT: + case MXC_GPIO_DIRECTION_OUT: l |= 1 << gpio; break; - case MX31_GPIO_DIRECTION_IN: + case MXC_GPIO_DIRECTION_IN: l &= ~(1 << gpio); } - __REG(gpio_ports[port] + GPIO_GDIR) = l; + writel(l, ®s->gpio_dir); return 0; } -void mx31_gpio_set(unsigned int gpio, unsigned int value) +void mxc_gpio_set(unsigned int gpio, unsigned int value) { unsigned int port = gpio >> 5; + struct gpio_regs *regs; u32 l; if (port >= ARRAY_SIZE(gpio_ports)) @@ -64,17 +78,20 @@ void mx31_gpio_set(unsigned int gpio, unsigned int value) gpio &= 0x1f; - l = __REG(gpio_ports[port] + GPIO_DR); + regs = (struct gpio_regs *)gpio_ports[port]; + + l = readl(®s->gpio_dr); if (value) l |= 1 << gpio; else l &= ~(1 << gpio); - __REG(gpio_ports[port] + GPIO_DR) = l; + writel(l, ®s->gpio_dr); } -int mx31_gpio_get(unsigned int gpio) +int mxc_gpio_get(unsigned int gpio) { unsigned int port = gpio >> 5; + struct gpio_regs *regs; u32 l; if (port >= ARRAY_SIZE(gpio_ports)) @@ -82,7 +99,9 @@ int mx31_gpio_get(unsigned int gpio) gpio &= 0x1f; - l = (__REG(gpio_ports[port] + GPIO_DR) >> gpio) & 0x01; + regs = (struct gpio_regs *)gpio_ports[port]; + + l = (readl(®s->gpio_dr) >> gpio) & 0x01; return l; } diff --git a/drivers/misc/fsl_pmic.c b/drivers/misc/fsl_pmic.c index dca0a1d57e..5ee1de176e 100644 --- a/drivers/misc/fsl_pmic.c +++ b/drivers/misc/fsl_pmic.c @@ -46,6 +46,7 @@ void pmic_spi_free(struct spi_slave *slave) u32 pmic_reg(u32 reg, u32 val, u32 write) { u32 pmic_tx, pmic_rx; + u32 tmp; if (!slave) { slave = pmic_spi_probe(); @@ -65,7 +66,9 @@ u32 pmic_reg(u32 reg, u32 val, u32 write) pmic_tx = (write << 31) | (reg << 25) | (val & 0x00FFFFFF); - if (spi_xfer(slave, 4 << 3, &pmic_tx, &pmic_rx, + tmp = cpu_to_be32(pmic_tx); + + if (spi_xfer(slave, 4 << 3, &tmp, &pmic_rx, SPI_XFER_BEGIN | SPI_XFER_END)) { spi_release_bus(slave); return -1; @@ -73,7 +76,8 @@ u32 pmic_reg(u32 reg, u32 val, u32 write) if (write) { pmic_tx &= ~(1 << 31); - if (spi_xfer(slave, 4 << 3, &pmic_tx, &pmic_rx, + tmp = cpu_to_be32(pmic_tx); + if (spi_xfer(slave, 4 << 3, &tmp, &pmic_rx, SPI_XFER_BEGIN | SPI_XFER_END)) { spi_release_bus(slave); return -1; @@ -81,7 +85,7 @@ u32 pmic_reg(u32 reg, u32 val, u32 write) } spi_release_bus(slave); - return pmic_rx; + return cpu_to_be32(pmic_rx); } void pmic_reg_write(u32 reg, u32 value) diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c index 4b93e7b97f..f96b21f7b1 100644 --- a/drivers/serial/serial_mxc.c +++ b/drivers/serial/serial_mxc.c @@ -18,6 +18,7 @@ */ #include <common.h> +#include <watchdog.h> #ifdef CONFIG_MX31 #include <asm/arch/mx31.h> #else @@ -189,7 +190,8 @@ void serial_setbrg (void) int serial_getc (void) { - while (__REG(UART_PHYS + UTS) & UTS_RXEMPTY); + while (__REG(UART_PHYS + UTS) & UTS_RXEMPTY) + WATCHDOG_RESET(); return (__REG(UART_PHYS + URXD) & URXD_RX_DATA); /* mask out status from upper word */ } @@ -198,7 +200,8 @@ void serial_putc (const char c) __REG(UART_PHYS + UTXD) = c; /* wait for transmitter to be ready */ - while(!(__REG(UART_PHYS + UTS) & UTS_TXEMPTY)); + while (!(__REG(UART_PHYS + UTS) & UTS_TXEMPTY)) + WATCHDOG_RESET(); /* If \n, also do \r */ if (c == '\n') diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c index e15a63caca..d558137c9d 100644 --- a/drivers/spi/mxc_spi.c +++ b/drivers/spi/mxc_spi.c @@ -23,6 +23,7 @@ #include <spi.h> #include <asm/errno.h> #include <asm/io.h> +#include <mxc_gpio.h> #ifdef CONFIG_MX27 /* i.MX27 has a completely wrong register layout and register definitions in the @@ -61,6 +62,7 @@ #define MXC_CSPICTRL_MAXBITS 0x1f #define MXC_CSPIPERIOD_32KHZ (1 << 15) +#define MAX_SPI_BYTES 4 static unsigned long spi_bases[] = { 0x43fa4000, @@ -68,9 +70,6 @@ static unsigned long spi_bases[] = { 0x53f84000, }; -#define OUT MX31_GPIO_DIRECTION_OUT -#define mxc_gpio_direction mx31_gpio_direction -#define mxc_gpio_set mx31_gpio_set #elif defined(CONFIG_MX51) #include <asm/arch/imx-regs.h> #include <asm/arch/clock.h> @@ -97,6 +96,7 @@ static unsigned long spi_bases[] = { #define MXC_CSPICTRL_RXOVF (1 << 6) #define MXC_CSPIPERIOD_32KHZ (1 << 15) +#define MAX_SPI_BYTES 32 /* Bit position inside CTRL register to be associated with SS */ #define MXC_CSPICTRL_CHAN 18 @@ -111,13 +111,12 @@ static unsigned long spi_bases[] = { CSPI2_BASE_ADDR, CSPI3_BASE_ADDR, }; -#define mxc_gpio_direction(gpio, dir) (0) -#define mxc_gpio_set(gpio, value) {} -#define OUT 1 #else #error "Unsupported architecture" #endif +#define OUT MXC_GPIO_DIRECTION_OUT + struct mxc_spi_slave { struct spi_slave slave; unsigned long base; @@ -126,6 +125,7 @@ struct mxc_spi_slave { u32 cfg_reg; #endif int gpio; + int ss_pol; }; static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave) @@ -147,7 +147,7 @@ void spi_cs_activate(struct spi_slave *slave) { struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); if (mxcs->gpio > 0) - mxc_gpio_set(mxcs->gpio, mxcs->ctrl_reg & MXC_CSPICTRL_SSPOL); + mxc_gpio_set(mxcs->gpio, mxcs->ss_pol); } void spi_cs_deactivate(struct spi_slave *slave) @@ -155,7 +155,7 @@ void spi_cs_deactivate(struct spi_slave *slave) struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); if (mxcs->gpio > 0) mxc_gpio_set(mxcs->gpio, - !(mxcs->ctrl_reg & MXC_CSPICTRL_SSPOL)); + !(mxcs->ss_pol)); } #ifdef CONFIG_MX51 @@ -217,7 +217,7 @@ static s32 spi_cfg(struct mxc_spi_slave *mxcs, unsigned int cs, if (mode & SPI_CS_HIGH) ss_pol = 1; - if (!(mode & SPI_CPOL)) + if (mode & SPI_CPOL) sclkpol = 1; if (mode & SPI_CPHA) @@ -254,13 +254,15 @@ static s32 spi_cfg(struct mxc_spi_slave *mxcs, unsigned int cs, } #endif -static u32 spi_xchg_single(struct spi_slave *slave, u32 data, int bitlen, - unsigned long flags) +int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen, + const u8 *dout, u8 *din, unsigned long flags) { struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); + int nbytes = (bitlen + 7) / 8; + u32 data, cnt, i; - if (flags & SPI_XFER_BEGIN) - spi_cs_activate(slave); + debug("%s: bitlen %d dout 0x%x din 0x%x\n", + __func__, bitlen, (u32)dout, (u32)din); mxcs->ctrl_reg = (mxcs->ctrl_reg & ~MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS)) | @@ -275,8 +277,46 @@ static u32 spi_xchg_single(struct spi_slave *slave, u32 data, int bitlen, reg_write(mxcs->base + MXC_CSPISTAT, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); - debug("Sending SPI 0x%x\n", data); - reg_write(mxcs->base + MXC_CSPITXDATA, data); + /* + * The SPI controller works only with words, + * check if less than a word is sent. + * Access to the FIFO is only 32 bit + */ + if (bitlen % 32) { + data = 0; + cnt = (bitlen % 32) / 8; + if (dout) { + for (i = 0; i < cnt; i++) { + data = (data << 8) | (*dout++ & 0xFF); + } + } + debug("Sending SPI 0x%x\n", data); + + reg_write(mxcs->base + MXC_CSPITXDATA, data); + nbytes -= cnt; + } + + data = 0; + + while (nbytes > 0) { + data = 0; + if (dout) { + /* Buffer is not 32-bit aligned */ + if ((unsigned long)dout & 0x03) { + data = 0; + for (i = 0; i < 4; i++, data <<= 8) { + data = (data << 8) | (*dout++ & 0xFF); + } + } else { + data = *(u32 *)dout; + data = cpu_to_be32(data); + } + dout += 4; + } + debug("Sending SPI 0x%x\n", data); + reg_write(mxcs->base + MXC_CSPITXDATA, data); + nbytes -= 4; + } /* FIFO is written, now starts the transfer setting the XCH bit */ reg_write(mxcs->base + MXC_CSPICTRL, mxcs->ctrl_reg | @@ -290,49 +330,78 @@ static u32 spi_xchg_single(struct spi_slave *slave, u32 data, int bitlen, reg_write(mxcs->base + MXC_CSPISTAT, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF); - data = reg_read(mxcs->base + MXC_CSPIRXDATA); - debug("SPI Rx: 0x%x\n", data); + nbytes = (bitlen + 7) / 8; - if (flags & SPI_XFER_END) - spi_cs_deactivate(slave); + cnt = nbytes % 32; + + if (bitlen % 32) { + data = reg_read(mxcs->base + MXC_CSPIRXDATA); + cnt = (bitlen % 32) / 8; + debug("SPI Rx unaligned: 0x%x\n", data); + if (din) { + for (i = 0; i < cnt; i++, data >>= 8) { + *din++ = data & 0xFF; + } + } + nbytes -= cnt; + } - return data; + while (nbytes > 0) { + u32 tmp; + tmp = reg_read(mxcs->base + MXC_CSPIRXDATA); + data = cpu_to_be32(tmp); + debug("SPI Rx: 0x%x 0x%x\n", tmp, data); + cnt = min(nbytes, sizeof(data)); + if (din) { + memcpy(din, &data, cnt); + din += cnt; + } + nbytes -= cnt; + } + + return 0; } + int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, void *din, unsigned long flags) { - int n_blks = (bitlen + 31) / 32; - u32 *out_l, *in_l; - int i; + int n_bytes = (bitlen + 7) / 8; + int n_bits; + int ret; + u32 blk_size; + u8 *p_outbuf = (u8 *)dout; + u8 *p_inbuf = (u8 *)din; - if ((int)dout & 3 || (int)din & 3) { - printf("Error: unaligned buffers in: %p, out: %p\n", din, dout); - return 1; - } + if (!slave) + return -1; + + if (flags & SPI_XFER_BEGIN) + spi_cs_activate(slave); + + while (n_bytes > 0) { + + if (n_bytes < MAX_SPI_BYTES) + blk_size = n_bytes; + else + blk_size = MAX_SPI_BYTES; + + n_bits = blk_size * 8; - /* This driver is currently partly broken, alert the user */ - if (bitlen > 16 && (bitlen % 32)) { - printf("Error: SPI transfer with bitlen=%d is broken.\n", - bitlen); - return 1; + ret = spi_xchg_single(slave, n_bits, p_outbuf, p_inbuf, 0); + + if (ret) + return ret; + if (dout) + p_outbuf += blk_size; + if (din) + p_inbuf += blk_size; + n_bytes -= blk_size; } - for (i = 0, in_l = (u32 *)din, out_l = (u32 *)dout; - i < n_blks; - i++, in_l++, out_l++, bitlen -= 32) { - u32 data = spi_xchg_single(slave, *out_l, bitlen, flags); - - /* Check if we're only transfering 8 or 16 bits */ - if (!i) { - if (bitlen < 9) - *(u8 *)din = data; - else if (bitlen < 17) - *(u16 *)din = data; - else - *in_l = data; - } + if (flags & SPI_XFER_END) { + spi_cs_deactivate(slave); } return 0; @@ -380,8 +449,10 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, return NULL; mxcs = malloc(sizeof(struct mxc_spi_slave)); - if (!mxcs) + if (!mxcs) { + puts("mxc_spi: SPI Slave not allocated !\n"); return NULL; + } ret = decode_cs(mxcs, cs); if (ret < 0) { @@ -394,6 +465,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, mxcs->slave.bus = bus; mxcs->slave.cs = cs; mxcs->base = spi_bases[bus]; + mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0; #ifdef CONFIG_MX51 /* Can be used for i.MX31 too ? */ @@ -413,7 +485,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, if (mode & SPI_CPHA) ctrl_reg |= MXC_CSPICTRL_PHA; - if (!(mode & SPI_CPOL)) + if (mode & SPI_CPOL) ctrl_reg |= MXC_CSPICTRL_POL; if (mode & SPI_CS_HIGH) ctrl_reg |= MXC_CSPICTRL_SSPOL; diff --git a/include/configs/imx31_litekit.h b/include/configs/imx31_litekit.h index 49048563cb..88c62d11e1 100644 --- a/include/configs/imx31_litekit.h +++ b/include/configs/imx31_litekit.h @@ -66,13 +66,13 @@ #define CONFIG_HARD_SPI 1 #define CONFIG_MXC_SPI 1 #define CONFIG_DEFAULT_SPI_BUS 1 -#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH) +#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH) #define CONFIG_FSL_PMIC #define CONFIG_FSL_PMIC_BUS 1 #define CONFIG_FSL_PMIC_CS 0 #define CONFIG_FSL_PMIC_CLK 1000000 -#define CONFIG_FSL_PMIC_MODE (SPI_MODE_2 | SPI_CS_HIGH) +#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) #define CONFIG_RTC_MC13783 1 diff --git a/include/configs/imx31_phycore.h b/include/configs/imx31_phycore.h index 1dbafa0521..62944a93f6 100644 --- a/include/configs/imx31_phycore.h +++ b/include/configs/imx31_phycore.h @@ -183,7 +183,7 @@ #ifdef CONFIG_IMX31_PHYCORE_EET #define BOARD_LATE_INIT -#define CONFIG_MX31_GPIO 1 +#define CONFIG_MXC_GPIO #define CONFIG_HARD_SPI 1 #define CONFIG_MXC_SPI 1 diff --git a/include/configs/mx31ads.h b/include/configs/mx31ads.h index dedecd7fb6..57955dfc3b 100644 --- a/include/configs/mx31ads.h +++ b/include/configs/mx31ads.h @@ -63,13 +63,13 @@ #define CONFIG_HARD_SPI 1 #define CONFIG_MXC_SPI 1 #define CONFIG_DEFAULT_SPI_BUS 1 -#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH) +#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH) #define CONFIG_FSL_PMIC #define CONFIG_FSL_PMIC_BUS 1 #define CONFIG_FSL_PMIC_CS 0 #define CONFIG_FSL_PMIC_CLK 1000000 -#define CONFIG_FSL_PMIC_MODE (SPI_MODE_2 | SPI_CS_HIGH) +#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) #define CONFIG_RTC_MC13783 1 /* allow to overwrite serial and ethaddr */ diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h index 0414cc37a7..4b4fb1a06a 100644 --- a/include/configs/mx31pdk.h +++ b/include/configs/mx31pdk.h @@ -67,13 +67,13 @@ #define CONFIG_HARD_SPI 1 #define CONFIG_MXC_SPI 1 #define CONFIG_DEFAULT_SPI_BUS 1 -#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH) +#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH) #define CONFIG_FSL_PMIC #define CONFIG_FSL_PMIC_BUS 1 #define CONFIG_FSL_PMIC_CS 2 #define CONFIG_FSL_PMIC_CLK 1000000 -#define CONFIG_FSL_PMIC_MODE (SPI_MODE_2 | SPI_CS_HIGH) +#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) #define CONFIG_RTC_MC13783 1 /* allow to overwrite serial and ethaddr */ diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index 86a4731a69..8864f3ab78 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -73,7 +73,7 @@ #define CONFIG_FSL_PMIC_BUS 0 #define CONFIG_FSL_PMIC_CS 0 #define CONFIG_FSL_PMIC_CLK 2500000 -#define CONFIG_FSL_PMIC_MODE (SPI_CPOL | SPI_CS_HIGH) +#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) /* * MMC Configs diff --git a/include/configs/qong.h b/include/configs/qong.h index 7a68b7b97e..cbb53dd3d2 100644 --- a/include/configs/qong.h +++ b/include/configs/qong.h @@ -52,18 +52,18 @@ #define CONFIG_MXC_UART 1 #define CONFIG_SYS_MX31_UART1 1 -#define CONFIG_MX31_GPIO +#define CONFIG_MXC_GPIO #define CONFIG_MXC_SPI #define CONFIG_DEFAULT_SPI_BUS 1 -#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH) +#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH) #define CONFIG_RTC_MC13783 #define CONFIG_FSL_PMIC #define CONFIG_FSL_PMIC_BUS 1 #define CONFIG_FSL_PMIC_CS 0 #define CONFIG_FSL_PMIC_CLK 100000 -#define CONFIG_FSL_PMIC_MODE (SPI_MODE_2 | SPI_CS_HIGH) +#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) /* FPGA */ #define CONFIG_QONG_FPGA 1 diff --git a/include/configs/vision2.h b/include/configs/vision2.h new file mode 100644 index 0000000000..44a6f8be69 --- /dev/null +++ b/include/configs/vision2.h @@ -0,0 +1,214 @@ +/* + * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> + * + * (C) Copyright 2009 Freescale Semiconductor, Inc. + * + * Configuration settings for the MX51-3Stack Freescale board. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/arch/imx-regs.h> + +#define CONFIG_MX51 /* in a mx51 */ +#define CONFIG_L2_OFF + +#define CONFIG_MX51_HCLK_FREQ 24000000 +#define CONFIG_MX51_CLK32 32768 +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_REVISION_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define BOARD_LATE_INIT + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (2048 * 1024) + +/* size in bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +/* + * Hardware drivers + */ +#define CONFIG_MXC_UART +#define CONFIG_SYS_MX51_UART3 +#define CONFIG_MXC_GPIO +#define CONFIG_MXC_SPI +#define CONFIG_HW_WATCHDOG + + /* + * SPI Configs + * */ +#define CONFIG_FSL_SF +#define CONFIG_CMD_SF + +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO + +/* + * Use gpio 4 pin 25 as chip select for SPI flash + * This corresponds to gpio 121 + */ +#define CONFIG_SPI_FLASH_CS (1 | (121 << 8)) +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define CONFIG_SF_DEFAULT_SPEED 25000000 + +#define CONFIG_ENV_SPI_CS (1 | (121 << 8)) +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_MAX_HZ 25000000 +#define CONFIG_ENV_SPI_MODE SPI_MODE_0 + +#define CONFIG_ENV_OFFSET (6 * 64 * 1024) +#define CONFIG_ENV_SECT_SIZE (1 * 64 * 1024) +#define CONFIG_ENV_SIZE (4 * 1024) + +#define CONFIG_FSL_ENV_IN_SF +#define CONFIG_ENV_IS_IN_SPI_FLASH + +/* PMIC Controller */ +#define CONFIG_FSL_PMIC +#define CONFIG_FSL_PMIC_BUS 0 +#define CONFIG_FSL_PMIC_CS 0 +#define CONFIG_FSL_PMIC_CLK 2500000 +#define CONFIG_FSL_PMIC_MODE SPI_MODE_0 +#define CONFIG_RTC_MC13783 + +/* + * MMC Configs + */ +#define CONFIG_FSL_ESDHC +#ifdef CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR (0x70004000) +#define CONFIG_SYS_FSL_ESDHC_NUM 1 + +#define CONFIG_MMC + +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + +#define CONFIG_CMD_DATE + +/* + * Eth Configs + */ +#define CONFIG_HAS_ETH1 +#define CONFIG_NET_MULTI +#define CONFIG_MII +#define CONFIG_DISCOVER_PHY + +#define CONFIG_FEC_MXC +#define IMX_FEC_BASE FEC_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x1F + +#define CONFIG_CMD_PING +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 3 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} + +/*********************************************************** + * Command definition + ***********************************************************/ + +#include <config_cmd_default.h> + +#define CONFIG_CMD_SPI +#undef CONFIG_CMD_IMLS + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_LOADADDR 0x90800000 /* loadaddr env var */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "loadaddr=0x90800000\0" + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_PROMPT "Vision II U-boot > " +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 64 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_MEMTEST_START 0x90000000 +#define CONFIG_SYS_MEMTEST_END 0x10000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_HZ 1000 +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "Vision II U-boot > " + +/* + * Stack sizes + */ +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ + +/* + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 2 +#define PHYS_SDRAM_1 CSD0_BASE_ADDR +#define PHYS_SDRAM_1_SIZE (256 * 1024 * 1024) +#define PHYS_SDRAM_2 CSD1_BASE_ADDR +#define PHYS_SDRAM_2_SIZE (256 * 1024 * 1024) +#define CONFIG_SYS_SDRAM_BASE 0x90000000 +#define CONFIG_SYS_INIT_RAM_ADDR 0x1FFE8000 + +#ifndef CONFIG_SYS_ARM_WITHOUT_RELOC +#define CONFIG_SYS_INIT_RAM_END (64 * 1024) +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \ + CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_GBL_DATA_OFFSET) +#undef CONFIG_SKIP_RELOCATE_UBOOT +#else +#define CONFIG_SKIP_RELOCATE_UBOOT +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + 0x2000) +#endif + +#define CONFIG_BOARD_EARLY_INIT_F + +/* 166 MHz DDR RAM */ +#define CONFIG_SYS_DDR_CLKSEL 0 +#define CONFIG_SYS_CLKTL_CBCDR 0x19239100 + +#define CONFIG_SYS_NO_FLASH + +#endif /* __CONFIG_H */ diff --git a/include/mc13892.h b/include/mc13892.h index b291757412..791e3ec878 100644 --- a/include/mc13892.h +++ b/include/mc13892.h @@ -157,4 +157,7 @@ #define VSDSTBY (1 << 19) #define VSDMODE (1 << 20) +/* Reg Power Control 2*/ +#define WDIRESET (1 << 12) + #endif diff --git a/board/freescale/mx51evk/mx51evk.h b/include/mxc_gpio.h index 2854e71e8d..002ba61e00 100644 --- a/board/freescale/mx51evk/mx51evk.h +++ b/include/mxc_gpio.h @@ -1,5 +1,6 @@ /* - * (C) Copyright 2009 Freescale Semiconductor, Inc. + * + * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> * * See file CREDITS for list of people who contributed to this * project. @@ -20,31 +21,32 @@ * MA 02111-1307 USA */ -#ifndef __BOARD_FREESCALE_MX51_EVK_H__ -#define __BOARD_FREESCALE_MX51_EVK_H__ +#ifndef __MXC_GPIO_H +#define __MXC_GPIO_H -#ifndef __ASSEMBLY__ -struct io_board_ctrl { - u16 led_ctrl; /* 0x00 */ - u16 resv1[0x03]; - u16 sb_stat; /* 0x08 */ - u16 resv2[0x03]; - u16 int_stat; /* 0x10 */ - u16 resv3[0x07]; - u16 int_rest; /* 0x20 */ - u16 resv4[0x0B]; - u16 int_mask; /* 0x38 */ - u16 resv5[0x03]; - u16 id1; /* 0x40 */ - u16 resv6[0x03]; - u16 id2; /* 0x48 */ - u16 resv7[0x03]; - u16 version; /* 0x50 */ - u16 resv8[0x03]; - u16 id3; /* 0x58 */ - u16 resv9[0x03]; - u16 sw_reset; /* 0x60 */ +enum mxc_gpio_direction { + MXC_GPIO_DIRECTION_IN, + MXC_GPIO_DIRECTION_OUT, }; + +#ifdef CONFIG_MXC_GPIO +extern int mxc_gpio_direction(unsigned int gpio, + enum mxc_gpio_direction direction); +extern void mxc_gpio_set(unsigned int gpio, unsigned int value); +extern int mxc_gpio_get(unsigned int gpio); +#else +static inline int mxc_gpio_direction(unsigned int gpio, + enum mxc_gpio_direction direction) +{ + return 1; +} +static inline int mxc_gpio_get(unsigned int gpio) +{ + return 1; +} +static inline void mxc_gpio_set(unsigned int gpio, unsigned int value) +{ +} #endif #endif |
