diff options
| -rw-r--r-- | board/atmel/at91cap9adk/at91cap9adk.c | 3 | ||||
| -rw-r--r-- | board/atmel/at91sam9261ek/at91sam9261ek.c | 3 | ||||
| -rw-r--r-- | board/atmel/at91sam9263ek/at91sam9263ek.c | 3 | ||||
| -rw-r--r-- | board/atmel/at91sam9rlek/at91sam9rlek.c | 3 | ||||
| -rw-r--r-- | cpu/arm926ejs/at91/Makefile | 2 | ||||
| -rw-r--r-- | cpu/arm926ejs/at91/clock.c | 202 | ||||
| -rw-r--r-- | cpu/arm926ejs/at91/cpu.c | 14 | ||||
| -rw-r--r-- | drivers/spi/atmel_dataflash_spi.c | 7 | ||||
| -rw-r--r-- | drivers/usb/host/ohci-at91.c | 3 | ||||
| -rw-r--r-- | include/asm-arm/arch-at91/at91_pmc.h | 30 | ||||
| -rw-r--r-- | include/asm-arm/arch-at91/clk.h | 19 | ||||
| -rw-r--r-- | include/asm-arm/arch-at91/hardware.h | 3 | ||||
| -rw-r--r-- | include/asm-arm/u-boot-arm.h | 3 | ||||
| -rw-r--r-- | include/configs/afeb9260.h | 5 | ||||
| -rw-r--r-- | include/configs/at91cap9adk.h | 6 | ||||
| -rw-r--r-- | include/configs/at91sam9260ek.h | 8 | ||||
| -rw-r--r-- | include/configs/at91sam9261ek.h | 5 | ||||
| -rw-r--r-- | include/configs/at91sam9263ek.h | 6 | ||||
| -rw-r--r-- | include/configs/at91sam9rlek.h | 5 | ||||
| -rw-r--r-- | lib_arm/board.c | 3 |
20 files changed, 285 insertions, 48 deletions
diff --git a/board/atmel/at91cap9adk/at91cap9adk.c b/board/atmel/at91cap9adk/at91cap9adk.c index e8025e7aed..f52edaaa03 100644 --- a/board/atmel/at91cap9adk/at91cap9adk.c +++ b/board/atmel/at91cap9adk/at91cap9adk.c @@ -29,6 +29,7 @@ #include <asm/arch/at91_common.h> #include <asm/arch/at91_pmc.h> #include <asm/arch/at91_rstc.h> +#include <asm/arch/clk.h> #include <asm/arch/gpio.h> #include <asm/arch/io.h> #include <asm/arch/hardware.h> @@ -283,7 +284,7 @@ void lcd_show_board_info(void) lcd_printf ("at91support@atmel.com\n"); lcd_printf ("%s CPU at %s MHz\n", AT91_CPU_NAME, - strmhz(temp, AT91_CPU_CLOCK)); + strmhz(temp, get_cpu_clk_rate())); dram_size = 0; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) diff --git a/board/atmel/at91sam9261ek/at91sam9261ek.c b/board/atmel/at91sam9261ek/at91sam9261ek.c index bae4092bb6..a89cb8bf27 100644 --- a/board/atmel/at91sam9261ek/at91sam9261ek.c +++ b/board/atmel/at91sam9261ek/at91sam9261ek.c @@ -29,6 +29,7 @@ #include <asm/arch/at91_common.h> #include <asm/arch/at91_pmc.h> #include <asm/arch/at91_rstc.h> +#include <asm/arch/clk.h> #include <asm/arch/gpio.h> #include <asm/arch/io.h> #include <lcd.h> @@ -185,7 +186,7 @@ void lcd_show_board_info(void) lcd_printf ("at91support@atmel.com\n"); lcd_printf ("%s CPU at %s MHz\n", AT91_CPU_NAME, - strmhz(temp, AT91_CPU_CLOCK)); + strmhz(temp, get_cpu_clk_rate())); dram_size = 0; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) diff --git a/board/atmel/at91sam9263ek/at91sam9263ek.c b/board/atmel/at91sam9263ek/at91sam9263ek.c index 1d5284592e..57d5c953f7 100644 --- a/board/atmel/at91sam9263ek/at91sam9263ek.c +++ b/board/atmel/at91sam9263ek/at91sam9263ek.c @@ -30,6 +30,7 @@ #include <asm/arch/at91_common.h> #include <asm/arch/at91_pmc.h> #include <asm/arch/at91_rstc.h> +#include <asm/arch/clk.h> #include <asm/arch/gpio.h> #include <asm/arch/io.h> #include <asm/arch/hardware.h> @@ -206,7 +207,7 @@ void lcd_show_board_info(void) lcd_printf ("at91support@atmel.com\n"); lcd_printf ("%s CPU at %s MHz\n", AT91_CPU_NAME, - strmhz(temp, AT91_CPU_CLOCK)); + strmhz(temp, get_cpu_clk_rate())); dram_size = 0; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) diff --git a/board/atmel/at91sam9rlek/at91sam9rlek.c b/board/atmel/at91sam9rlek/at91sam9rlek.c index 908b9c801b..7013ba2b13 100644 --- a/board/atmel/at91sam9rlek/at91sam9rlek.c +++ b/board/atmel/at91sam9rlek/at91sam9rlek.c @@ -29,6 +29,7 @@ #include <asm/arch/at91_common.h> #include <asm/arch/at91_pmc.h> #include <asm/arch/at91_rstc.h> +#include <asm/arch/clk.h> #include <asm/arch/gpio.h> #include <asm/arch/io.h> #include <lcd.h> @@ -157,7 +158,7 @@ void lcd_show_board_info(void) lcd_printf ("at91support@atmel.com\n"); lcd_printf ("%s CPU at %s MHz\n", AT91_CPU_NAME, - strmhz(temp, AT91_CPU_CLOCK)); + strmhz(temp, get_cpu_clk_rate())); dram_size = 0; for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) diff --git a/cpu/arm926ejs/at91/Makefile b/cpu/arm926ejs/at91/Makefile index 34e746182a..3d45c427cc 100644 --- a/cpu/arm926ejs/at91/Makefile +++ b/cpu/arm926ejs/at91/Makefile @@ -55,6 +55,8 @@ COBJS-y += at91sam9rl_serial.o COBJS-$(CONFIG_HAS_DATAFLASH) += at91sam9rl_spi.o endif COBJS-$(CONFIG_AT91_LED) += led.o +COBJS-y += clock.o +COBJS-y += cpu.o COBJS-y += timer.o SOBJS = lowlevel_init.o diff --git a/cpu/arm926ejs/at91/clock.c b/cpu/arm926ejs/at91/clock.c new file mode 100644 index 0000000000..31e53b30dd --- /dev/null +++ b/cpu/arm926ejs/at91/clock.c @@ -0,0 +1,202 @@ +/* + * [origin: Linux kernel linux/arch/arm/mach-at91/clock.c] + * + * Copyright (C) 2005 David Brownell + * Copyright (C) 2005 Ivan Kokshaysky + * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <config.h> +#include <asm/arch/hardware.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/clk.h> +#include <asm/arch/io.h> + +static unsigned long cpu_clk_rate_hz; +static unsigned long main_clk_rate_hz; +static unsigned long mck_rate_hz; +static unsigned long plla_rate_hz; +static unsigned long pllb_rate_hz; +static u32 at91_pllb_usb_init; + +unsigned long get_cpu_clk_rate(void) +{ + return cpu_clk_rate_hz; +} + +unsigned long get_main_clk_rate(void) +{ + return main_clk_rate_hz; +} + +unsigned long get_mck_clk_rate(void) +{ + return mck_rate_hz; +} + +unsigned long get_plla_clk_rate(void) +{ + return plla_rate_hz; +} + +unsigned long get_pllb_clk_rate(void) +{ + return pllb_rate_hz; +} + +u32 get_pllb_init(void) +{ + return at91_pllb_usb_init; +} + +static unsigned long at91_css_to_rate(unsigned long css) +{ + switch (css) { + case AT91_PMC_CSS_SLOW: + return AT91_SLOW_CLOCK; + case AT91_PMC_CSS_MAIN: + return main_clk_rate_hz; + case AT91_PMC_CSS_PLLA: + return plla_rate_hz; + case AT91_PMC_CSS_PLLB: + return pllb_rate_hz; + } + + return 0; +} + +#ifdef CONFIG_USB_ATMEL +static unsigned at91_pll_calc(unsigned main_freq, unsigned out_freq) +{ + unsigned i, div = 0, mul = 0, diff = 1 << 30; + unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00; + + /* PLL output max 240 MHz (or 180 MHz per errata) */ + if (out_freq > 240000000) + goto fail; + + for (i = 1; i < 256; i++) { + int diff1; + unsigned input, mul1; + + /* + * PLL input between 1MHz and 32MHz per spec, but lower + * frequences seem necessary in some cases so allow 100K. + * Warning: some newer products need 2MHz min. + */ + input = main_freq / i; +#if defined(CONFIG_AT91SAM9G20) + if (input < 2000000) + continue; +#endif + if (input < 100000) + continue; + if (input > 32000000) + continue; + + mul1 = out_freq / input; +#if defined(CONFIG_AT91SAM9G20) + if (mul > 63) + continue; +#endif + if (mul1 > 2048) + continue; + if (mul1 < 2) + goto fail; + + diff1 = out_freq - input * mul1; + if (diff1 < 0) + diff1 = -diff1; + if (diff > diff1) { + diff = diff1; + div = i; + mul = mul1; + if (diff == 0) + break; + } + } + if (i == 256 && diff > (out_freq >> 5)) + goto fail; + return ret | ((mul - 1) << 16) | div; +fail: + return 0; +} + +static u32 at91_pll_rate(u32 freq, u32 reg) +{ + unsigned mul, div; + + div = reg & 0xff; + mul = (reg >> 16) & 0x7ff; + if (div && mul) { + freq /= div; + freq *= mul + 1; + } else + freq = 0; + + return freq; +} +#endif + +int at91_clock_init(unsigned long main_clock) +{ + unsigned freq, mckr; +#ifndef AT91_MAIN_CLOCK + unsigned tmp; + /* + * When the bootloader initialized the main oscillator correctly, + * there's no problem using the cycle counter. But if it didn't, + * or when using oscillator bypass mode, we must be told the speed + * of the main clock. + */ + if (!main_clock) { + do { + tmp = at91_sys_read(AT91_CKGR_MCFR); + } while (!(tmp & AT91_PMC_MAINRDY)); + main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16); + } +#endif + main_clk_rate_hz = main_clock; + + /* report if PLLA is more than mildly overclocked */ + plla_rate_hz = at91_pll_rate(main_clock, at91_sys_read(AT91_CKGR_PLLAR)); + +#ifdef CONFIG_USB_ATMEL + /* + * USB clock init: choose 48 MHz PLLB value, + * disable 48MHz clock during usb peripheral suspend. + * + * REVISIT: assumes MCK doesn't derive from PLLB! + */ + at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | + AT91_PMC_USB96M; + pllb_rate_hz = at91_pll_rate(main_clock, at91_pllb_usb_init); +#endif + + /* + * MCK and CPU derive from one of those primary clocks. + * For now, assume this parentage won't change. + */ + mckr = at91_sys_read(AT91_PMC_MCKR); + freq = mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_CSS); + freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2)); /* prescale */ +#if defined(CONFIG_AT91RM9200) + mck_rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ +#elif defined(CONFIG_AT91SAM9G20) + mck_rate_hz = (mckr & AT91_PMC_MDIV) ? + freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq; /* mdiv ; (x >> 7) = ((x >> 8) * 2) */ + if (mckr & AT91_PMC_PDIV) + freq /= 2; /* processor clock division */ +#else + mck_rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ +#endif + cpu_clk_rate_hz = freq; + + return 0; +} + diff --git a/cpu/arm926ejs/at91/cpu.c b/cpu/arm926ejs/at91/cpu.c new file mode 100644 index 0000000000..a9705cfed3 --- /dev/null +++ b/cpu/arm926ejs/at91/cpu.c @@ -0,0 +1,14 @@ +#include <config.h> +#include <asm/arch/hardware.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/clk.h> +#include <asm/arch/io.h> + +int arch_cpu_init(void) +{ +#ifdef AT91_MAIN_CLOCK + return at91_clock_init(AT91_MAIN_CLOCK); +#else + return at91_clock_init(0); +#endif +} diff --git a/drivers/spi/atmel_dataflash_spi.c b/drivers/spi/atmel_dataflash_spi.c index 3eb252c5b5..614965c367 100644 --- a/drivers/spi/atmel_dataflash_spi.c +++ b/drivers/spi/atmel_dataflash_spi.c @@ -21,6 +21,7 @@ #include <common.h> #include <asm/arch/hardware.h> +#include <asm/arch/clk.h> #include <asm/arch/gpio.h> #include <asm/arch/io.h> #include <asm/arch/at91_pio.h> @@ -45,7 +46,7 @@ void AT91F_SpiInit(void) writel(AT91_SPI_NCPHA | (AT91_SPI_DLYBS & DATAFLASH_TCSS) | (AT91_SPI_DLYBCT & DATAFLASH_TCHS) | - ((AT91_MASTER_CLOCK / AT91_SPI_CLK) << 8), + ((get_mck_clk_rate() / AT91_SPI_CLK) << 8), AT91_BASE_SPI + AT91_SPI_CSR(0)); #ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1 @@ -53,7 +54,7 @@ void AT91F_SpiInit(void) writel(AT91_SPI_NCPHA | (AT91_SPI_DLYBS & DATAFLASH_TCSS) | (AT91_SPI_DLYBCT & DATAFLASH_TCHS) | - ((AT91_MASTER_CLOCK / AT91_SPI_CLK) << 8), + ((get_mck_clk_rate() / AT91_SPI_CLK) << 8), AT91_BASE_SPI + AT91_SPI_CSR(1)); #endif @@ -62,7 +63,7 @@ void AT91F_SpiInit(void) writel(AT91_SPI_NCPHA | (AT91_SPI_DLYBS & DATAFLASH_TCSS) | (AT91_SPI_DLYBCT & DATAFLASH_TCHS) | - ((AT91_MASTER_CLOCK / AT91_SPI_CLK) << 8), + ((get_mck_clk_rate() / AT91_SPI_CLK) << 8), AT91_BASE_SPI + AT91_SPI_CSR(3)); #endif diff --git a/drivers/usb/host/ohci-at91.c b/drivers/usb/host/ohci-at91.c index 7c44ad0e95..c35319c1cb 100644 --- a/drivers/usb/host/ohci-at91.c +++ b/drivers/usb/host/ohci-at91.c @@ -28,6 +28,7 @@ #include <asm/arch/hardware.h> #include <asm/arch/io.h> #include <asm/arch/at91_pmc.h> +#include <asm/arch/clk.h> int usb_cpu_init(void) { @@ -35,7 +36,7 @@ int usb_cpu_init(void) #if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \ defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G20) /* Enable PLLB */ - at91_sys_write(AT91_CKGR_PLLBR, CONFIG_SYS_AT91_PLLB); + at91_sys_write(AT91_CKGR_PLLBR, get_pllb_init()); while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB) ; #endif diff --git a/include/asm-arm/arch-at91/at91_pmc.h b/include/asm-arm/arch-at91/at91_pmc.h index b57875d798..07580da692 100644 --- a/include/asm-arm/arch-at91/at91_pmc.h +++ b/include/asm-arm/arch-at91/at91_pmc.h @@ -1,5 +1,5 @@ /* - * [origin: Linux kernel include/asm-arm/arch-at91/at91_pmc.h] + * [origin: Linux kernel arch/arm/mach-at91/include/mach/at91_pmc.h] * * Copyright (C) 2005 Ivan Kokshaysky * Copyright (C) SAN People @@ -23,6 +23,7 @@ #define AT91_PMC_PCK (1 << 0) /* Processor Clock */ #define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */ #define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */ +#define AT91CAP9_PMC_DDR (1 << 2) /* DDR Clock [AT91CAP9 revC only] */ #define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */ #define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */ #define AT91CAP9_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91CAP9 only] */ @@ -39,10 +40,14 @@ #define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */ #define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [SAM9RL, CAP9] */ +#define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */ +#define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */ +#define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */ +#define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI PLL Start-up Time */ #define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */ #define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ -#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [AT91SAM926x only] */ +#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [SAM9x, CAP9] */ #define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */ #define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */ @@ -76,10 +81,17 @@ #define AT91_PMC_PRES_32 (5 << 2) #define AT91_PMC_PRES_64 (6 << 2) #define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */ -#define AT91_PMC_MDIV_1 (0 << 8) -#define AT91_PMC_MDIV_2 (1 << 8) -#define AT91_PMC_MDIV_3 (2 << 8) -#define AT91_PMC_MDIV_4 (3 << 8) +#define AT91RM9200_PMC_MDIV_1 (0 << 8) /* [AT91RM9200 only] */ +#define AT91RM9200_PMC_MDIV_2 (1 << 8) +#define AT91RM9200_PMC_MDIV_3 (2 << 8) +#define AT91RM9200_PMC_MDIV_4 (3 << 8) +#define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9,CAP9 only] */ +#define AT91SAM9_PMC_MDIV_2 (1 << 8) +#define AT91SAM9_PMC_MDIV_4 (2 << 8) +#define AT91SAM9_PMC_MDIV_6 (3 << 8) +#define AT91_PMC_PDIV (1 << 12) /* Processor Clock Division [some SAM9 only] */ +#define AT91_PMC_PDIV_1 (0 << 12) +#define AT91_PMC_PDIV_2 (1 << 12) #define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-3 Registers */ @@ -90,6 +102,8 @@ #define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */ #define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */ #define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */ +#define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock [AT91CAP9 only] */ +#define AT91_PMC_OSCSEL (1 << 7) /* Slow Clock Oscillator [AT91CAP9 revC only] */ #define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */ #define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */ #define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */ @@ -97,8 +111,8 @@ #define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */ #define AT91_PMC_PROT (AT91_PMC + 0xe4) /* Protect Register [AT91CAP9 revC only] */ -#define AT91_PMC_PROTKEY 0x504d4301 /* Activation Code */ +#define AT91_PMC_PROTKEY 0x504d4301 /* Activation Code */ -#define AT91_PMC_VER (AT91_PMC + 0xfc) /* PMC Module Version [AT91CAP9 only] */ +#define AT91_PMC_VER (AT91_PMC + 0xfc) /* PMC Module Version [AT91CAP9 only] */ #endif diff --git a/include/asm-arm/arch-at91/clk.h b/include/asm-arm/arch-at91/clk.h index 1b502c822c..6aaf82eae2 100644 --- a/include/asm-arm/arch-at91/clk.h +++ b/include/asm-arm/arch-at91/clk.h @@ -2,6 +2,7 @@ * (C) Copyright 2007 * Stelian Pop <stelian.pop@leadtechdesign.com> * Lead Tech Design <www.leadtechdesign.com> + * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> * * See file CREDITS for list of people who contributed to this * project. @@ -26,20 +27,32 @@ #include <asm/arch/hardware.h> +unsigned long get_cpu_clk_rate(void); +unsigned long get_main_clk_rate(void); +unsigned long get_mck_clk_rate(void); +unsigned long get_plla_clk_rate(void); +unsigned long get_pllb_clk_rate(void); +unsigned int get_pllb_init(void); + static inline unsigned long get_macb_pclk_rate(unsigned int dev_id) { - return AT91_MASTER_CLOCK; + return get_mck_clk_rate(); } static inline unsigned long get_usart_clk_rate(unsigned int dev_id) { - return AT91_MASTER_CLOCK; + return get_mck_clk_rate(); } static inline unsigned long get_lcdc_clk_rate(unsigned int dev_id) { - return AT91_MASTER_CLOCK; + return get_mck_clk_rate(); } +static inline unsigned long get_twi_clk_rate(unsigned int dev_id) +{ + return get_mck_clk_rate(); +} +int at91_clock_init(unsigned long main_clock); #endif /* __ASM_ARM_ARCH_CLK_H__ */ diff --git a/include/asm-arm/arch-at91/hardware.h b/include/asm-arm/arch-at91/hardware.h index 4f0e1a7e6d..6b46a366a6 100644 --- a/include/asm-arm/arch-at91/hardware.h +++ b/include/asm-arm/arch-at91/hardware.h @@ -48,4 +48,7 @@ #error "Unsupported AT91 processor" #endif +/* Clocks */ +#define AT91_SLOW_CLOCK 32768 /* slow clock */ + #endif diff --git a/include/asm-arm/u-boot-arm.h b/include/asm-arm/u-boot-arm.h index 4ee5a327e5..e7d58fe8cd 100644 --- a/include/asm-arm/u-boot-arm.h +++ b/include/asm-arm/u-boot-arm.h @@ -40,6 +40,9 @@ extern ulong FIQ_STACK_START; /* top of FIQ stack */ int cpu_init(void); int cleanup_before_linux(void); +/* cpu/.../arch/cpu.c */ +int arch_cpu_init(void); + /* board/.../... */ int board_init(void); int dram_init (void); diff --git a/include/configs/afeb9260.h b/include/configs/afeb9260.h index de938f7a29..d637a9455b 100644 --- a/include/configs/afeb9260.h +++ b/include/configs/afeb9260.h @@ -28,14 +28,11 @@ /* ARM asynchronous clock */ #define AT91_MAIN_CLOCK 18429952 /* from 18.432 MHz crystal */ -#define AT91_MASTER_CLOCK 89999598 /* peripheral = main / 2 */ -#define CONFIG_SYS_AT91_PLLB 0x107c3e18 /* PLLB settings for USB */ #define CONFIG_SYS_HZ 1000000 /* 1us resolution */ -#define AT91_SLOW_CLOCK 32768 /* slow clock */ - #define CONFIG_AT91SAM9260 1 /* It's an Atmel AT91SAM9260 SoC*/ #define CONFIG_AFEB9260 1 /* on an AFEB9260 Board */ +#define CONFIG_ARCH_CPU_INIT #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ diff --git a/include/configs/at91cap9adk.h b/include/configs/at91cap9adk.h index b978731bce..c61af08be2 100644 --- a/include/configs/at91cap9adk.h +++ b/include/configs/at91cap9adk.h @@ -30,16 +30,12 @@ /* ARM asynchronous clock */ #define AT91_CPU_NAME "AT91CAP9" #define AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ -#define AT91_MASTER_CLOCK 100000000 /* peripheral */ -#define AT91_CPU_CLOCK 200000000 /* cpu */ -#define CONFIG_SYS_AT91_PLLB 0x10073e01 /* PLLB settings for USB */ #define CONFIG_SYS_HZ 1000000 /* 1us resolution */ -#define AT91_SLOW_CLOCK 32768 /* slow clock */ - #define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ #define CONFIG_AT91CAP9 1 /* It's an Atmel AT91CAP9 SoC */ #define CONFIG_AT91CAP9ADK 1 /* on an AT91CAP9ADK Board */ +#define CONFIG_ARCH_CPU_INIT #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h index bcc65bdd64..b6e2edf313 100644 --- a/include/configs/at91sam9260ek.h +++ b/include/configs/at91sam9260ek.h @@ -29,25 +29,19 @@ /* ARM asynchronous clock */ #define AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */ -#define CONFIG_SYS_AT91_PLLB 0x107c3e18 /* PLLB settings for USB */ #define CONFIG_SYS_HZ 1000000 /* 1us resolution */ -#define AT91_SLOW_CLOCK 32768 /* slow clock */ - #define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ #ifdef CONFIG_AT91SAM9G20EK #define AT91_CPU_NAME "AT91SAM9G20" -#define AT91_MASTER_CLOCK 132000000 /* peripheral */ -#define AT91_CPU_CLOCK 396000000 /* cpu */ #define CONFIG_AT91SAM9G20 1 /* It's an Atmel AT91SAM9G20 SoC*/ #else #define AT91_CPU_NAME "AT91SAM9260" -#define AT91_MASTER_CLOCK 100000000 /* peripheral */ -#define AT91_CPU_CLOCK 200000000 /* cpu */ #define CONFIG_AT91SAM9260 1 /* It's an Atmel AT91SAM9260 SoC*/ #endif +#define CONFIG_ARCH_CPU_INIT #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h index cc40d7bda7..7ec171cfbb 100644 --- a/include/configs/at91sam9261ek.h +++ b/include/configs/at91sam9261ek.h @@ -30,15 +30,12 @@ /* ARM asynchronous clock */ #define AT91_CPU_NAME "AT91SAM9261" #define AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */ -#define AT91_MASTER_CLOCK 100000000 /* peripheral */ -#define AT91_CPU_CLOCK 200000000 /* cpu */ #define CONFIG_SYS_HZ 1000000 /* 1us resolution */ -#define AT91_SLOW_CLOCK 32768 /* slow clock */ - #define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ #define CONFIG_AT91SAM9261 1 /* It's an Atmel AT91SAM9261 SoC*/ #define CONFIG_AT91SAM9261EK 1 /* on an AT91SAM9261EK Board */ +#define CONFIG_ARCH_CPU_INIT #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h index ee1531f1a7..34c7521f3f 100644 --- a/include/configs/at91sam9263ek.h +++ b/include/configs/at91sam9263ek.h @@ -30,16 +30,12 @@ /* ARM asynchronous clock */ #define AT91_CPU_NAME "AT91SAM9263" #define AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */ -#define AT91_MASTER_CLOCK 100000000 /* peripheral */ -#define AT91_CPU_CLOCK 200000000 /* cpu */ -#define CONFIG_SYS_AT91_PLLB 0x133a3e8d /* PLLB settings for USB */ #define CONFIG_SYS_HZ 1000000 /* 1us resolution */ -#define AT91_SLOW_CLOCK 32768 /* slow clock */ - #define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ #define CONFIG_AT91SAM9263 1 /* It's an Atmel AT91SAM9263 SoC*/ #define CONFIG_AT91SAM9263EK 1 /* on an AT91SAM9263EK Board */ +#define CONFIG_ARCH_CPU_INIT #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h index fec48b6b26..2ccf9587a6 100644 --- a/include/configs/at91sam9rlek.h +++ b/include/configs/at91sam9rlek.h @@ -30,15 +30,12 @@ /* ARM asynchronous clock */ #define AT91_CPU_NAME "AT91SAM9RL" #define AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ -#define AT91_MASTER_CLOCK 100000000 /* peripheral */ -#define AT91_CPU_CLOCK 200000000 /* cpu */ #define CONFIG_SYS_HZ 1000000 /* 1us resolution */ -#define AT91_SLOW_CLOCK 32768 /* slow clock */ - #define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ #define CONFIG_AT91SAM9RL 1 /* It's an Atmel AT91SAM9RL SoC*/ #define CONFIG_AT91SAM9RLEK 1 /* on an AT91SAM9RLEK Board */ +#define CONFIG_ARCH_CPU_INIT #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ diff --git a/lib_arm/board.c b/lib_arm/board.c index 3dfaec01b4..6847ea8239 100644 --- a/lib_arm/board.c +++ b/lib_arm/board.c @@ -262,6 +262,9 @@ int print_cpuinfo (void); /* test-only */ init_fnc_t *init_sequence[] = { cpu_init, /* basic cpu dependent setup */ +#if defined(CONFIG_ARCH_CPU_INIT) + arch_cpu_init, /* basic arch cpu dependent setup */ +#endif board_init, /* basic board dependent setup */ interrupt_init, /* set up exceptions */ env_init, /* initialize environment */ |
