diff options
| -rw-r--r-- | cpu/blackfin/cpu.c | 35 | ||||
| -rw-r--r-- | lib_blackfin/cache.c | 35 |
2 files changed, 35 insertions, 35 deletions
diff --git a/cpu/blackfin/cpu.c b/cpu/blackfin/cpu.c index 0c799325c6..9efd88e7ec 100644 --- a/cpu/blackfin/cpu.c +++ b/cpu/blackfin/cpu.c @@ -14,46 +14,11 @@ #include <asm/blackfin.h> #include <asm/cplb.h> #include <asm/mach-common/bits/core.h> -#include <asm/mach-common/bits/mpu.h> #include <asm/mach-common/bits/trace.h> #include "cpu.h" #include "serial.h" -void icache_enable(void) -{ - bfin_write_IMEM_CONTROL(bfin_read_IMEM_CONTROL() | (IMC | ENICPLB)); - SSYNC(); -} - -void icache_disable(void) -{ - bfin_write_IMEM_CONTROL(bfin_read_IMEM_CONTROL() & ~(IMC | ENICPLB)); - SSYNC(); -} - -int icache_status(void) -{ - return bfin_read_IMEM_CONTROL() & ENICPLB; -} - -void dcache_enable(void) -{ - bfin_write_DMEM_CONTROL(bfin_read_DMEM_CONTROL() | (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)); - SSYNC(); -} - -void dcache_disable(void) -{ - bfin_write_DMEM_CONTROL(bfin_read_DMEM_CONTROL() & ~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0)); - SSYNC(); -} - -int dcache_status(void) -{ - return bfin_read_DMEM_CONTROL() & ENDCPLB; -} - __attribute__ ((__noreturn__)) void cpu_init_f(ulong bootflag, ulong loaded_from_ldr) { diff --git a/lib_blackfin/cache.c b/lib_blackfin/cache.c index c2f6e2848e..41e2a62d12 100644 --- a/lib_blackfin/cache.c +++ b/lib_blackfin/cache.c @@ -11,6 +11,7 @@ #include <common.h> #include <asm/blackfin.h> +#include <asm/mach-common/bits/mpu.h> void flush_cache(unsigned long addr, unsigned long size) { @@ -24,3 +25,37 @@ void flush_cache(unsigned long addr, unsigned long size) if (dcache_status()) blackfin_dcache_flush_range((void *)addr, (void *)(addr + size)); } + +void icache_enable(void) +{ + bfin_write_IMEM_CONTROL(IMC | ENICPLB); + SSYNC(); +} + +void icache_disable(void) +{ + bfin_write_IMEM_CONTROL(0); + SSYNC(); +} + +int icache_status(void) +{ + return bfin_read_IMEM_CONTROL() & ENICPLB; +} + +void dcache_enable(void) +{ + bfin_write_DMEM_CONTROL(ACACHE_BCACHE | ENDCPLB | PORT_PREF0); + SSYNC(); +} + +void dcache_disable(void) +{ + bfin_write_DMEM_CONTROL(0); + SSYNC(); +} + +int dcache_status(void) +{ + return bfin_read_DMEM_CONTROL() & ENDCPLB; +} |
