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-rw-r--r--arch/arm/cpu/armv7/keystone/clock.c24
-rw-r--r--arch/arm/cpu/armv7/keystone/ddr3.c8
-rw-r--r--arch/arm/cpu/armv7/keystone/init.c4
-rw-r--r--arch/arm/cpu/armv7/keystone/keystone.c2
-rw-r--r--arch/arm/cpu/armv7/keystone/msmc.c2
-rw-r--r--arch/arm/include/asm/arch-keystone/clock-k2hk.h2
-rw-r--r--arch/arm/include/asm/arch-keystone/clock_defs.h2
-rw-r--r--arch/arm/include/asm/arch-keystone/hardware-k2hk.h202
-rw-r--r--arch/arm/include/asm/arch-keystone/hardware.h4
-rw-r--r--board/ti/k2hk_evm/ddr3.c24
-rw-r--r--include/configs/k2hk_evm.h12
11 files changed, 138 insertions, 148 deletions
diff --git a/arch/arm/cpu/armv7/keystone/clock.c b/arch/arm/cpu/armv7/keystone/clock.c
index bfa4c9d8f6..f905fdcf0d 100644
--- a/arch/arm/cpu/armv7/keystone/clock.c
+++ b/arch/arm/cpu/armv7/keystone/clock.c
@@ -29,11 +29,11 @@ struct pll_regs {
};
static const struct pll_regs pll_regs[] = {
- [CORE_PLL] = { K2HK_MAINPLLCTL0, K2HK_MAINPLLCTL1},
- [PASS_PLL] = { K2HK_PASSPLLCTL0, K2HK_PASSPLLCTL1},
- [TETRIS_PLL] = { K2HK_ARMPLLCTL0, K2HK_ARMPLLCTL1},
- [DDR3A_PLL] = { K2HK_DDR3APLLCTL0, K2HK_DDR3APLLCTL1},
- [DDR3B_PLL] = { K2HK_DDR3BPLLCTL0, K2HK_DDR3BPLLCTL1},
+ [CORE_PLL] = { KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
+ [PASS_PLL] = { KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
+ [TETRIS_PLL] = { KS2_ARMPLLCTL0, KS2_ARMPLLCTL1},
+ [DDR3A_PLL] = { KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
+ [DDR3B_PLL] = { KS2_DDR3BPLLCTL0, KS2_DDR3BPLLCTL1},
};
/* Fout = Fref * NF(mult) / NR(prediv) / OD */
@@ -47,7 +47,7 @@ static unsigned long pll_freq_get(int pll)
ret = external_clk[sys_clk];
if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) {
/* PLL mode */
- tmp = __raw_readl(K2HK_MAINPLLCTL0);
+ tmp = __raw_readl(KS2_MAINPLLCTL0);
prediv = (tmp & PLL_DIV_MASK) + 1;
mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) |
(pllctl_reg_read(pll, mult) &
@@ -61,19 +61,19 @@ static unsigned long pll_freq_get(int pll)
switch (pll) {
case PASS_PLL:
ret = external_clk[pa_clk];
- reg = K2HK_PASSPLLCTL0;
+ reg = KS2_PASSPLLCTL0;
break;
case TETRIS_PLL:
ret = external_clk[tetris_clk];
- reg = K2HK_ARMPLLCTL0;
+ reg = KS2_ARMPLLCTL0;
break;
case DDR3A_PLL:
ret = external_clk[ddr3a_clk];
- reg = K2HK_DDR3APLLCTL0;
+ reg = KS2_DDR3APLLCTL0;
break;
case DDR3B_PLL:
ret = external_clk[ddr3b_clk];
- reg = K2HK_DDR3BPLLCTL0;
+ reg = KS2_DDR3BPLLCTL0;
break;
default:
return 0;
@@ -214,7 +214,7 @@ void init_pll(const struct pll_init_data *data)
* Set CHIPMISCCTL1[13] = 0 (enable glitchfree bypass)
* only applicable for Kepler
*/
- clrbits_le32(K2HK_MISC_CTRL, ARM_PLL_EN);
+ clrbits_le32(KS2_MISC_CTRL, KS2_ARM_PLL_EN);
/* 2 In PLLCTL1, write PLLRST = 1 (PLL is reset) */
setbits_le32(pll_regs[data->pll].reg1 ,
PLL_PLLRST | PLLCTL_ENSAT);
@@ -255,7 +255,7 @@ void init_pll(const struct pll_init_data *data)
* 9 Set CHIPMISCCTL1[13] = 1 (disable glitchfree bypass)
* only applicable for Kepler
*/
- setbits_le32(K2HK_MISC_CTRL, ARM_PLL_EN);
+ setbits_le32(KS2_MISC_CTRL, KS2_ARM_PLL_EN);
} else {
setbits_le32(pll_regs[data->pll].reg1, PLLCTL_ENSAT);
/*
diff --git a/arch/arm/cpu/armv7/keystone/ddr3.c b/arch/arm/cpu/armv7/keystone/ddr3.c
index b711b810cb..2391e794e8 100644
--- a/arch/arm/cpu/armv7/keystone/ddr3.c
+++ b/arch/arm/cpu/armv7/keystone/ddr3.c
@@ -74,15 +74,15 @@ void ddr3_reset_ddrphy(void)
u32 tmp;
/* Assert DDR3A PHY reset */
- tmp = readl(K2HK_DDR3APLLCTL1);
+ tmp = readl(KS2_DDR3APLLCTL1);
tmp |= KS2_DDR3_PLLCTRL_PHY_RESET;
- writel(tmp, K2HK_DDR3APLLCTL1);
+ writel(tmp, KS2_DDR3APLLCTL1);
/* wait 10us to catch the reset */
udelay(10);
/* Release DDR3A PHY reset */
- tmp = readl(K2HK_DDR3APLLCTL1);
+ tmp = readl(KS2_DDR3APLLCTL1);
tmp &= ~KS2_DDR3_PLLCTRL_PHY_RESET;
- __raw_writel(tmp, K2HK_DDR3APLLCTL1);
+ __raw_writel(tmp, KS2_DDR3APLLCTL1);
}
diff --git a/arch/arm/cpu/armv7/keystone/init.c b/arch/arm/cpu/armv7/keystone/init.c
index 4df5ae1cae..f4c293aa89 100644
--- a/arch/arm/cpu/armv7/keystone/init.c
+++ b/arch/arm/cpu/armv7/keystone/init.c
@@ -15,8 +15,8 @@
void chip_configuration_unlock(void)
{
- __raw_writel(KEYSTONE_KICK0_MAGIC, KEYSTONE_KICK0);
- __raw_writel(KEYSTONE_KICK1_MAGIC, KEYSTONE_KICK1);
+ __raw_writel(KS2_KICK0_MAGIC, KS2_KICK0);
+ __raw_writel(KS2_KICK1_MAGIC, KS2_KICK1);
}
int arch_cpu_init(void)
diff --git a/arch/arm/cpu/armv7/keystone/keystone.c b/arch/arm/cpu/armv7/keystone/keystone.c
index 1c8c038455..11a9357db4 100644
--- a/arch/arm/cpu/armv7/keystone/keystone.c
+++ b/arch/arm/cpu/armv7/keystone/keystone.c
@@ -23,7 +23,7 @@ int cpu_to_bus(u32 *ptr, u32 length)
{
u32 i;
- if (!(readl(K2HK_DEVSTAT) & 0x1))
+ if (!(readl(KS2_DEVSTAT) & 0x1))
for (i = 0; i < length; i++, ptr++)
*ptr = cpu_to_be32(*ptr);
diff --git a/arch/arm/cpu/armv7/keystone/msmc.c b/arch/arm/cpu/armv7/keystone/msmc.c
index f3f1621d20..af858fa758 100644
--- a/arch/arm/cpu/armv7/keystone/msmc.c
+++ b/arch/arm/cpu/armv7/keystone/msmc.c
@@ -58,7 +58,7 @@ struct msms_regs {
void share_all_segments(int priv_id)
{
- struct msms_regs *msmc = (struct msms_regs *)K2HK_MSMC_CTRL_BASE;
+ struct msms_regs *msmc = (struct msms_regs *)KS2_MSMC_CTRL_BASE;
int j;
for (j = 0; j < 8; j++) {
diff --git a/arch/arm/include/asm/arch-keystone/clock-k2hk.h b/arch/arm/include/asm/arch-keystone/clock-k2hk.h
index 6a69a8d2be..ed1225c298 100644
--- a/arch/arm/include/asm/arch-keystone/clock-k2hk.h
+++ b/arch/arm/include/asm/arch-keystone/clock-k2hk.h
@@ -56,7 +56,7 @@ enum clk_e {
sys_clk3_clk
};
-#define K2HK_CLK1_6 sys_clk0_6_clk
+#define KS2_CLK1_6 sys_clk0_6_clk
/* PLL identifiers */
enum pll_type_e {
diff --git a/arch/arm/include/asm/arch-keystone/clock_defs.h b/arch/arm/include/asm/arch-keystone/clock_defs.h
index b251aff383..e545341ca7 100644
--- a/arch/arm/include/asm/arch-keystone/clock_defs.h
+++ b/arch/arm/include/asm/arch-keystone/clock_defs.h
@@ -50,7 +50,7 @@ struct pllctl_regs {
};
static struct pllctl_regs *pllctl_regs[] = {
- (struct pllctl_regs *)(CLOCK_BASE + 0x100)
+ (struct pllctl_regs *)(KS2_CLOCK_BASE + 0x100)
};
#define pllctl_reg(pll, reg) (&(pllctl_regs[pll]->reg))
diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
index 5e2f659e94..e7dff059b8 100644
--- a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
+++ b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
@@ -6,134 +6,124 @@
*
* SPDX-License-Identifier: GPL-2.0+
*/
+
#ifndef __ASM_ARCH_HARDWARE_K2HK_H
#define __ASM_ARCH_HARDWARE_K2HK_H
-#define K2HK_PLL_CNTRL_BASE 0x02310000
-#define CLOCK_BASE K2HK_PLL_CNTRL_BASE
-#define KS2_RSTCTRL (K2HK_PLL_CNTRL_BASE + 0xe8)
-#define KS2_RSTCTRL_KEY 0x5a69
-#define KS2_RSTCTRL_MASK 0xffff0000
-#define KS2_RSTCTRL_SWRST 0xfffe0000
+#define KS2_PLL_CNTRL_BASE 0x02310000
+#define KS2_CLOCK_BASE KS2_PLL_CNTRL_BASE
+#define KS2_RSTCTRL (KS2_PLL_CNTRL_BASE + 0xe8)
+#define KS2_RSTCTRL_KEY 0x5a69
+#define KS2_RSTCTRL_MASK 0xffff0000
+#define KS2_RSTCTRL_SWRST 0xfffe0000
-#define KS2_DEVICE_STATE_CTRL_BASE 0x02620000
-#define JTAG_ID_REG (KS2_DEVICE_STATE_CTRL_BASE + 0x18)
-#define K2HK_DEVSTAT (KS2_DEVICE_STATE_CTRL_BASE + 0x20)
+#define KS2_DEVICE_STATE_CTRL_BASE 0x02620000
+#define KS2_JTAG_ID_REG (KS2_DEVICE_STATE_CTRL_BASE + 0x18)
+#define KS2_DEVSTAT (KS2_DEVICE_STATE_CTRL_BASE + 0x20)
-#define K2HK_MISC_CTRL (KS2_DEVICE_STATE_CTRL_BASE + 0xc7c)
+#define KS2_MISC_CTRL (KS2_DEVICE_STATE_CTRL_BASE + 0xc7c)
-#define ARM_PLL_EN BIT(13)
+#define KS2_ARM_PLL_EN BIT(13)
-#define K2HK_SPI0_BASE 0x21000400
-#define K2HK_SPI1_BASE 0x21000600
-#define K2HK_SPI2_BASE 0x21000800
-#define K2HK_SPI_BASE K2HK_SPI0_BASE
+#define KS2_SPI0_BASE 0x21000400
+#define KS2_SPI1_BASE 0x21000600
+#define KS2_SPI2_BASE 0x21000800
+#define KS2_SPI_BASE KS2_SPI0_BASE
/* Chip configuration unlock codes and registers */
-#define KEYSTONE_KICK0 (KS2_DEVICE_STATE_CTRL_BASE + 0x38)
-#define KEYSTONE_KICK1 (KS2_DEVICE_STATE_CTRL_BASE + 0x3c)
-#define KEYSTONE_KICK0_MAGIC 0x83e70b13
-#define KEYSTONE_KICK1_MAGIC 0x95a4f1e0
+#define KS2_KICK0 (KS2_DEVICE_STATE_CTRL_BASE + 0x38)
+#define KS2_KICK1 (KS2_DEVICE_STATE_CTRL_BASE + 0x3c)
+#define KS2_KICK0_MAGIC 0x83e70b13
+#define KS2_KICK1_MAGIC 0x95a4f1e0
/* PA SS Registers */
-#define KS2_PASS_BASE 0x02000000
+#define KS2_PASS_BASE 0x02000000
/* PLL control registers */
-#define K2HK_MAINPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x350)
-#define K2HK_MAINPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x354)
-#define K2HK_PASSPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x358)
-#define K2HK_PASSPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x35C)
-#define K2HK_DDR3APLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x360)
-#define K2HK_DDR3APLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x364)
-#define K2HK_DDR3BPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x368)
-#define K2HK_DDR3BPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x36C)
-#define K2HK_ARMPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x370)
-#define K2HK_ARMPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x374)
+#define KS2_MAINPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x350)
+#define KS2_MAINPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x354)
+#define KS2_PASSPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x358)
+#define KS2_PASSPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x35C)
+#define KS2_DDR3APLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x360)
+#define KS2_DDR3APLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x364)
+#define KS2_DDR3BPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x368)
+#define KS2_DDR3BPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x36C)
+#define KS2_ARMPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x370)
+#define KS2_ARMPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x374)
/* Power and Sleep Controller (PSC) Domains */
-#define K2HK_LPSC_MOD 0
-#define K2HK_LPSC_DUMMY1 1
-#define K2HK_LPSC_USB 2
-#define K2HK_LPSC_EMIF25_SPI 3
-#define K2HK_LPSC_TSIP 4
-#define K2HK_LPSC_DEBUGSS_TRC 5
-#define K2HK_LPSC_TETB_TRC 6
-#define K2HK_LPSC_PKTPROC 7
-#define KS2_LPSC_PA K2HK_LPSC_PKTPROC
-#define K2HK_LPSC_SGMII 8
-#define KS2_LPSC_CPGMAC K2HK_LPSC_SGMII
-#define K2HK_LPSC_CRYPTO 9
-#define K2HK_LPSC_PCIE 10
-#define K2HK_LPSC_SRIO 11
-#define K2HK_LPSC_VUSR0 12
-#define K2HK_LPSC_CHIP_SRSS 13
-#define K2HK_LPSC_MSMC 14
-#define K2HK_LPSC_GEM_1 16
-#define K2HK_LPSC_GEM_2 17
-#define K2HK_LPSC_GEM_3 18
-#define K2HK_LPSC_GEM_4 19
-#define K2HK_LPSC_GEM_5 20
-#define K2HK_LPSC_GEM_6 21
-#define K2HK_LPSC_GEM_7 22
-#define K2HK_LPSC_EMIF4F_DDR3A 23
-#define K2HK_LPSC_EMIF4F_DDR3B 24
-#define K2HK_LPSC_TAC 25
-#define K2HK_LPSC_RAC 26
-#define K2HK_LPSC_RAC_1 27
-#define K2HK_LPSC_FFTC_A 28
-#define K2HK_LPSC_FFTC_B 29
-#define K2HK_LPSC_FFTC_C 30
-#define K2HK_LPSC_FFTC_D 31
-#define K2HK_LPSC_FFTC_E 32
-#define K2HK_LPSC_FFTC_F 33
-#define K2HK_LPSC_AI2 34
-#define K2HK_LPSC_TCP3D_0 35
-#define K2HK_LPSC_TCP3D_1 36
-#define K2HK_LPSC_TCP3D_2 37
-#define K2HK_LPSC_TCP3D_3 38
-#define K2HK_LPSC_VCP2X4_A 39
-#define K2HK_LPSC_CP2X4_B 40
-#define K2HK_LPSC_VCP2X4_C 41
-#define K2HK_LPSC_VCP2X4_D 42
-#define K2HK_LPSC_VCP2X4_E 43
-#define K2HK_LPSC_VCP2X4_F 44
-#define K2HK_LPSC_VCP2X4_G 45
-#define K2HK_LPSC_VCP2X4_H 46
-#define K2HK_LPSC_BCP 47
-#define K2HK_LPSC_DXB 48
-#define K2HK_LPSC_VUSR1 49
-#define K2HK_LPSC_XGE 50
-#define K2HK_LPSC_ARM_SREFLEX 51
+#define KS2_LPSC_MOD 0
+#define KS2_LPSC_DUMMY1 1
+#define KS2_LPSC_USB 2
+#define KS2_LPSC_EMIF25_SPI 3
+#define KS2_LPSC_TSIP 4
+#define KS2_LPSC_DEBUGSS_TRC 5
+#define KS2_LPSC_TETB_TRC 6
+#define KS2_LPSC_PKTPROC 7
+#define KS2_LPSC_PA KS2_LPSC_PKTPROC
+#define KS2_LPSC_SGMII 8
+#define KS2_LPSC_CPGMAC KS2_LPSC_SGMII
+#define KS2_LPSC_CRYPTO 9
+#define KS2_LPSC_PCIE 10
+#define KS2_LPSC_SRIO 11
+#define KS2_LPSC_VUSR0 12
+#define KS2_LPSC_CHIP_SRSS 13
+#define KS2_LPSC_MSMC 14
+#define KS2_LPSC_GEM_1 16
+#define KS2_LPSC_GEM_2 17
+#define KS2_LPSC_GEM_3 18
+#define KS2_LPSC_GEM_4 19
+#define KS2_LPSC_GEM_5 20
+#define KS2_LPSC_GEM_6 21
+#define KS2_LPSC_GEM_7 22
+#define KS2_LPSC_EMIF4F_DDR3A 23
+#define KS2_LPSC_EMIF4F_DDR3B 24
+#define KS2_LPSC_TAC 25
+#define KS2_LPSC_RAC 26
+#define KS2_LPSC_RAC_1 27
+#define KS2_LPSC_FFTC_A 28
+#define KS2_LPSC_FFTC_B 29
+#define KS2_LPSC_FFTC_C 30
+#define KS2_LPSC_FFTC_D 31
+#define KS2_LPSC_FFTC_E 32
+#define KS2_LPSC_FFTC_F 33
+#define KS2_LPSC_AI2 34
+#define KS2_LPSC_TCP3D_0 35
+#define KS2_LPSC_TCP3D_1 36
+#define KS2_LPSC_TCP3D_2 37
+#define KS2_LPSC_TCP3D_3 38
+#define KS2_LPSC_VCP2X4_A 39
+#define KS2_LPSC_CP2X4_B 40
+#define KS2_LPSC_VCP2X4_C 41
+#define KS2_LPSC_VCP2X4_D 42
+#define KS2_LPSC_VCP2X4_E 43
+#define KS2_LPSC_VCP2X4_F 44
+#define KS2_LPSC_VCP2X4_G 45
+#define KS2_LPSC_VCP2X4_H 46
+#define KS2_LPSC_BCP 47
+#define KS2_LPSC_DXB 48
+#define KS2_LPSC_VUSR1 49
+#define KS2_LPSC_XGE 50
+#define KS2_LPSC_ARM_SREFLEX 51
/* DDR3A definitions */
-#define K2HK_DDR3A_EMIF_CTRL_BASE 0x21010000
-#define K2HK_DDR3A_EMIF_DATA_BASE 0x80000000
-#define K2HK_DDR3A_DDRPHYC 0x02329000
+#define KS2_DDR3A_EMIF_CTRL_BASE 0x21010000
+#define KS2_DDR3A_EMIF_DATA_BASE 0x80000000
+#define KS2_DDR3A_DDRPHYC 0x02329000
/* DDR3B definitions */
-#define K2HK_DDR3B_EMIF_CTRL_BASE 0x21020000
-#define K2HK_DDR3B_EMIF_DATA_BASE 0x60000000
-#define K2HK_DDR3B_DDRPHYC 0x02328000
+#define KS2_DDR3B_EMIF_CTRL_BASE 0x21020000
+#define KS2_DDR3B_EMIF_DATA_BASE 0x60000000
+#define KS2_DDR3B_DDRPHYC 0x02328000
/* Queue manager */
-#define DEVICE_QM_MANAGER_BASE 0x02a02000
-#define DEVICE_QM_DESC_SETUP_BASE 0x02a03000
-#define DEVICE_QM_MANAGER_QUEUES_BASE 0x02a80000
-#define DEVICE_QM_MANAGER_Q_PROXY_BASE 0x02ac0000
-#define DEVICE_QM_QUEUE_STATUS_BASE 0x02a40000
-#define DEVICE_QM_NUM_LINKRAMS 2
-#define DEVICE_QM_NUM_MEMREGIONS 20
-
-#define DEVICE_PA_CDMA_GLOBAL_CFG_BASE 0x02004000
-#define DEVICE_PA_CDMA_TX_CHAN_CFG_BASE 0x02004400
-#define DEVICE_PA_CDMA_RX_CHAN_CFG_BASE 0x02004800
-#define DEVICE_PA_CDMA_RX_FLOW_CFG_BASE 0x02005000
-
-#define DEVICE_PA_CDMA_RX_NUM_CHANNELS 24
-#define DEVICE_PA_CDMA_RX_NUM_FLOWS 32
-#define DEVICE_PA_CDMA_TX_NUM_CHANNELS 9
+#define KS2_QM_MANAGER_BASE 0x02a02000
+#define KS2_QM_DESC_SETUP_BASE 0x02a03000
+#define KS2_QM_MANAGER_QUEUES_BASEi 0x02a80000
+#define KS2_QM_MANAGER_Q_PROXY_BASE 0x02ac0000
+#define KS2_QM_QUEUE_STATUS_BASE 0x02a40000
/* MSMC control */
-#define K2HK_MSMC_CTRL_BASE 0x0bc00000
+#define KS2_MSMC_CTRL_BASE 0x0bc00000
/* Number of DSP cores */
#define KS2_NUM_DSPS 8
diff --git a/arch/arm/include/asm/arch-keystone/hardware.h b/arch/arm/include/asm/arch-keystone/hardware.h
index 0dcc31a645..133edadc2a 100644
--- a/arch/arm/include/asm/arch-keystone/hardware.h
+++ b/arch/arm/include/asm/arch-keystone/hardware.h
@@ -105,7 +105,7 @@ typedef volatile unsigned int *dv_reg_p;
#ifndef __ASSEMBLY__
static inline int cpu_is_k2hk(void)
{
- unsigned int jtag_id = __raw_readl(JTAG_ID_REG);
+ unsigned int jtag_id = __raw_readl(KS2_JTAG_ID_REG);
unsigned int part_no = (jtag_id >> 12) & 0xffff;
return (part_no == 0xb981) ? 1 : 0;
@@ -113,7 +113,7 @@ static inline int cpu_is_k2hk(void)
static inline int cpu_revision(void)
{
- unsigned int jtag_id = __raw_readl(JTAG_ID_REG);
+ unsigned int jtag_id = __raw_readl(KS2_JTAG_ID_REG);
unsigned int rev = (jtag_id >> 28) & 0xf;
return rev;
diff --git a/board/ti/k2hk_evm/ddr3.c b/board/ti/k2hk_evm/ddr3.c
index b604266837..31e9c31ea2 100644
--- a/board/ti/k2hk_evm/ddr3.c
+++ b/board/ti/k2hk_evm/ddr3.c
@@ -299,20 +299,20 @@ void ddr3_init(void)
/* PG 2.0 */
/* Reset DDR3A PHY after PLL enabled */
ddr3_reset_ddrphy();
- ddr3_init_ddrphy(K2HK_DDR3A_DDRPHYC,
+ ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
&ddr3phy_1600_64A_pg2);
} else {
/* PG 1.1 */
- ddr3_init_ddrphy(K2HK_DDR3A_DDRPHYC,
+ ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
&ddr3phy_1600_64A);
}
- ddr3_init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE,
+ ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
&ddr3_1600_64);
printf("DRAM: Capacity 8 GiB (includes reported below)\n");
} else {
- ddr3_init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1600_32);
- ddr3_init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE,
+ ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_32);
+ ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
&ddr3_1600_32);
printf("DRAM: Capacity 4 GiB (includes reported below)\n");
}
@@ -323,18 +323,18 @@ void ddr3_init(void)
/* PG 2.0 */
/* Reset DDR3A PHY after PLL enabled */
ddr3_reset_ddrphy();
- ddr3_init_ddrphy(K2HK_DDR3A_DDRPHYC,
+ ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
&ddr3phy_1333_64A_pg2);
} else {
/* PG 1.1 */
- ddr3_init_ddrphy(K2HK_DDR3A_DDRPHYC,
+ ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC,
&ddr3phy_1333_64A);
}
- ddr3_init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE,
+ ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
&ddr3_1333_64);
} else {
- ddr3_init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1333_32);
- ddr3_init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE,
+ ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1333_32);
+ ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
&ddr3_1333_32);
}
} else {
@@ -344,6 +344,6 @@ void ddr3_init(void)
}
init_pll(&ddr3b_333);
- ddr3_init_ddrphy(K2HK_DDR3B_DDRPHYC, &ddr3phy_1333_64);
- ddr3_init_ddremif(K2HK_DDR3B_EMIF_CTRL_BASE, &ddr3_1333_64);
+ ddr3_init_ddrphy(KS2_DDR3B_DDRPHYC, &ddr3phy_1333_64);
+ ddr3_init_ddremif(KS2_DDR3B_EMIF_CTRL_BASE, &ddr3_1333_64);
}
diff --git a/include/configs/k2hk_evm.h b/include/configs/k2hk_evm.h
index 63e02495e1..bacf3bca9d 100644
--- a/include/configs/k2hk_evm.h
+++ b/include/configs/k2hk_evm.h
@@ -73,7 +73,7 @@
#define CONFIG_SYS_NS16550_REG_SIZE -4
#define CONFIG_SYS_NS16550_COM1 KS2_UART0_BASE
#define CONFIG_SYS_NS16550_COM2 KS2_UART1_BASE
-#define CONFIG_SYS_NS16550_CLK clk_get_rate(K2HK_CLK1_6)
+#define CONFIG_SYS_NS16550_CLK clk_get_rate(KS2_CLK1_6)
#define CONFIG_CONS_INDEX 1
#define CONFIG_BAUDRATE 115200
@@ -83,16 +83,16 @@
#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_DAVINCI_SPI
#define CONFIG_SYS_SPI0
-#define CONFIG_SYS_SPI_BASE K2HK_SPI_BASE
+#define CONFIG_SYS_SPI_BASE KS2_SPI_BASE
#define CONFIG_SYS_SPI0_NUM_CS 4
#define CONFIG_SYS_SPI1
-#define CONFIG_SYS_SPI1_BASE K2HK_SPI1_BASE
+#define CONFIG_SYS_SPI1_BASE KS2_SPI1_BASE
#define CONFIG_SYS_SPI1_NUM_CS 4
#define CONFIG_SYS_SPI2
#define CONFIG_SYS_SPI2_NUM_CS 4
-#define CONFIG_SYS_SPI2_BASE K2HK_SPI2_BASE
+#define CONFIG_SYS_SPI2_BASE KS2_SPI2_BASE
#define CONFIG_CMD_SPI
-#define CONFIG_SYS_SPI_CLK clk_get_rate(K2HK_LPSC_EMIF25_SPI)
+#define CONFIG_SYS_SPI_CLK clk_get_rate(KS2_LPSC_EMIF25_SPI)
#define CONFIG_SF_DEFAULT_SPEED 30000000
#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
@@ -264,6 +264,6 @@
/* we may include files below only after all above definitions */
#include <asm/arch/hardware.h>
#include <asm/arch/clock.h>
-#define CONFIG_SYS_HZ_CLOCK clk_get_rate(K2HK_CLK1_6)
+#define CONFIG_SYS_HZ_CLOCK clk_get_rate(KS2_CLK1_6)
#endif /* __CONFIG_K2HK_EVM_H */
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