diff options
| -rw-r--r-- | arch/arm/include/asm/arch-rockchip/cru_rk3288.h | 17 | ||||
| -rw-r--r-- | drivers/clk/clk_rk3288.c | 14 |
2 files changed, 31 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h index d2690c7788..8a8ca9c9aa 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h @@ -90,6 +90,23 @@ enum { SDIO0_DIV_MASK = 0x3f, }; +/* CRU_CLKSEL21_CON */ +enum { + MAC_DIV_CON_SHIFT = 0xf, + MAC_DIV_CON_MASK = 0x1f, + + RMII_EXTCLK_SHIFT = 4, + RMII_EXTCLK_MASK = 1, + RMII_EXTCLK_SELECT_INT_DIV_CLK = 0, + RMII_EXTCLK_SELECT_EXT_CLK = 1, + + EMAC_PLL_SHIFT = 0, + EMAC_PLL_MASK = 0x3, + EMAC_PLL_SELECT_NEW = 0x0, + EMAC_PLL_SELECT_CODEC = 0x1, + EMAC_PLL_SELECT_GENERAL = 0x2, +}; + /* CRU_CLKSEL25_CON */ enum { SPI1_PLL_SHIFT = 0xf, diff --git a/drivers/clk/clk_rk3288.c b/drivers/clk/clk_rk3288.c index 2a85e93a6c..a110a1c160 100644 --- a/drivers/clk/clk_rk3288.c +++ b/drivers/clk/clk_rk3288.c @@ -326,6 +326,17 @@ static int pll_para_config(ulong freq_hz, struct pll_div *div, uint *ext_div) return 0; } +static int rockchip_mac_set_clk(struct rk3288_cru *cru, + int periph, uint freq) +{ + /* Assuming mac_clk is fed by an external clock */ + rk_clrsetreg(&cru->cru_clksel_con[21], + RMII_EXTCLK_MASK << RMII_EXTCLK_SHIFT, + RMII_EXTCLK_SELECT_EXT_CLK << RMII_EXTCLK_SHIFT); + + return 0; +} + static int rockchip_vop_set_clk(struct rk3288_cru *cru, struct rk3288_grf *grf, int periph, unsigned int rate_hz) { @@ -759,6 +770,9 @@ static ulong rk3288_set_periph_rate(struct udevice *dev, int periph, ulong rate) new_rate = rockchip_spi_set_clk(cru, gclk_rate, periph, rate); break; #ifndef CONFIG_SPL_BUILD + case SCLK_MAC: + new_rate = rockchip_mac_set_clk(priv->cru, periph, rate); + break; case DCLK_VOP0: case DCLK_VOP1: new_rate = rockchip_vop_set_clk(cru, priv->grf, periph, rate); |
