Merge branch 'master' of git://git.denx.de/u-boot-video

* 'master' of git://git.denx.de/u-boot-video:
  video: atmel/lcd: add LCD driver for new Atmel SoC
  video: cfb_console: flush dcache for frame buffer in DRAM
  cfb_console: Ignore bell character
  cfb_console: Add console_clear_line function
  cfb_console: Fix function console_back
  omap3_dss: cosmetic changes
  omap3_dss: add optional framebuffer
  mx53loco: Add LCD support
  mx5: Rename mx51_fb_init()
  mx53: Allow IPUv3 driver to also work on mx53
  mx51evk: Add LCD support
  EXYNOS: display 32bpp bitmap TIZEN logo
  create lib/tizen directory
  LCD: display 32bpp decompressed bitmap image
  common/lcd.c: reduce one CONFIG_LCD_LOGO ifdef
  common/lcd.c: reduce some CONFIG_LCD_*_LOGO ifdefs
  common/lcd.c: use ARRAY_SIZE
  cmd_bmp.c: make bmp_display() usable by drivers or board code
  LCD: support another s6e8ax0 panel type
  LCD: change s6e8ax0 panel gamma value
  include/video.h: drop unused video_printf()

Signed-off-by: Wolfgang Denk <wd@denx.de>

8 files changed, 306 insertions, 6 deletions

diff --git a/include/atmel_hlcdc.h b/include/atmel_hlcdc.h
new file mode 100644
index 0000000000..945b30acb0
--- /dev/null
+++ b/include/atmel_hlcdc.h
@@ -0,0 +1,231 @@
+/*
+ *  Header file for AT91/AT32 MULTI LAYER LCD Controller
+ *
+ *  Data structure and register user interface
+ *
+ *  Copyright (C) 2012 Atmel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ATMEL_HLCDC_H__
+#define __ATMEL_HLCDC_H__
+
+/* Atmel multi layer lcdc hardware registers */
+struct atmel_hlcd_regs {
+	u32	lcdc_lcdcfg0;
+	u32	lcdc_lcdcfg1;
+	u32	lcdc_lcdcfg2;
+	u32	lcdc_lcdcfg3;
+	u32	lcdc_lcdcfg4;
+	u32	lcdc_lcdcfg5;
+	u32	lcdc_lcdcfg6;
+	u32	res1;
+	u32	lcdc_lcden;
+	u32	lcdc_lcddis;
+	u32	lcdc_lcdsr;
+	u32	res2;
+	u32	lcdc_lcdidr;
+	u32	res3[3];
+	u32	lcdc_basecher;
+	u32	res4[3];
+	u32	lcdc_baseidr;
+	u32	res5[3];
+	u32	lcdc_baseaddr;
+	u32	lcdc_basectrl;
+	u32	lcdc_basenext;
+	u32	lcdc_basecfg0;
+	u32	lcdc_basecfg1;
+	u32	lcdc_basecfg2;
+	u32	lcdc_basecfg3;
+	u32	lcdc_basecfg4;
+};
+
+#define LCDC_LCDCFG0_CLKPOL	(0x1 << 0)
+#define LCDC_LCDCFG0_CLKSEL	(0x1 << 2)
+#define LCDC_LCDCFG0_CLKPWMSEL	(0x1 << 3)
+#define LCDC_LCDCFG0_CGDISBASE	(0x1 << 8)
+#define LCDC_LCDCFG0_CGDISOVR1	(0x1 << 9)
+#define LCDC_LCDCFG0_CGDISHEO	(0x1 << 11)
+#define LCDC_LCDCFG0_CGDISHCR	(0x1 << 12)
+#define LCDC_LCDCFG0_CLKDIV_Pos	16
+#define LCDC_LCDCFG0_CLKDIV_Msk	(0xff << LCDC_LCDCFG0_CLKDIV_Pos)
+#define LCDC_LCDCFG0_CLKDIV(value) \
+	((LCDC_LCDCFG0_CLKDIV_Msk & ((value) << LCDC_LCDCFG0_CLKDIV_Pos)))
+
+#define LCDC_LCDCFG1_HSPW_Pos	0
+#define LCDC_LCDCFG1_HSPW_Msk	(0x3f << LCDC_LCDCFG1_HSPW_Pos)
+#define LCDC_LCDCFG1_HSPW(value) \
+	((LCDC_LCDCFG1_HSPW_Msk & ((value) << LCDC_LCDCFG1_HSPW_Pos)))
+#define LCDC_LCDCFG1_VSPW_Pos	16
+#define LCDC_LCDCFG1_VSPW_Msk	(0x3f << LCDC_LCDCFG1_VSPW_Pos)
+#define LCDC_LCDCFG1_VSPW(value) \
+	((LCDC_LCDCFG1_VSPW_Msk & ((value) << LCDC_LCDCFG1_VSPW_Pos)))
+
+#define LCDC_LCDCFG2_VFPW_Pos	0
+#define LCDC_LCDCFG2_VFPW_Msk	(0x3f << LCDC_LCDCFG2_VFPW_Pos)
+#define LCDC_LCDCFG2_VFPW(value) \
+	((LCDC_LCDCFG2_VFPW_Msk & ((value) << LCDC_LCDCFG2_VFPW_Pos)))
+#define LCDC_LCDCFG2_VBPW_Pos	16
+#define LCDC_LCDCFG2_VBPW_Msk	(0x3f << LCDC_LCDCFG2_VBPW_Pos)
+#define LCDC_LCDCFG2_VBPW(value) \
+	((LCDC_LCDCFG2_VBPW_Msk & ((value) << LCDC_LCDCFG2_VBPW_Pos)))
+
+#define LCDC_LCDCFG3_HFPW_Pos	0
+#define LCDC_LCDCFG3_HFPW_Msk	(0xff << LCDC_LCDCFG3_HFPW_Pos)
+#define LCDC_LCDCFG3_HFPW(value) \
+	((LCDC_LCDCFG3_HFPW_Msk & ((value) << LCDC_LCDCFG3_HFPW_Pos)))
+#define LCDC_LCDCFG3_HBPW_Pos	16
+#define LCDC_LCDCFG3_HBPW_Msk	(0xff << LCDC_LCDCFG3_HBPW_Pos)
+#define LCDC_LCDCFG3_HBPW(value) \
+	((LCDC_LCDCFG3_HBPW_Msk & ((value) << LCDC_LCDCFG3_HBPW_Pos)))
+
+#define LCDC_LCDCFG4_PPL_Pos	0
+#define LCDC_LCDCFG4_PPL_Msk	(0x7ff << LCDC_LCDCFG4_PPL_Pos)
+#define LCDC_LCDCFG4_PPL(value) \
+	((LCDC_LCDCFG4_PPL_Msk & ((value) << LCDC_LCDCFG4_PPL_Pos)))
+#define LCDC_LCDCFG4_RPF_Pos	16
+#define LCDC_LCDCFG4_RPF_Msk	(0x7ff << LCDC_LCDCFG4_RPF_Pos)
+#define LCDC_LCDCFG4_RPF(value) \
+	((LCDC_LCDCFG4_RPF_Msk & ((value) << LCDC_LCDCFG4_RPF_Pos)))
+
+#define LCDC_LCDCFG5_HSPOL	(0x1 << 0)
+#define LCDC_LCDCFG5_VSPOL	(0x1 << 1)
+#define LCDC_LCDCFG5_VSPDLYS	(0x1 << 2)
+#define LCDC_LCDCFG5_VSPDLYE	(0x1 << 3)
+#define LCDC_LCDCFG5_DISPPOL	(0x1 << 4)
+#define LCDC_LCDCFG5_SERIAL	(0x1 << 5)
+#define LCDC_LCDCFG5_DITHER	(0x1 << 6)
+#define LCDC_LCDCFG5_DISPDLY	(0x1 << 7)
+#define LCDC_LCDCFG5_MODE_Pos	8
+#define LCDC_LCDCFG5_MODE_Msk	(0x3 << LCDC_LCDCFG5_MODE_Pos)
+#define LCDC_LCDCFG5_MODE_OUTPUT_12BPP	(0x0 << 8)
+#define LCDC_LCDCFG5_MODE_OUTPUT_16BPP	(0x1 << 8)
+#define LCDC_LCDCFG5_MODE_OUTPUT_18BPP	(0x2 << 8)
+#define LCDC_LCDCFG5_MODE_OUTPUT_24BPP	(0x3 << 8)
+#define LCDC_LCDCFG5_VSPSU		(0x1 << 12)
+#define LCDC_LCDCFG5_VSPHO		(0x1 << 13)
+#define LCDC_LCDCFG5_GUARDTIME_Pos	16
+#define LCDC_LCDCFG5_GUARDTIME_Msk	(0x1f << LCDC_LCDCFG5_GUARDTIME_Pos)
+#define LCDC_LCDCFG5_GUARDTIME(value) \
+	((LCDC_LCDCFG5_GUARDTIME_Msk & ((value) << LCDC_LCDCFG5_GUARDTIME_Pos)))
+
+#define LCDC_LCDCFG6_PWMPS_Pos		0
+#define LCDC_LCDCFG6_PWMPS_Msk		(0x7 << LCDC_LCDCFG6_PWMPS_Pos)
+#define LCDC_LCDCFG6_PWMPS(value) \
+	((LCDC_LCDCFG6_PWMPS_Msk & ((value) << LCDC_LCDCFG6_PWMPS_Pos)))
+#define LCDC_LCDCFG6_PWMPOL		(0x1 << 4)
+#define LCDC_LCDCFG6_PWMCVAL_Pos	8
+#define LCDC_LCDCFG6_PWMCVAL_Msk	(0xff << LCDC_LCDCFG6_PWMCVAL_Pos)
+#define LCDC_LCDCFG6_PWMCVAL(value) \
+	((LCDC_LCDCFG6_PWMCVAL_Msk & ((value) << LCDC_LCDCFG6_PWMCVAL_Pos)))
+
+#define LCDC_LCDEN_CLKEN	(0x1 << 0)
+#define LCDC_LCDEN_SYNCEN	(0x1 << 1)
+#define LCDC_LCDEN_DISPEN	(0x1 << 2)
+#define LCDC_LCDEN_PWMEN	(0x1 << 3)
+
+#define LCDC_LCDDIS_CLKDIS	(0x1 << 0)
+#define LCDC_LCDDIS_SYNCDIS	(0x1 << 1)
+#define LCDC_LCDDIS_DISPDIS	(0x1 << 2)
+#define LCDC_LCDDIS_PWMDIS	(0x1 << 3)
+#define LCDC_LCDDIS_CLKRST	(0x1 << 8)
+#define LCDC_LCDDIS_SYNCRST	(0x1 << 9)
+#define LCDC_LCDDIS_DISPRST	(0x1 << 10)
+#define LCDC_LCDDIS_PWMRST	(0x1 << 11)
+
+#define LCDC_LCDSR_CLKSTS	(0x1 << 0)
+#define LCDC_LCDSR_LCDSTS	(0x1 << 1)
+#define LCDC_LCDSR_DISPSTS	(0x1 << 2)
+#define LCDC_LCDSR_PWMSTS	(0x1 << 3)
+#define LCDC_LCDSR_SIPSTS	(0x1 << 4)
+
+#define LCDC_LCDIDR_SOFID	(0x1 << 0)
+#define LCDC_LCDIDR_DISID	(0x1 << 1)
+#define LCDC_LCDIDR_DISPID	(0x1 << 2)
+#define LCDC_LCDIDR_FIFOERRID	(0x1 << 4)
+#define LCDC_LCDIDR_BASEID	(0x1 << 8)
+#define LCDC_LCDIDR_OVR1ID	(0x1 << 9)
+#define LCDC_LCDIDR_HEOID	(0x1 << 11)
+#define LCDC_LCDIDR_HCRID	(0x1 << 12)
+
+#define LCDC_BASECHER_CHEN	(0x1 << 0)
+#define LCDC_BASECHER_UPDATEEN	(0x1 << 1)
+#define LCDC_BASECHER_A2QEN	(0x1 << 2)
+
+#define LCDC_BASEIDR_DMA	(0x1 << 2)
+#define LCDC_BASEIDR_DSCR	(0x1 << 3)
+#define LCDC_BASEIDR_ADD	(0x1 << 4)
+#define LCDC_BASEIDR_DONE	(0x1 << 5)
+#define LCDC_BASEIDR_OVR	(0x1 << 6)
+
+#define LCDC_BASECTRL_DFETCH	(0x1 << 0)
+#define LCDC_BASECTRL_LFETCH	(0x1 << 1)
+#define LCDC_BASECTRL_DMAIEN	(0x1 << 2)
+#define LCDC_BASECTRL_DSCRIEN	(0x1 << 3)
+#define LCDC_BASECTRL_ADDIEN	(0x1 << 4)
+#define LCDC_BASECTRL_DONEIEN	(0x1 << 5)
+
+#define LCDC_BASECFG0_BLEN_Pos		4
+#define LCDC_BASECFG0_BLEN_AHB_SINGLE	(0x0 << 4)
+#define LCDC_BASECFG0_BLEN_AHB_INCR4	(0x1 << 4)
+#define LCDC_BASECFG0_BLEN_AHB_INCR8	(0x2 << 4)
+#define LCDC_BASECFG0_BLEN_AHB_INCR16	(0x3 << 4)
+#define LCDC_BASECFG0_DLBO		(0x1 << 8)
+
+#define LCDC_BASECFG1_RGBMODE_12BPP_RGB_444		(0x0 << 4)
+#define LCDC_BASECFG1_RGBMODE_16BPP_ARGB_4444		(0x1 << 4)
+#define LCDC_BASECFG1_RGBMODE_16BPP_RGBA_4444		(0x2 << 4)
+#define LCDC_BASECFG1_RGBMODE_16BPP_RGB_565		(0x3 << 4)
+#define LCDC_BASECFG1_RGBMODE_16BPP_TRGB_1555		(0x4 << 4)
+#define LCDC_BASECFG1_RGBMODE_18BPP_RGB_666		(0x5 << 4)
+#define LCDC_BASECFG1_RGBMODE_18BPP_RGB_666_PACKED	(0x6 << 4)
+#define LCDC_BASECFG1_RGBMODE_19BPP_TRGB_1666		(0x7 << 4)
+#define LCDC_BASECFG1_RGBMODE_19BPP_TRGB_PACKED		(0x8 << 4)
+#define LCDC_BASECFG1_RGBMODE_24BPP_RGB_888		(0x9 << 4)
+#define LCDC_BASECFG1_RGBMODE_24BPP_RGB_888_PACKED	(0xA << 4)
+#define LCDC_BASECFG1_RGBMODE_25BPP_TRGB_1888		(0xB << 4)
+#define LCDC_BASECFG1_RGBMODE_32BPP_ARGB_8888		(0xC << 4)
+#define LCDC_BASECFG1_RGBMODE_32BPP_RGBA_8888		(0xD << 4)
+
+#define LCDC_BASECFG2_XSTRIDE_Pos 0
+#define LCDC_BASECFG2_XSTRIDE_Msk (0xffffffff << LCDC_BASECFG2_XSTRIDE_Pos)
+#define LCDC_BASECFG2_XSTRIDE(value) \
+	((LCDC_BASECFG2_XSTRIDE_Msk & ((value) << LCDC_BASECFG2_XSTRIDE_Pos)))
+
+#define LCDC_BASECFG3_BDEF_Pos	0
+#define LCDC_BASECFG3_BDEF_Msk	(0xff << LCDC_BASECFG3_BDEF_Pos)
+#define LCDC_BASECFG3_BDEF(value) \
+	((LCDC_BASECFG3_BDEF_Msk & ((value) << LCDC_BASECFG3_BDEF_Pos)))
+#define LCDC_BASECFG3_GDEF_Pos	8
+#define LCDC_BASECFG3_GDEF_Msk	(0xff << LCDC_BASECFG3_GDEF_Pos)
+#define LCDC_BASECFG3_GDEF(value) \
+	((LCDC_BASECFG3_GDEF_Msk & ((value) << LCDC_BASECFG3_GDEF_Pos)))
+#define LCDC_BASECFG3_RDEF_Pos	16
+#define LCDC_BASECFG3_RDEF_Msk	(0xff << LCDC_BASECFG3_RDEF_Pos)
+#define LCDC_BASECFG3_RDEF(value) \
+	((LCDC_BASECFG3_RDEF_Msk & ((value) << LCDC_BASECFG3_RDEF_Pos)))
+
+#define LCDC_BASECFG4_DMA	(0x1 << 8)
+#define LCDC_BASECFG4_REP	(0x1 << 9)
+
+struct lcd_dma_desc {
+	u32	address;
+	u32	control;
+	u32	next;
+};
+
+#define ATMEL_LCDC_LUT(n)	(0x0400 + ((n)*4))
+
+#endif /* __ATMEL_HLCDC_H__ */
diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h
index 1477b213bd..58b6f1c10d 100644
--- a/include/configs/mx51evk.h
+++ b/include/configs/mx51evk.h
@@ -51,7 +51,7 @@
 /*
  * Size of malloc() pool
  */
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2 * 1024 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(10 * 1024 * 1024)
 
 #define CONFIG_BOARD_LATE_INIT
 
@@ -123,6 +123,17 @@
 #define CONFIG_MXC_USB_PORTSC	PORT_PTS_ULPI
 #define CONFIG_MXC_USB_FLAGS	MXC_EHCI_POWER_PINS_ENABLED
 
+/* Framebuffer and LCD */
+#define CONFIG_PREBOOT
+#define CONFIG_VIDEO
+#define CONFIG_VIDEO_MX5
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_LOGO
+
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_CONS_INDEX		1
diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h
index eab0e27fb5..99daafb900 100644
--- a/include/configs/mx53loco.h
+++ b/include/configs/mx53loco.h
@@ -38,7 +38,7 @@
 #define CONFIG_INITRD_TAG
 
 /* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2 * 1024 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(10 * 1024 * 1024)
 
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_BOARD_LATE_INIT
@@ -220,4 +220,15 @@
 	#define CONFIG_LIBATA
 #endif
 
+/* Framebuffer and LCD */
+#define CONFIG_PREBOOT
+#define CONFIG_VIDEO
+#define CONFIG_VIDEO_MX5
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_LOGO
+
 #endif				/* __CONFIG_H */
diff --git a/include/configs/trats.h b/include/configs/trats.h
index ef6510e67d..5e38de2bc8 100644
--- a/include/configs/trats.h
+++ b/include/configs/trats.h
@@ -34,6 +34,7 @@
 #define CONFIG_S5P		/* which is in a S5P Family */
 #define CONFIG_EXYNOS4210	/* which is in a EXYNOS4210 */
 #define CONFIG_TRATS		/* working with TRATS */
+#define CONFIG_TIZEN		/* TIZEN lib */
 
 #include <asm/arch/cpu.h>	/* get chip and board defs */
 
@@ -217,9 +218,12 @@
 /* LCD */
 #define CONFIG_EXYNOS_FB
 #define CONFIG_LCD
+#define CONFIG_CMD_BMP
+#define CONFIG_BMP_32BPP
 #define CONFIG_FB_ADDR		0x52504000
 #define CONFIG_S6E8AX0
 #define CONFIG_EXYNOS_MIPI_DSIM
-#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE	(1280 * 720 * 4)
+#define CONFIG_VIDEO_BMP_GZIP
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 120 * 4) + (1 << 12))
 
 #endif	/* __CONFIG_H */
diff --git a/include/ipu_pixfmt.h b/include/ipu_pixfmt.h
index 656f605462..0019898d51 100644
--- a/include/ipu_pixfmt.h
+++ b/include/ipu_pixfmt.h
@@ -76,6 +76,6 @@
 #define IPU_PIX_FMT_YVU422P fourcc('Y', 'V', '1', '6')	/*< 16 YVU 4:2:2 */
 #define IPU_PIX_FMT_YUV422P fourcc('4', '2', '2', 'P')	/*< 16 YUV 4:2:2 */
 
-int mx51_fb_init(struct fb_videomode *mode, uint8_t disp, uint32_t pixfmt);
+int ipuv3_fb_init(struct fb_videomode *mode, uint8_t disp, uint32_t pixfmt);
 
 #endif
diff --git a/include/lcd.h b/include/lcd.h
index 3d9ef16710..6e0a2a3915 100644
--- a/include/lcd.h
+++ b/include/lcd.h
@@ -55,6 +55,7 @@ extern void lcd_initcolregs (void);
 
 /* gunzip_bmp used if CONFIG_VIDEO_BMP_GZIP */
 extern struct bmp_image *gunzip_bmp(unsigned long addr, unsigned long *lenp);
+extern int bmp_display(ulong addr, int x, int y);
 
 #if defined CONFIG_MPC823
 /*
@@ -157,7 +158,7 @@ typedef struct vidinfo {
 	struct	pxafb_info pxa;
 } vidinfo_t;
 
-#elif defined(CONFIG_ATMEL_LCD)
+#elif defined(CONFIG_ATMEL_LCD) || defined(CONFIG_ATMEL_HLCD)
 
 typedef struct vidinfo {
 	ushort vl_col;		/* Number of columns (i.e. 640) */
@@ -169,6 +170,7 @@ typedef struct vidinfo {
 	u_long vl_bpix;		/* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */
 	u_long vl_tft;		/* 0 = passive, 1 = TFT */
 	u_long vl_cont_pol_low;	/* contrast polarity is low */
+	u_long vl_clk_pol;	/* clock polarity */
 
 	/* Horizontal control register. */
 	u_long vl_hsync_len;	/* Length of horizontal sync */
@@ -190,6 +192,13 @@ enum {
 	FIMD_CPU_INTERFACE = 2,
 };
 
+enum exynos_fb_rgb_mode_t {
+	MODE_RGB_P = 0,
+	MODE_BGR_P = 1,
+	MODE_RGB_S = 2,
+	MODE_BGR_S = 3,
+};
+
 typedef struct vidinfo {
 	ushort vl_col;		/* Number of columns (i.e. 640) */
 	ushort vl_row;		/* Number of rows (i.e. 480) */
@@ -235,6 +244,12 @@ typedef struct vidinfo {
 	unsigned int wr_setup;
 	unsigned int wr_act;
 	unsigned int wr_hold;
+	unsigned int logo_on;
+	unsigned int logo_width;
+	unsigned int logo_height;
+	unsigned long logo_addr;
+	unsigned int rgb_mode;
+	unsigned int resolution;
 
 	/* parent clock name(MPLL, EPLL or VPLL) */
 	unsigned int pclk_name;
diff --git a/include/libtizen.h b/include/libtizen.h
new file mode 100644
index 0000000000..f669d730ad
--- /dev/null
+++ b/include/libtizen.h
@@ -0,0 +1,29 @@
+/*
+ * (C) Copyright 2012 Samsung Electronics
+ * Donghwa Lee <dh09.lee@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * aint with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _LIBTIZEN_H_
+#define _LIBTIZEN_H_
+
+#define HD_RESOLUTION	0
+
+void get_tizen_logo_info(vidinfo_t *vid);
+
+#endif	/* _LIBTIZEN_H_ */
diff --git a/include/video.h b/include/video.h
index efcc682a29..9519ceaf98 100644
--- a/include/video.h
+++ b/include/video.h
@@ -14,6 +14,5 @@
 int	video_init	(void *videobase);
 void	video_putc	(const char c);
 void	video_puts	(const char *s);
-void	video_printf	(const char *fmt, ...);
 
 #endif