Merge branch 'master' of git://git.denx.de/u-boot-blackfin

29 files changed, 567 insertions, 51 deletions

diff --git a/include/configs/bct-brettl2.h b/include/configs/bct-brettl2.h
new file mode 100644
index 0000000000..09691d3737
--- /dev/null
+++ b/include/configs/bct-brettl2.h
@@ -0,0 +1,155 @@
+/*
+ * U-boot - Configuration file for BF536 brettl2 board
+ */
+
+#ifndef __CONFIG_BCT_BRETTL2_H__
+#define __CONFIG_BCT_BRETTL2_H__
+
+#include <asm/config-pre.h>
+
+
+/*
+ * Processor Settings
+ */
+#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS
+
+
+/*
+ * Clock Settings
+ *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
+ */
+/* CONFIG_CLKIN_HZ is any value in Hz					*/
+#define CONFIG_CLKIN_HZ			16384000
+/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
+/*                                                1 = CLKIN / 2		*/
+#define CONFIG_CLKIN_HALF		0
+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
+/*                                                1 = bypass PLL	*/
+#define CONFIG_PLL_BYPASS		0
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
+/* Values can range from 0-63 (where 0 means 64)			*/
+#define CONFIG_VCO_MULT			24
+/* CCLK_DIV controls the core clock divider				*/
+/* Values can be 1, 2, 4, or 8 ONLY					*/
+#define CONFIG_CCLK_DIV			1
+/* SCLK_DIV controls the system clock divider				*/
+/* Values can range from 1-15						*/
+#define CONFIG_SCLK_DIV			3
+#define CONFIG_VR_CTL_VAL       (VLEV_110 | GAIN_20 | FREQ_1000)
+
+
+/*
+ * Memory Settings
+ */
+#define CONFIG_MEM_ADD_WDTH	9
+#define CONFIG_MEM_SIZE		32
+
+
+/*
+ * SDRAM Settings
+ */
+#define CONFIG_EBIU_SDRRC_VAL	0x07f6
+#define CONFIG_EBIU_SDGCTL_VAL	0x9111cd
+
+#define CONFIG_EBIU_AMGCTL_VAL	(AMBEN_ALL)
+#define CONFIG_EBIU_AMBCTL0_VAL	(B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
+#define CONFIG_EBIU_AMBCTL1_VAL	(B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
+
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)
+
+
+/*
+ * Network Settings
+ */
+#ifndef __ADSPBF534__
+#define ADI_CMDS_NETWORK	1
+#define CONFIG_BFIN_MAC		1
+#define CONFIG_NETCONSOLE	1
+#define CONFIG_NET_MULTI	1
+#define CONFIG_HOSTNAME		brettl2
+#define CONFIG_IPADDR		192.168.233.224
+#define CONFIG_GATEWAYIP	192.168.233.1
+#define CONFIG_SERVERIP		192.168.233.53
+#define CONFIG_ROOTPATH		/romfs/brettl2
+/* Uncomment next line to use fixed MAC address */
+/* #define CONFIG_ETHADDR	02:80:ad:20:31:e8 */
+#endif
+
+
+/*
+ * Flash Settings
+ */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_FLASH_BASE			0x20000000
+#define CONFIG_SYS_MAX_FLASH_BANKS		1
+#define CONFIG_SYS_MAX_FLASH_SECT		135
+
+
+/*
+ * Env Storage Settings
+ */
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_OFFSET	0x4000
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x10000
+
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
+#define ENV_IS_EMBEDDED
+#else
+#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
+#endif
+
+#ifdef ENV_IS_EMBEDDED
+/* WARNING - the following is hand-optimized to fit within
+ * the sector before the environment sector. If it throws
+ * an error during compilation remove an object here to get
+ * it linked after the configuration sector.
+ */
+# define LDS_BOARD_TEXT \
+        arch/blackfin/cpu/traps.o            (.text .text.*); \
+        arch/blackfin/cpu/interrupt.o        (.text .text.*); \
+        arch/blackfin/cpu/serial.o           (.text .text.*); \
+        common/dlmalloc.o               (.text .text.*); \
+        lib/crc32.o             (.text .text.*); \
+        . = DEFINED(env_offset) ? env_offset : .; \
+        common/env_embedded.o           (.text .text.*);
+#endif
+
+
+/*
+ * I2C Settings
+ */
+#define CONFIG_BFIN_TWI_I2C	1
+#define CONFIG_HARD_I2C		1
+
+
+/*
+ * Misc Settings
+ */
+#define CONFIG_BOOTDELAY	1
+#define CONFIG_LOADADDR		0x800000
+#define CONFIG_MISC_INIT_R
+#define CONFIG_UART_CONSOLE	0
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+
+/*
+ * Pull in common ADI header for remaining command/environment setup
+ */
+#include <configs/bfin_adi_common.h>
+
+/* disable unnecessary features */
+#undef CONFIG_BOOTM_RTEMS
+#undef CONFIG_BZIP2
+#undef CONFIG_KALLSYMS
+
+#endif
diff --git a/include/configs/bf518f-ezbrd.h b/include/configs/bf518f-ezbrd.h
index 6eec1c91a7..64ca9ed439 100644
--- a/include/configs/bf518f-ezbrd.h
+++ b/include/configs/bf518f-ezbrd.h
@@ -11,7 +11,6 @@
 /*
  * Processor Settings
  */
-#define CONFIG_BFIN_CPU             bf518-0.0
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_PARA
 
 
diff --git a/include/configs/bf526-ezbrd.h b/include/configs/bf526-ezbrd.h
index 82396d0ed2..4c30c25392 100644
--- a/include/configs/bf526-ezbrd.h
+++ b/include/configs/bf526-ezbrd.h
@@ -11,7 +11,6 @@
 /*
  * Processor Settings
  */
-#define CONFIG_BFIN_CPU             bf526-0.0
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_PARA
 
 
@@ -53,7 +52,7 @@
 #define CONFIG_EBIU_AMBCTL0_VAL	(B1WAT_15 | B1RAT_15 | B1HT_3 | B1RDYPOL | B0WAT_15 | B0RAT_15 | B0HT_3 | B0RDYPOL)
 #define CONFIG_EBIU_AMBCTL1_VAL	(B3WAT_15 | B3RAT_15 | B3HT_3 | B3RDYPOL | B2WAT_15 | B2RAT_15 | B2HT_3 | B2RDYPOL)
 
-#define CONFIG_SYS_MONITOR_LEN	(512 * 1024)
+#define CONFIG_SYS_MONITOR_LEN	(768 * 1024)
 #define CONFIG_SYS_MALLOC_LEN	(512 * 1024)
 
 
@@ -62,7 +61,8 @@
  * (can't be used same time as ethernet)
  */
 #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
-#define CONFIG_BFIN_NFC
+# define CONFIG_BFIN_NFC
+# define CONFIG_BFIN_NFC_BOOTROM_ECC
 #endif
 #ifdef CONFIG_BFIN_NFC
 #define CONFIG_BFIN_NFC_CTL_VAL	0x0033
diff --git a/include/configs/bf527-ad7160-eval.h b/include/configs/bf527-ad7160-eval.h
index eb3a2b7dc1..14ade1b1e6 100644
--- a/include/configs/bf527-ad7160-eval.h
+++ b/include/configs/bf527-ad7160-eval.h
@@ -11,7 +11,6 @@
 /*
  * Processor Settings
  */
-#define CONFIG_BFIN_CPU             bf527-0.2
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_SPI_MASTER
 
 
@@ -130,7 +129,7 @@
 #define CONFIG_MMC
 #define CONFIG_CMD_EXT2
 #define CONFIG_SPI_MMC
-#define CONFIG_SPI_MMC_DEFAULT_CS (7 + GPIO_PH3)
+#define CONFIG_SPI_MMC_DEFAULT_CS (MAX_CTRL_CS + GPIO_PH3)
 
 
 /*
diff --git a/include/configs/bf527-ezkit.h b/include/configs/bf527-ezkit.h
index 07e4ce86e1..54fc063f9a 100644
--- a/include/configs/bf527-ezkit.h
+++ b/include/configs/bf527-ezkit.h
@@ -11,7 +11,6 @@
 /*
  * Processor Settings
  */
-#define CONFIG_BFIN_CPU             bf527-0.0
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_PARA
 
 
diff --git a/include/configs/bf527-sdp.h b/include/configs/bf527-sdp.h
new file mode 100644
index 0000000000..358284619c
--- /dev/null
+++ b/include/configs/bf527-sdp.h
@@ -0,0 +1,121 @@
+/*
+ * U-boot - Configuration file for BF527 SDP board
+ */
+
+#ifndef __CONFIG_BF527_SDP_H__
+#define __CONFIG_BF527_SDP_H__
+
+#include <asm/config-pre.h>
+
+
+/*
+ * Processor Settings
+ */
+#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_PARA
+
+
+/*
+ * Clock Settings
+ *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
+ */
+/* CONFIG_CLKIN_HZ is any value in Hz					*/
+#define CONFIG_CLKIN_HZ			24000000
+/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
+/*                                                1 = CLKIN / 2		*/
+#define CONFIG_CLKIN_HALF		0
+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
+/*                                                1 = bypass PLL	*/
+#define CONFIG_PLL_BYPASS		0
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
+/* Values can range from 0-63 (where 0 means 64)			*/
+#define CONFIG_VCO_MULT			25
+/* CCLK_DIV controls the core clock divider				*/
+/* Values can be 1, 2, 4, or 8 ONLY					*/
+#define CONFIG_CCLK_DIV			1
+/* SCLK_DIV controls the system clock divider				*/
+/* Values can range from 1-15						*/
+#define CONFIG_SCLK_DIV			5
+
+#define CONFIG_PLL_LOCKCNT_VAL	0x0200
+#define CONFIG_PLL_CTL_VAL		0x2a00
+#define CONFIG_VR_CTL_VAL		0x7090
+
+
+/*
+ * Memory Settings
+ */
+#define CONFIG_MEM_ADD_WDTH	9
+#define CONFIG_MEM_SIZE		32
+
+#define CONFIG_EBIU_SDRRC_VAL	0x00FE
+#define CONFIG_EBIU_SDGCTL_VAL	0x8011998d
+
+#define CONFIG_EBIU_AMGCTL_VAL	(AMCKEN | AMBEN_ALL)
+#define CONFIG_EBIU_AMBCTL0_VAL	(B1WAT_15 | B1RAT_15 | B1HT_3 | B1RDYPOL | B0WAT_15 | B0RAT_15 | B0HT_3 | B0RDYPOL)
+#define CONFIG_EBIU_AMBCTL1_VAL	(B3WAT_15 | B3RAT_15 | B3HT_3 | B3RDYPOL | B2WAT_15 | B2RAT_15 | B2HT_3 | B2RDYPOL)
+
+#define CONFIG_SYS_MONITOR_LEN	(768 * 1024)
+#define CONFIG_SYS_MALLOC_LEN	(640 * 1024)
+
+
+/*
+ * Flash Settings
+ */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_BASE		0x20000000
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	259
+
+
+/*
+ * SPI Settings
+ */
+#define CONFIG_BFIN_SPI
+#define CONFIG_ENV_SPI_MAX_HZ	30000000
+#define CONFIG_SF_DEFAULT_SPEED	30000000
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_ALL
+
+
+/*
+ * Env Storage Settings
+ */
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OFFSET	0x10000
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x10000
+#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OFFSET	0x4000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x2000
+#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
+#endif
+
+
+/*
+ * I2C Settings
+ */
+#define CONFIG_BFIN_TWI_I2C	1
+#define CONFIG_HARD_I2C		1
+
+
+/*
+ * Misc Settings
+ */
+#define CONFIG_MISC_INIT_R
+#define CONFIG_UART_CONSOLE	0
+
+
+/*
+ * Pull in common ADI header for remaining command/environment setup
+ */
+#include <configs/bfin_adi_common.h>
+
+#endif
diff --git a/include/configs/bf533-ezkit.h b/include/configs/bf533-ezkit.h
index 95d3afa85c..e1bb594438 100644
--- a/include/configs/bf533-ezkit.h
+++ b/include/configs/bf533-ezkit.h
@@ -11,7 +11,6 @@
 /*
  * Processor Settings
  */
-#define CONFIG_BFIN_CPU             bf533-0.3
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS
 
 
diff --git a/include/configs/bf533-stamp.h b/include/configs/bf533-stamp.h
index f39bfee0a4..03bc811036 100644
--- a/include/configs/bf533-stamp.h
+++ b/include/configs/bf533-stamp.h
@@ -11,7 +11,6 @@
 /*
  * Processor Settings
  */
-#define CONFIG_BFIN_CPU             bf533-0.3
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS
 
 
@@ -93,10 +92,7 @@
 #define CONFIG_ENV_SPI_MAX_HZ	30000000
 #define CONFIG_SF_DEFAULT_SPEED	30000000
 #define CONFIG_SPI_FLASH
-#define CONFIG_SPI_FLASH_ATMEL
-#define CONFIG_SPI_FLASH_SPANSION
-#define CONFIG_SPI_FLASH_STMICRO
-#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_SPI_FLASH_ALL
 
 
 /*
diff --git a/include/configs/bf537-minotaur.h b/include/configs/bf537-minotaur.h
index 86aa1f61e6..0ba29bc0cd 100644
--- a/include/configs/bf537-minotaur.h
+++ b/include/configs/bf537-minotaur.h
@@ -24,7 +24,6 @@
 /*
  * Processor Settings
  */
-#define CONFIG_BFIN_CPU             bf537-0.2
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_SPI_MASTER
 
 
diff --git a/include/configs/bf537-pnav.h b/include/configs/bf537-pnav.h
index 39bbb41fb3..730ae279b6 100644
--- a/include/configs/bf537-pnav.h
+++ b/include/configs/bf537-pnav.h
@@ -11,7 +11,6 @@
 /*
  * Processor Settings
  */
-#define CONFIG_BFIN_CPU             bf537-0.2
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_SPI_MASTER
 
 
@@ -52,7 +51,7 @@
 #define CONFIG_EBIU_AMBCTL0_VAL	0x7BB033B0
 #define CONFIG_EBIU_AMBCTL1_VAL	0xFFC27BB0
 
-#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
 #define CONFIG_SYS_MALLOC_LEN		(128 * 1024)
 
 
diff --git a/include/configs/bf537-srv1.h b/include/configs/bf537-srv1.h
index 7e9dd36bce..559428f484 100644
--- a/include/configs/bf537-srv1.h
+++ b/include/configs/bf537-srv1.h
@@ -24,7 +24,6 @@
 /*
  * Processor Settings
  */
-#define CONFIG_BFIN_CPU             bf537-0.2
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_SPI_MASTER
 
 
diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h
index fc9784e083..22d31508eb 100644
--- a/include/configs/bf537-stamp.h
+++ b/include/configs/bf537-stamp.h
@@ -11,7 +11,6 @@
 /*
  * Processor Settings
  */
-#define CONFIG_BFIN_CPU             bf537-0.2
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS
 
 
@@ -89,10 +88,7 @@
 #define CONFIG_ENV_SPI_MAX_HZ	30000000
 #define CONFIG_SF_DEFAULT_SPEED	30000000
 #define CONFIG_SPI_FLASH
-#define CONFIG_SPI_FLASH_ATMEL
-#define CONFIG_SPI_FLASH_SPANSION
-#define CONFIG_SPI_FLASH_STMICRO
-#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_SPI_FLASH_ALL
 
 
 /*
diff --git a/include/configs/bf538f-ezkit.h b/include/configs/bf538f-ezkit.h
index 1c14b6bdd3..04ba210171 100644
--- a/include/configs/bf538f-ezkit.h
+++ b/include/configs/bf538f-ezkit.h
@@ -11,7 +11,6 @@
 /*
  * Processor Settings
  */
-#define CONFIG_BFIN_CPU             bf538-0.4
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS
 
 
@@ -86,10 +85,7 @@
 #define CONFIG_ENV_SPI_MAX_HZ	30000000
 #define CONFIG_SF_DEFAULT_SPEED	30000000
 #define CONFIG_SPI_FLASH
-#define CONFIG_SPI_FLASH_ATMEL
-#define CONFIG_SPI_FLASH_SPANSION
-#define CONFIG_SPI_FLASH_STMICRO
-#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_SPI_FLASH_ALL
 
 
 /*
diff --git a/include/configs/bf548-ezkit.h b/include/configs/bf548-ezkit.h
index 60cca0c07a..4412177ff0 100644
--- a/include/configs/bf548-ezkit.h
+++ b/include/configs/bf548-ezkit.h
@@ -11,7 +11,6 @@
 /*
  * Processor Settings
  */
-#define CONFIG_BFIN_CPU             bf548-0.0
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_PARA
 
 
@@ -183,6 +182,7 @@
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_RTC_BFIN
 #define CONFIG_UART_CONSOLE	1
+#define CONFIG_BFIN_SPI_IMG_SIZE 0x50000
 
 #ifndef __ADSPBF542__
 /* Don't waste time transferring a logo over the UART */
diff --git a/include/configs/bf561-acvilon.h b/include/configs/bf561-acvilon.h
index 0c0204fbd7..2b12c3fbe1 100644
--- a/include/configs/bf561-acvilon.h
+++ b/include/configs/bf561-acvilon.h
@@ -12,7 +12,6 @@
 /*
  * Processor Settings
  */
-#define CONFIG_BFIN_CPU				bf561-0.5
 #define CONFIG_BFIN_BOOT_MODE		BFIN_BOOT_BYPASS
 
 
diff --git a/include/configs/bf561-ezkit.h b/include/configs/bf561-ezkit.h
index 4e293b58a8..1557e14f52 100644
--- a/include/configs/bf561-ezkit.h
+++ b/include/configs/bf561-ezkit.h
@@ -11,7 +11,6 @@
 /*
  * Processor Settings
  */
-#define CONFIG_BFIN_CPU             bf561-0.3
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS
 
 
diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h
index 91dcaccb4f..608788a66f 100644
--- a/include/configs/bfin_adi_common.h
+++ b/include/configs/bfin_adi_common.h
@@ -47,6 +47,7 @@
 # endif
 # if defined(CONFIG_NAND_PLAT) || defined(CONFIG_DRIVER_NAND_BFIN)
 #  define CONFIG_CMD_NAND
+#  define CONFIG_CMD_NAND_LOCK_UNLOCK
 # endif
 # ifdef CONFIG_POST
 #  define CONFIG_CMD_DIAG
@@ -119,10 +120,12 @@
 /*
  * Env Settings
  */
-#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART)
-# define CONFIG_BOOTDELAY	-1
-#else
-# define CONFIG_BOOTDELAY	5
+#ifndef CONFIG_BOOTDELAY
+# if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART)
+#  define CONFIG_BOOTDELAY	-1
+# else
+#  define CONFIG_BOOTDELAY	5
+# endif
 #endif
 #ifndef CONFIG_BOOTCOMMAND
 # define CONFIG_BOOTCOMMAND	"run ramboot"
@@ -169,9 +172,12 @@
 #   define UBOOT_ENV_UPDATE \
 		"eeprom write $(loadaddr) 0x0 $(filesize)"
 #  else
+#   ifndef CONFIG_BFIN_SPI_IMG_SIZE
+#    define CONFIG_BFIN_SPI_IMG_SIZE 0x40000
+#   endif
 #   define UBOOT_ENV_UPDATE \
 		"sf probe " MK_STR(BFIN_BOOT_SPI_SSEL) ";" \
-		"sf erase 0 0x40000;" \
+		"sf erase 0 " MK_STR(CONFIG_BFIN_SPI_IMG_SIZE) ";" \
 		"sf write $(loadaddr) 0 $(filesize)"
 #  endif
 # elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
@@ -231,20 +237,28 @@
 #else
 # define NETWORK_ENV_SETTINGS
 #endif
+#ifndef BOARD_ENV_SETTINGS
+# define BOARD_ENV_SETTINGS
+#endif
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	NAND_ENV_SETTINGS \
 	NETWORK_ENV_SETTINGS \
-	FLASHBOOT_ENV_SETTINGS
+	FLASHBOOT_ENV_SETTINGS \
+	BOARD_ENV_SETTINGS
 
 /*
  * Network Settings
  */
 #ifdef CONFIG_CMD_NET
-# define CONFIG_IPADDR		192.168.0.15
 # define CONFIG_NETMASK		255.255.255.0
-# define CONFIG_GATEWAYIP	192.168.0.1
-# define CONFIG_SERVERIP	192.168.0.2
-# define CONFIG_ROOTPATH	/romfs
+# ifndef CONFIG_IPADDR
+#  define CONFIG_IPADDR		192.168.0.15
+#  define CONFIG_GATEWAYIP	192.168.0.1
+#  define CONFIG_SERVERIP	192.168.0.2
+# endif
+# ifndef CONFIG_ROOTPATH
+#  define CONFIG_ROOTPATH	/romfs
+# endif
 # ifdef CONFIG_CMD_DHCP
 #  ifndef CONFIG_SYS_AUTOLOAD
 #   define CONFIG_SYS_AUTOLOAD "no"
@@ -255,6 +269,18 @@
 #endif
 
 /*
+ * SPI Settings
+ */
+#ifdef CONFIG_SPI_FLASH_ALL
+# define CONFIG_SPI_FLASH_ATMEL
+# define CONFIG_SPI_FLASH_MACRONIX
+# define CONFIG_SPI_FLASH_SPANSION
+# define CONFIG_SPI_FLASH_SST
+# define CONFIG_SPI_FLASH_STMICRO
+# define CONFIG_SPI_FLASH_WINBOND
+#endif
+
+/*
  * I2C Settings
  */
 #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
diff --git a/include/configs/blackstamp.h b/include/configs/blackstamp.h
index 85f08ea888..3f5c95917d 100644
--- a/include/configs/blackstamp.h
+++ b/include/configs/blackstamp.h
@@ -24,7 +24,6 @@
 /* CPU Options
  * Be sure to set the Silicon Revision Correctly
  */
-#define CONFIG_BFIN_CPU		bf532-0.5
 #define CONFIG_BFIN_BOOT_MODE	BFIN_BOOT_SPI_MASTER
 
 /*
diff --git a/include/configs/blackvme.h b/include/configs/blackvme.h
new file mode 100644
index 0000000000..8b2bdc715d
--- /dev/null
+++ b/include/configs/blackvme.h
@@ -0,0 +1,246 @@
+/* U-boot for BlackVME. (C) Wojtek Skulski 2010.
+ * The board includes ADSP-BF561 rev. 0.5,
+ * 32-bit SDRAM (2 * MT48LC16M16A2TG or MT48LC32M16A2TG),
+ * Gigabit Ether AX88180 (ASIX) + 88E1111 rev. B2 (Marvell),
+ * SPI  boot flash on PF2 (M25P64 8MB, or M25P128 16 MB),
+ * FPGA boot flash on PF3 (M25P64 8MB, or M25P128 16 MB),
+ * Spartan6-LX150 (memory-mapped; both PPIs also connected).
+ * See http://www.skutek.com
+ */
+
+#ifndef __CONFIG_BLACKVME_H__
+#define __CONFIG_BLACKVME_H__
+
+#include <asm/config-pre.h>
+
+/* Debugging: Set these options if you're having problems
+ * #define CONFIG_DEBUG_EARLY_SERIAL
+ * #define DEBUG
+ * #define CONFIG_DEBUG_DUMP
+ * #define CONFIG_DEBUG_DUMP_SYMS
+ * CONFIG_PANIC_HANG means that the board will not auto-reboot
+ */
+#define CONFIG_PANIC_HANG 0
+
+/* CPU Options */
+#define CONFIG_BFIN_BOOT_MODE	BFIN_BOOT_SPI_MASTER
+
+/*
+ *		CLOCK SETTINGS CAVEAT
+ * You CANNOT just change the clock settings, esp. the SCLK.
+ * The SDRAM timing, SPI baud, and the serial UART baud
+ * use SCLK frequency to set their own frequencies. Therefore,
+ * if you change the SCLK_DIV, you may also have to adjust
+ * SDRAM refresh and other timings.
+ * --------------------------------------------------------------
+ *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ *		25 *  8 / 1 = 200 MHz
+ *		25 * 16 / 1 = 400 MHz
+ *		25 * 24 / 1 = 600 MHz
+ *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
+ *		25 *  8 / 2 = 100 MHz
+ *		25 * 24 / 6 = 100 MHz
+ *		25 * 24 / 5 = 120 MHz
+ *		25 * 16 / 3 = 133 MHz
+ * 25 MHz because the oscillator also feeds the ether chip.
+ * CONFIG_CLKIN_HZ is 25 MHz written in Hz
+ * CLKIN_HALF controls the DF bit in PLL_CTL
+ *	0 = CLKIN	1 = CLKIN / 2
+ * PLL_BYPASS controls the BYPASS bit in PLL_CTL
+ *	0 = do not bypass	1 = bypass PLL
+ * VCO_MULT = MSEL (multiplier) in PLL_CTL
+ * Values can range from 0-63 (where 0 means 64)
+ * CCLK_DIV = core clock divider (1, 2, 4, or 8 ONLY)
+ * SCLK_DIV = system clock divider, 1 to 15
+ */
+#define CONFIG_CLKIN_HZ		25000000
+#define CONFIG_CLKIN_HALF	0
+#define CONFIG_PLL_BYPASS	0
+#define CONFIG_VCO_MULT		8
+#define CONFIG_CCLK_DIV		1
+#define CONFIG_SCLK_DIV		2
+
+/*
+ * Ether chip in async memory space AMS3, same as BF561-EZ-KIT.
+ * Used in 32-bit mode. 16-bit mode not supported.
+ * http://docs.blackfin.uclinux.org/doku.php?id=hw:cards:ax88180
+ */
+/*
+ * Network settings using a dedicated 2nd ether card in PC
+ * Windows will automatically acquire IP of that card
+ * Then use the dedicated card IP + 1 for the board
+ * http://docs.blackfin.uclinux.org/doku.php?id=setting_up_the_network
+ */
+#define CONFIG_NET_MULTI
+
+#define CONFIG_DRIVER_AX88180	1
+#define AX88180_BASE		0x2c000000
+#define CONFIG_CMD_MII		/* enable probing PHY */
+
+#ifdef CONFIG_NET_MULTI		/* also used as the network enabler */
+# define CONFIG_HOSTNAME	blackvme	/* Bfin board  */
+# define CONFIG_IPADDR		169.254.144.145	/* Bfin board  */
+# define CONFIG_GATEWAYIP	169.254.144.144	/* dedic card  */
+# define CONFIG_SERVERIP	169.254.144.144	/* tftp server */
+# define CONFIG_NETMASK		255.255.255.0
+# define CONFIG_ROOTPATH	/export/uClinux-dist/romfs	/*NFS*/
+# define CFG_AUTOLOAD		"no"
+# define CONFIG_CMD_DHCP
+# define CONFIG_CMD_PING
+# define CONFIG_ENV_OVERWRITE	1	/* enable changing MAC at runtime */
+/* Comment out hardcoded MAC to enable MAC storage in EEPROM */
+/* # define CONFIG_ETHADDR	ff:ee:dd:cc:bb:aa */
+#endif
+
+/*
+ * SDRAM settings & memory map
+ */
+
+#define CONFIG_MEM_SIZE		64	/* 128, 64, 32, 16 */
+#define CONFIG_MEM_ADD_WDTH	 9	/* 8, 9, 10, 11    */
+/*
+ * SDRAM reference page
+ * http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
+ * NOTE: BlackVME populates only SDRAM bank 0
+ */
+/* CONFIG_EBIU_SDBCTL_VAL bank ctrl may be needed in future */
+#define CONFIG_EBIU_SDGCTL_VAL  0x91114d  /* global control */
+#define CONFIG_EBIU_SDRRC_VAL   0x306     /* refresh rate */
+
+/* Async memory global settings. (ASRAM, not SDRAM)
+ * HRM page 16-10. Global ASRAM control = 0x3F. Six lower bits = 1
+ * CLKOUT enabled, all async banks enabled, core has priority
+ * bank 0&1 16 bit (FPGA)
+ * bank 2&3 32 bit (ether and USB chips)
+ */
+#define CONFIG_EBIU_AMGCTL_VAL  0x3F   /* ASRAM setup */
+
+/* Async mem timing: BF561 HRM page 16-12 and 16-15.
+ * Default values 0xFFC2 FFC2 are the slowest supported.
+ * Example settings of CONFIG_EBIU_AMBCTL1_VAL
+ * 1. EZ-KIT settings: 0xFFC2 7BB0
+ * 2. Bank 3 good timing for AX88180 @ 125MHz = 0x8850 xxxx
+ *    See the following page:
+ *    http://docs.blackfin.uclinux.org/doku.php?id=hw:cards:ax88180
+ * 3. Bank 3 timing for AX88180 @ SCLK = 100 MHz:
+ * AX88180  WEN = 5 clocks  REN 6 clocks @ SCLK = 100 MHz
+ * One extra clock needed because AX88180 is asynchronous to CPU.
+ */
+                           /* bank 1   0 */
+#define CONFIG_EBIU_AMBCTL0_VAL 0xFFC2FFC2
+                           /* bank 3   2 */
+#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC2FFC2
+
+/* memory layout */
+
+#define CONFIG_SYS_MONITOR_LEN	(256 << 10)
+#define CONFIG_SYS_MALLOC_LEN	(384 << 10)
+
+/*
+ * Serial SPI Flash
+ * For the M25P64 SCK should be kept < 15 MHz
+ */
+#define CONFIG_BFIN_SPI
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OFFSET	0x40000
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x40000
+
+#define CONFIG_ENV_SPI_MAX_HZ	15000000
+#define CONFIG_SF_DEFAULT_SPEED	15000000
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+
+/*
+ * Interactive command settings
+ */
+
+#define CONFIG_SYS_LONGHELP	1
+#define CONFIG_CMDLINE_EDITING	1
+#define CONFIG_AUTO_COMPLETE	1
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BOOTLDR
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_CPLBINFO
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_ELF
+
+/*
+ * Default: boot from SPI flash.
+ * "sfboot" is a composite command defined in extra settings
+ */
+#define CONFIG_BOOTDELAY	5
+#define CONFIG_BOOTCOMMAND	"run sfboot"
+
+/*
+ * Console settings
+ */
+#define CONFIG_BAUDRATE		57600
+#define CONFIG_LOADS_ECHO	1
+#define CONFIG_UART_CONSOLE	0
+
+/*
+ * U-Boot environment variables. Use "printenv" to examine.
+ * http://docs.blackfin.uclinux.org/doku.php?id=bootloaders:u-boot:env
+ */
+#define CONFIG_BOOTARGS \
+	"root=/dev/mtdblock0 rw " \
+	"clkin_hz=" MK_STR(CONFIG_CLKIN_HZ) " " \
+	"earlyprintk=serial,uart0," \
+	MK_STR(CONFIG_BAUDRATE) " " \
+	"console=ttyBF0," MK_STR(CONFIG_BAUDRATE) " "
+
+/* Convenience env variables & commands.
+ * Reserve kernstart = 0x20000  = 128 kB for U-Boot.
+ * Reserve kernarea  = 0x500000 = 5 MB   for kernel (reasonable size).
+ * U-Boot image is saved at flash offset=0.
+ * Kernel image is saved at flash offset=$kernstart.
+ * Instructions. Ksave takes about a minute to complete.
+ *	1. Update U-Boot: run uget; run usave
+ *	2. Update kernel: run kget; run ksave
+ * After updating U-Boot also update the kernel per above instructions
+ * to make the saved environment consistent with the flash.
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"kernstart=0x20000\0" \
+	"kernarea=0x500000\0" \
+	"uget=tftp u-boot.ldr\0" \
+	"kget=tftp uImage\0" \
+	"usave=sf probe 2; " \
+		"sf erase 0 $(kernstart); " \
+		"sf write $(fileaddr) 0 $(filesize)\0" \
+	"ksave=sf probe 2; " \
+		"saveenv; " \
+		"echo Now patiently wait for the prompt...; " \
+		"sf erase $(kernstart) $(kernarea); " \
+		"sf write $(fileaddr) $(kernstart) $(filesize)\0" \
+	"sfboot=sf probe 2; " \
+		"sf read $(loadaddr) $(kernstart) $(filesize); " \
+		"run addip; bootm\0" \
+	"addip=setenv bootargs $(bootargs) " \
+	"ip=$(ipaddr):$(serverip):$(gatewayip):" \
+		"$(netmask):$(hostname):eth0:off\0"
+
+/*
+ * Soft I2C settings (BF561 does not have hard I2C)
+ * PF12,13 on SPI connector 0.
+ */
+#ifdef CONFIG_SOFT_I2C
+# define CONFIG_CMD_I2C
+# define CONFIG_SOFT_I2C_GPIO_SCL	GPIO_PF12
+# define CONFIG_SOFT_I2C_GPIO_SDA	GPIO_PF13
+# define CONFIG_SYS_I2C_SPEED		50000
+# define CONFIG_SYS_I2C_SLAVE		0xFE
+#endif
+
+/*
+ * No Parallel Flash on this board
+ */
+#define CONFIG_SYS_NO_FLASH
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_JFFS2
+#undef CONFIG_CMD_FLASH
+
+#endif
diff --git a/include/configs/cm-bf527.h b/include/configs/cm-bf527.h
index e0c6d53b2c..84c93099ce 100644
--- a/include/configs/cm-bf527.h
+++ b/include/configs/cm-bf527.h
@@ -11,7 +11,6 @@
 /*
  * Processor Settings
  */
-#define CONFIG_BFIN_CPU             bf527-0.0
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_PARA
 
 
diff --git a/include/configs/cm-bf533.h b/include/configs/cm-bf533.h
index 75152964b6..dbc4a5b100 100644
--- a/include/configs/cm-bf533.h
+++ b/include/configs/cm-bf533.h
@@ -11,7 +11,6 @@
 /*
  * Processor Settings
  */
-#define CONFIG_BFIN_CPU             bf533-0.3
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS
 
 
diff --git a/include/configs/cm-bf537e.h b/include/configs/cm-bf537e.h
index 742df9c019..df3fe48f65 100644
--- a/include/configs/cm-bf537e.h
+++ b/include/configs/cm-bf537e.h
@@ -11,7 +11,6 @@
 /*
  * Processor Settings
  */
-#define CONFIG_BFIN_CPU             bf537-0.2
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS
 
 
diff --git a/include/configs/cm-bf537u.h b/include/configs/cm-bf537u.h
index 9def99f728..e5b0ecfc5e 100644
--- a/include/configs/cm-bf537u.h
+++ b/include/configs/cm-bf537u.h
@@ -11,7 +11,6 @@
 /*
  * Processor Settings
  */
-#define CONFIG_BFIN_CPU             bf537-0.2
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS
 
 
diff --git a/include/configs/cm-bf548.h b/include/configs/cm-bf548.h
index fa62a8e9c1..27b1cc519c 100644
--- a/include/configs/cm-bf548.h
+++ b/include/configs/cm-bf548.h
@@ -11,7 +11,6 @@
 /*
  * Processor Settings
  */
-#define CONFIG_BFIN_CPU             bf548-0.0
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_PARA
 
 
diff --git a/include/configs/cm-bf561.h b/include/configs/cm-bf561.h
index c60401c8fe..8c350bc263 100644
--- a/include/configs/cm-bf561.h
+++ b/include/configs/cm-bf561.h
@@ -11,7 +11,6 @@
 /*
  * Processor Settings
  */
-#define CONFIG_BFIN_CPU             bf561-0.3
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_PARA
 
 
diff --git a/include/configs/ibf-dsp561.h b/include/configs/ibf-dsp561.h
index 53b5197112..cd856ac79c 100644
--- a/include/configs/ibf-dsp561.h
+++ b/include/configs/ibf-dsp561.h
@@ -11,7 +11,6 @@
 /*
  * Processor Settings
  */
-#define CONFIG_BFIN_CPU             bf561-0.5
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS
 
 
diff --git a/include/configs/ip04.h b/include/configs/ip04.h
index c024d78c18..528363c6b4 100644
--- a/include/configs/ip04.h
+++ b/include/configs/ip04.h
@@ -20,7 +20,6 @@
 /*
  * Processor Settings
  */
-#define CONFIG_BFIN_CPU             bf532-0.5
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_NAND
 
 
diff --git a/include/configs/tcm-bf518.h b/include/configs/tcm-bf518.h
index 52055e80dc..042d78915c 100644
--- a/include/configs/tcm-bf518.h
+++ b/include/configs/tcm-bf518.h
@@ -11,7 +11,6 @@
 /*
  * Processor Settings
  */
-#define CONFIG_BFIN_CPU             bf518-0.0
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_PARA
 
 
diff --git a/include/configs/tcm-bf537.h b/include/configs/tcm-bf537.h
index 24ce8f854a..dceff308b8 100644
--- a/include/configs/tcm-bf537.h
+++ b/include/configs/tcm-bf537.h
@@ -11,7 +11,6 @@
 /*
  * Processor Settings
  */
-#define CONFIG_BFIN_CPU             bf537-0.2
 #define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS