powerpc/ppc4xx: Use generic accessor functions for gdsys FPGA

A set of accessor functions was added to be able to access not only
memory mapped FPGA in a generic way.

Thanks to Wolfgang Denk for getting this sorted properly.

Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Signed-off-by: Stefan Roese <sr@denx.de>

6 files changed, 62 insertions, 8 deletions

diff --git a/include/configs/dlvision-10g.h b/include/configs/dlvision-10g.h
index 17391cddc9..d4011a1e8a 100644
--- a/include/configs/dlvision-10g.h
+++ b/include/configs/dlvision-10g.h
@@ -123,6 +123,12 @@
 
 #define CONFIG_SYS_FPGA_COUNT		2
 
+#define CONFIG_SYS_FPGA_PTR { \
+	(struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, \
+	(struct ihs_fpga *)CONFIG_SYS_FPGA1_BASE }
+
+#define CONFIG_SYS_FPGA_COMMON
+
 #define CONFIG_SYS_LATCH0_RESET		0xffff
 #define CONFIG_SYS_LATCH0_BOOT		0xffff
 #define CONFIG_SYS_LATCH1_RESET		0xffcf
diff --git a/include/configs/io.h b/include/configs/io.h
index 33743e61ac..27d1b0f0a1 100644
--- a/include/configs/io.h
+++ b/include/configs/io.h
@@ -230,6 +230,11 @@
 
 #define CONFIG_SYS_FPGA_COUNT		1
 
+#define CONFIG_SYS_FPGA_PTR \
+	{ (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE }
+
+#define CONFIG_SYS_FPGA_COMMON
+
 /* Memory Bank 3 (Latches) initialization */
 #define CONFIG_SYS_LATCH_BASE		0x7f200000
 #define CONFIG_SYS_EBC_PB3AP		0xa2015480
diff --git a/include/configs/io64.h b/include/configs/io64.h
index dcd1b82e25..f110b70602 100644
--- a/include/configs/io64.h
+++ b/include/configs/io64.h
@@ -498,6 +498,12 @@
 
 #define CONFIG_SYS_FPGA_COUNT		2
 
+#define CONFIG_SYS_FPGA_PTR { \
+	(struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, \
+	(struct ihs_fpga *)CONFIG_SYS_FPGA1_BASE }
+
+#define CONFIG_SYS_FPGA_COMMON
+
 #define CONFIG_SYS_LATCH0_RESET		0xffff
 #define CONFIG_SYS_LATCH0_BOOT		0xffff
 #define CONFIG_SYS_LATCH1_RESET		0xffbf
diff --git a/include/configs/iocon.h b/include/configs/iocon.h
index 32d9050adb..67a7ab9ee3 100644
--- a/include/configs/iocon.h
+++ b/include/configs/iocon.h
@@ -236,6 +236,11 @@ int fpga_gpio_get(int pin);
 
 #define CONFIG_SYS_FPGA_COUNT		1
 
+#define CONFIG_SYS_FPGA_PTR \
+	{ (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE }
+
+#define CONFIG_SYS_FPGA_COMMON
+
 /* Memory Bank 3 (Latches) initialization */
 #define CONFIG_SYS_LATCH_BASE		0x7f200000
 #define CONFIG_SYS_EBC_PB3AP		0x02025080
diff --git a/include/configs/neo.h b/include/configs/neo.h
index 5abb8b1a75..91871f718f 100644
--- a/include/configs/neo.h
+++ b/include/configs/neo.h
@@ -222,6 +222,11 @@
 
 #define CONFIG_SYS_FPGA_COUNT		1
 
+#define CONFIG_SYS_FPGA_PTR \
+	{ (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE }
+
+#define CONFIG_SYS_FPGA_COMMON
+
 /* Memory Bank 3 (Latches) initialization                      */
 #define CONFIG_SYS_LATCH_BASE		0x7f200000
 #define CONFIG_SYS_EBC_PB3AP		0x92015480
diff --git a/include/gdsys_fpga.h b/include/gdsys_fpga.h
index 0a8268cbb5..8b895457bd 100644
--- a/include/gdsys_fpga.h
+++ b/include/gdsys_fpga.h
@@ -19,6 +19,23 @@ enum {
 int get_fpga_state(unsigned dev);
 void print_fpga_state(unsigned dev);
 
+int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data);
+int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data);
+
+extern struct ihs_fpga *fpga_ptr[];
+
+#define FPGA_SET_REG(ix, fld, val) \
+	fpga_set_reg((ix), \
+		     &fpga_ptr[ix]->fld, \
+		     offsetof(struct ihs_fpga, fld), \
+		     val)
+
+#define FPGA_GET_REG(ix, fld, val) \
+	fpga_get_reg((ix), \
+		     &fpga_ptr[ix]->fld, \
+		     offsetof(struct ihs_fpga, fld), \
+		     val)
+
 struct ihs_gpio {
 	u16 read;
 	u16 clear;
@@ -67,6 +84,19 @@ struct ihs_fpga {
 #endif
 
 #ifdef CONFIG_IO64
+
+struct ihs_fpga_channel {
+	u16 status_int;
+	u16 config_int;
+	u16 switch_connect_config;
+	u16 tx_destination;
+};
+
+struct ihs_fpga_hicb {
+	u16 status_int;
+	u16 config_int;
+};
+
 struct ihs_fpga {
 	u16 reflection_low;	/* 0x0000 */
 	u16 versions;		/* 0x0002 */
@@ -75,12 +105,9 @@ struct ihs_fpga {
 	u16 reserved_0[5];	/* 0x0008 */
 	u16 quad_serdes_reset;	/* 0x0012 */
 	u16 reserved_1[502];	/* 0x0014 */
-	u16 ch0_status_int;	/* 0x0400 */
-	u16 ch0_config_int;	/* 0x0402 */
-	u16 reserved_2[126];	/* 0x0404 */
-	u16 ch0_hicb_status_int;/* 0x0500 */
-	u16 ch0_hicb_config_int;/* 0x0502 */
-	u16 reserved_3[7549];	/* 0x0504 */
+	struct ihs_fpga_channel ch[32];		/* 0x0400 */
+	struct ihs_fpga_channel hicb_ch[32];	/* 0x0500 */
+	u16 reserved_2[7487];	/* 0x0580 */
 	u16 reflection_high;	/* 0x3ffe */
 };
 #endif
@@ -100,7 +127,7 @@ struct ihs_fpga {
 	u16 reflection_high;	/* 0x00fe */
 	struct ihs_osd osd;	/* 0x0100 */
 	u16 reserved_3[889];	/* 0x010e */
-	u16 videomem;		/* 0x0800 */
+	u16 videomem[31736];	/* 0x0800 */
 };
 #endif
 
@@ -121,7 +148,7 @@ struct ihs_fpga {
 	u16 reserved_4[176];	/* 0x00a0 */
 	struct ihs_osd osd;	/* 0x0200 */
 	u16 reserved_5[761];	/* 0x020e */
-	u16 videomem;		/* 0x0800 */
+	u16 videomem[31736];	/* 0x0800 */
 };
 #endif