ColdFire: Add M5253EVBE platform for MCF52x2

Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>

4 files changed, 405 insertions, 1 deletions

diff --git a/include/asm-m68k/immap.h b/include/asm-m68k/immap.h
index 3ee7071f39..bf7b51becf 100644
--- a/include/asm-m68k/immap.h
+++ b/include/asm-m68k/immap.h
@@ -43,11 +43,34 @@
 #define CFG_TMRINTR_NO		(31)
 #define CFG_TMRINTR_MASK	(0x00000400)
 #define CFG_TMRINTR_PEND	(CFG_TMRINTR_MASK)
-#define CFG_TMRINTR_PRI		(0)		/* Level must include inorder to work */
+#define CFG_TMRINTR_PRI		(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3)
 #define CFG_TIMER_PRESCALER	(((gd->bus_clk / 2000000) - 1) << 8)
 #endif
 #endif				/* CONFIG_M5249 */
 
+#ifdef CONFIG_M5253
+#include <asm/immap_5253.h>
+#include <asm/m5249.h>
+#include <asm/m5253.h>
+
+#define CFG_UART_BASE		(MMAP_UART0 + (CFG_UART_PORT * 0x40))
+
+#define CFG_INTR_BASE		(MMAP_INTC)
+#define CFG_NUM_IRQS		(64)
+
+/* Timer */
+#ifdef CONFIG_MCFTMR
+#define CFG_UDELAY_BASE		(MMAP_DTMR0)
+#define CFG_TMR_BASE		(MMAP_DTMR1)
+#define CFG_TMRPND_REG		(mbar_readLong(MCFSIM_IPR))
+#define CFG_TMRINTR_NO		(27)
+#define CFG_TMRINTR_MASK	(0x00000400)
+#define CFG_TMRINTR_PEND	(CFG_TMRINTR_MASK)
+#define CFG_TMRINTR_PRI		(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL3 | MCFSIM_ICR_PRI3)
+#define CFG_TIMER_PRESCALER	(((gd->bus_clk / 2000000) - 1) << 8)
+#endif
+#endif				/* CONFIG_M5253 */
+
 #ifdef CONFIG_M5271
 #include <asm/immap_5271.h>
 #include <asm/m5271.h>
diff --git a/include/asm-m68k/immap_5253.h b/include/asm-m68k/immap_5253.h
new file mode 100644
index 0000000000..aafbdd0957
--- /dev/null
+++ b/include/asm-m68k/immap_5253.h
@@ -0,0 +1,95 @@
+/*
+ * MCF5253 Internal Memory Map
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __IMMAP_5249__
+#define __IMMAP_5249__
+
+#define MMAP_INTC		(CFG_MBAR + 0x00000040)
+#define MMAP_DTMR0		(CFG_MBAR + 0x00000140)
+#define MMAP_DTMR1		(CFG_MBAR + 0x00000180)
+#define MMAP_UART0		(CFG_MBAR + 0x000001C0)
+#define MMAP_UART1		(CFG_MBAR + 0x00000200)
+#define MMAP_I2C0		(CFG_MBAR + 0x00000280)
+#define MMAP_QSPI		(CFG_MBAR + 0x00000400)
+#define MMAP_CAN0		(CFG_MBAR + 0x00010000)
+#define MMAP_CAN1		(CFG_MBAR + 0x00011000)
+
+#define MMAP_I2C1		(CFG_MBAR2 + 0x00000440)
+#define MMAP_UART2		(CFG_MBAR2 + 0x00000C00)
+
+/*********************************************************************
+* ATA Module (ATAC)
+*********************************************************************/
+
+/* Register read/write struct */
+typedef struct atac {
+	/* PIO */
+	u8 toff;		/* 0x00 */
+	u8 ton;			/* 0x01 */
+	u8 t1;			/* 0x02 */
+	u8 t2w;			/* 0x03 */
+	u8 t2r;			/* 0x04 */
+	u8 ta;			/* 0x05 */
+	u8 trd;			/* 0x06 */
+	u8 t4;			/* 0x07 */
+	u8 t9;			/* 0x08 */
+
+	/* DMA */
+	u8 tm;			/* 0x09 */
+	u8 tn;			/* 0x0A */
+	u8 td;			/* 0x0B */
+	u8 tk;			/* 0x0C */
+	u8 tack;		/* 0x0D */
+	u8 tenv;		/* 0x0E */
+	u8 trp;			/* 0x0F */
+	u8 tzah;		/* 0x10 */
+	u8 tmli;		/* 0x11 */
+	u8 tdvh;		/* 0x12 */
+	u8 tdzfs;		/* 0x13 */
+	u8 tdvs;		/* 0x14 */
+	u8 tcvh;		/* 0x15 */
+	u8 tss;			/* 0x16 */
+	u8 tcyc;		/* 0x17 */
+
+	/* FIFO */
+	u32 fifo32;		/* 0x18 */
+	u16 fifo16;		/* 0x1C */
+	u8 rsvd0[2];
+	u8 ffill;		/* 0x20 */
+	u8 rsvd1[3];
+
+	/* ATA */
+	u8 cr;			/* 0x24 */
+	u8 rsvd2[3];
+	u8 isr;			/* 0x28 */
+	u8 rsvd3[3];
+	u8 ier;			/* 0x2C */
+	u8 rsvd4[3];
+	u8 icr;			/* 0x30 */
+	u8 rsvd5[3];
+	u8 falarm;		/* 0x34 */
+} atac_t;
+
+#endif				/* __IMMAP_5249__ */
diff --git a/include/asm-m68k/m5253.h b/include/asm-m68k/m5253.h
new file mode 100644
index 0000000000..eda3472738
--- /dev/null
+++ b/include/asm-m68k/m5253.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef m5253_h
+#define m5253_h
+/****************************************************************************/
+
+/*
+* PLL Module (PLL)
+*/
+
+/* Register read/write macros */
+#define PLL_PLLCR		(0x000180)
+
+#define SIM_RSR			(0x000000)
+#define SIM_SYPCR		(0x000001)
+#define SIM_SWIVR		(0x000002)
+#define SIM_SWSR		(0x000003)
+#define SIM_MPARK		(0x00000C)
+
+/* Bit definitions and macros for RSR */
+#define SIM_RSR_SWTR		(0x20)
+#define SIM_RSR_HRST		(0x80)
+
+/* Register read/write macros */
+#define CIM_MISCCR		(0x000500)
+#define CIM_ATA_DADDR		(0x000504)
+#define CIM_ATA_DCOUNT		(0x000508)
+#define CIM_RTC_TIME		(0x00050C)
+#define CIM_USB_CANCLK		(0x000510)
+
+/* Bit definitions and macros for MISCCR */
+#define CIM_MISCCR_ADTA		(0x00000001)
+#define CIM_MISCCR_ADTD		(0x00000002)
+#define CIM_MISCCR_ADIE		(0x00000004)
+#define CIM_MISCCR_ADIC		(0x00000008)
+#define CIM_MISCCR_ADIP		(0x00000010)
+#define CIM_MISCCR_CPUEND	(0x00000020)
+#define CIM_MISCCR_DMAEND	(0x00000040)
+#define CIM_MISCCR_RTCCLR	(0x00000080)
+#define CIM_MISCCR_RTCPL	(0x00000100)
+#define CIM_MISCCR_URIE		(0x00000800)
+#define CIM_MISCCR_URIC		(0x00001000)
+#define CIM_MISCCR_URIP		(0x00002000)
+
+/* Bit definitions and macros for ATA_DADDR */
+#define CIM_ATA_DADDR_ATAADDR(x)	(((x)&0x00003FFF)<<2)
+#define CIM_ATA_DADDR_RAMADDR(x)	(((x)&0x00003FFF)<<18)
+
+/* Bit definitions and macros for ATA_DCOUNT */
+#define CIM_ATA_DCOUNT_COUNT(x)		(((x)&0x0000FFFF))
+
+#endif				/* m5253_h */
diff --git a/include/configs/M5253EVBE.h b/include/configs/M5253EVBE.h
new file mode 100644
index 0000000000..9ad74e2bc6
--- /dev/null
+++ b/include/configs/M5253EVBE.h
@@ -0,0 +1,213 @@
+/*
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Hayden Fraser (Hayden.Fraser@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _M5253EVBE_H
+#define _M5253EVBE_H
+
+#define CONFIG_MCF52x2		/* define processor family */
+#define CONFIG_M5253		/* define processor type */
+#define CONFIG_M5253EVBE	/* define board type */
+
+#define CONFIG_MCFTMR
+
+#define CONFIG_MCFUART
+#define CFG_UART_PORT		(0)
+#define CONFIG_BAUDRATE		19200
+#define CFG_BAUDRATE_TABLE	{ 9600 , 19200 , 38400 , 57600, 115200 }
+
+#undef CONFIG_WATCHDOG		/* disable watchdog */
+
+#define CONFIG_BOOTDELAY	5
+
+/* Configuration for environment
+ * Environment is embedded in u-boot in the second sector of the flash
+ */
+#ifndef CONFIG_MONITOR_IS_IN_RAM
+#define CFG_ENV_OFFSET		0x4000
+#define CFG_ENV_SECT_SIZE	0x2000
+#define CFG_ENV_IS_IN_FLASH	1
+#else
+#define CFG_ENV_ADDR		0xffe04000
+#define CFG_ENV_SECT_SIZE	0x2000
+#define CFG_ENV_IS_IN_FLASH	1
+#endif
+
+/*
+ * BOOTP options
+ */
+#undef CONFIG_BOOTP_BOOTFILESIZE
+#undef CONFIG_BOOTP_BOOTPATH
+#undef CONFIG_BOOTP_GATEWAY
+#undef CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_NET
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
+
+/* ATA */
+#define CONFIG_DOS_PARTITION
+#define CONFIG_MAC_PARTITION
+#define CONFIG_IDE_RESET	1
+#define CONFIG_IDE_PREINIT	1
+#define CONFIG_ATAPI
+#undef CONFIG_LBA48
+
+#define CFG_IDE_MAXBUS		1
+#define CFG_IDE_MAXDEVICE	2
+
+#define CFG_ATA_BASE_ADDR	(CFG_MBAR2 + 0x800)
+#define CFG_ATA_IDE0_OFFSET	0
+
+#define CFG_ATA_DATA_OFFSET	0xA0	/* Offset for data I/O */
+#define CFG_ATA_REG_OFFSET	0xA0	/* Offset for normal register accesses */
+#define CFG_ATA_ALT_OFFSET	0xC0	/* Offset for alternate registers */
+#define CFG_ATA_STRIDE		4	/* Interval between registers */
+#define _IO_BASE		0
+
+#define CFG_PROMPT		"=> "
+#define CFG_LONGHELP		/* undef to save memory */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CFG_CBSIZE		1024	/* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE		256	/* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
+#define CFG_MAXARGS		16	/* max number of command args */
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size */
+
+#define CFG_LOAD_ADDR		0x00100000
+
+#define CFG_MEMTEST_START	0x400
+#define CFG_MEMTEST_END		0x380000
+
+#define CFG_HZ			1000
+
+#undef CFG_PLL_BYPASS		/* bypass PLL for test purpose */
+#define CFG_FAST_CLK
+#ifdef CFG_FAST_CLK
+#	define CFG_PLLCR	0x1243E054
+#	define CFG_CLK		140000000
+#else
+#	define CFG_PLLCR	0x135a4140
+#	define CFG_CLK		70000000
+#endif
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+#define CFG_MBAR		0x10000000	/* Register Base Addrs */
+#define CFG_MBAR2		0x80000000	/* Module Base Addrs 2 */
+
+/*
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	0x20000000
+#define CFG_INIT_RAM_END	0x10000	/* End of used area in internal SRAM */
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_SDRAM_SIZE		16	/* SDRAM size in MB */
+
+#ifdef CONFIG_MONITOR_IS_IN_RAM
+#define CFG_MONITOR_BASE	0x20000
+#else
+#define CFG_MONITOR_BASE	(CFG_FLASH_BASE + 0x400)
+#endif
+
+#define CFG_MONITOR_LEN		0x40000
+#define CFG_MALLOC_LEN		(256 << 10)
+#define CFG_BOOTPARAMS_LEN	(64*1024)
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+#define CFG_BOOTMAPSZ		(CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
+
+/* FLASH organization */
+#define CFG_FLASH_BASE		0xffe00000
+#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
+#define CFG_MAX_FLASH_SECT	35	/* max number of sectors on one chip */
+#define CFG_FLASH_ERASE_TOUT	1000
+
+#define CFG_FLASH_CFI		1
+#define CFG_FLASH_CFI_DRIVER	1
+#define CFG_FLASH_SIZE		0x200000
+#define CFG_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+
+/* Cache Configuration */
+#define CFG_CACHELINE_SIZE	16
+
+/* Port configuration */
+#define CFG_FECI2C		0xF0
+
+#define CFG_CSAR0		0xFFE0
+#define CFG_CSMR0		0x001F0021
+#define CFG_CSCR0		0x1D80
+
+#define CFG_CSAR1		0
+#define CFG_CSMR1		0
+#define CFG_CSCR1		0
+
+#define CFG_CSAR2		0
+#define CFG_CSMR2		0
+#define CFG_CSCR2		0
+
+#define CFG_CSAR3		0
+#define CFG_CSMR3		0
+#define CFG_CSCR3		0
+
+/*-----------------------------------------------------------------------
+ * Port configuration
+ */
+#define CFG_GPIO_FUNC		0x00000008	/* Set gpio pins: none */
+#define CFG_GPIO1_FUNC		0x00df00f0	/* 36-39(SWITCH),48-52(FPGAs),54 */
+#define CFG_GPIO_EN		0x00000008	/* Set gpio output enable */
+#define CFG_GPIO1_EN		0x00c70000	/* Set gpio output enable */
+#define CFG_GPIO_OUT		0x00000008	/* Set outputs to default state */
+#define CFG_GPIO1_OUT		0x00c70000	/* Set outputs to default state */
+#define CFG_GPIO1_LED		0x00400000	/* user led */
+
+#endif				/* _M5253EVB_H */
+