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authorwdenk <wdenk>2004-03-14 18:23:55 +0000
committerwdenk <wdenk>2004-03-14 18:23:55 +0000
commit855a496fe9ba431772f1ff1aef21a5c001288bb0 (patch)
tree67ce44a0170787acf0da735beba5c5a0a7959398 /include/miiphy.h
parent4b248f3f71dc867b0b636b137b044cc762b68486 (diff)
downloadblackbird-obmc-uboot-855a496fe9ba431772f1ff1aef21a5c001288bb0.tar.gz
blackbird-obmc-uboot-855a496fe9ba431772f1ff1aef21a5c001288bb0.zip
* Patches by Travis Sawyer, 12 Mar 2004:
- Fix Gigabit Ethernet support for 440GX - Add Gigabit Ethernet Support to MII PHY utilities * Patch by Brad Kemp, 12 Mar 2004: Fixes for drivers/cfi_flash.c: - Better support for x8/x16 implementations - Added failure for AMD chips attempting to use CFG_FLASH_USE_BUFFER_WRITE - Added defines for AMD command and address constants * Patch by Leon Kukovec, 12 Mar 2004: Fix get_dentfromdir() to correctly handle deleted dentries * Patch by George G. Davis, 11 Mar 2004: Remove hard coded network settings in TI OMAP1610 H2 default board config * Patch by George G. Davis, 11 Mar 2004: add support for ADS GraphicsClient+ board.
Diffstat (limited to 'include/miiphy.h')
-rw-r--r--include/miiphy.h13
1 files changed, 13 insertions, 0 deletions
diff --git a/include/miiphy.h b/include/miiphy.h
index 672baf9f40..7f61cfa4e3 100644
--- a/include/miiphy.h
+++ b/include/miiphy.h
@@ -53,6 +53,7 @@ int miiphy_link(unsigned char addr);
/* phy seed setup */
#define AUTO 99
+#define _1000BASET 1000
#define _100BASET 100
#define _10BASET 10
#define HALF 22
@@ -67,6 +68,9 @@ int miiphy_link(unsigned char addr);
#define PHY_ANLPAR 0x05
#define PHY_ANER 0x06
#define PHY_ANNPTR 0x07
+#define PHY_ANLPNP 0x08
+#define PHY_1000BTCR 0x09
+#define PHY_1000BTSR 0x0A
#define PHY_PHYSTS 0x10
#define PHY_MIPSCR 0x11
#define PHY_MIPGSR 0x12
@@ -113,4 +117,13 @@ int miiphy_link(unsigned char addr);
#define PHY_ANLPAR_10FD 0x0040
#define PHY_ANLPAR_10 0x0020
#define PHY_ANLPAR_100 0x0380 /* we can run at 100 */
+
+/* PHY_1000BTSR */
+#define PHY_1000BTSR_MSCF 0x8000
+#define PHY_1000BTSR_MSCR 0x4000
+#define PHY_1000BTSR_LRS 0x2000
+#define PHY_1000BTSR_RRS 0x1000
+#define PHY_1000BTSR_1000FD 0x0800
+#define PHY_1000BTSR_1000HD 0x0400
+
#endif
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