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| author | Peng Fan <Peng.Fan@freescale.com> | 2015-11-30 17:45:02 +0800 |
|---|---|---|
| committer | Jagan Teki <jteki@openedev.com> | 2015-12-11 22:12:23 +0530 |
| commit | 53cc647dc63085438510ee3d65de399c92ca3cac (patch) | |
| tree | 2e2f742afbf99c46ad2a60cd387034ed64c3b71b /include/configs/mx7dsabresd.h | |
| parent | cd337da21ecea0f34335d3b2d33bcd28d9e3d0d0 (diff) | |
| download | blackbird-obmc-uboot-53cc647dc63085438510ee3d65de399c92ca3cac.tar.gz blackbird-obmc-uboot-53cc647dc63085438510ee3d65de399c92ca3cac.zip | |
imx: mx7dsabresd: Add QSPI support
Support qspi flashes for mx7dsabresd
1. introduce pin mux settings
2. enable qspi clock
3. introduce related macro definitions
Default QSPI is not enabled, since we need hardware rework to use QSPI,
see SPF-28590, page 9:
"
QSPI signals are muxed with EPDC_D[7:0]
When using QSPI: de-populate R388-R391, R396-R399
populate R392-R395, R299, R300
"
After hardware rework, define CONFIG_FSL_QSPI in mx7dsabresd.h. qspi
flashes can be deteced and read/erase/write. Log info:
"
=> sf probe
SF: Detected MX25L51235F with page size 256 Bytes, erase size 64 KiB, total 64 MiB
=> sf read 0x80000000 0 0x4000000
device 0 whole chip
SF: 67108864 bytes @ 0x0 Read: OK
=> sf erase 0 0x4000000
SF: 67108864 bytes @ 0x0 Erased: OK
=> sf write 0x80000000 0 0x4000000
device 0 whole chip
SF: 67108864 bytes @ 0x0 Written: OK
"
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Adrian Alonso <aalonso@freescale.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Diffstat (limited to 'include/configs/mx7dsabresd.h')
| -rw-r--r-- | include/configs/mx7dsabresd.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h index cc98547461..22e515cccd 100644 --- a/include/configs/mx7dsabresd.h +++ b/include/configs/mx7dsabresd.h @@ -236,4 +236,19 @@ #define CONFIG_VIDEO_BMP_LOGO #endif +#ifdef CONFIG_FSL_QSPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_MACRONIX +#define CONFIG_SPI_FLASH_BAR +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 40000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define FSL_QSPI_FLASH_NUM 1 +#define FSL_QSPI_FLASH_SIZE SZ_64M +#define QSPI0_BASE_ADDR QSPI1_IPS_BASE_ADDR +#define QSPI0_AMBA_BASE QSPI0_ARB_BASE_ADDR +#endif + #endif /* __CONFIG_H */ |
