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authorValentin Longchamp <valentin.longchamp@keymile.com>2014-04-30 15:01:44 +0200
committerYork Sun <yorksun@freescale.com>2014-05-13 08:26:55 -0700
commit18794944c6f60b912db8509012d10793f35586ae (patch)
tree7a630dabc61ddc53b10ba0d9b08bd96da3324d13 /include/configs/km
parent4921a149e1470d92e2982e13c709357d90ef5e6c (diff)
downloadblackbird-obmc-uboot-18794944c6f60b912db8509012d10793f35586ae.tar.gz
blackbird-obmc-uboot-18794944c6f60b912db8509012d10793f35586ae.zip
kmp204x: selftest/factory test pin support
This patch defines the post_hotkeys_pressed() function that is used for: - triggering POST memory regions test - starting the test application through the checktestboot command in a script by setting the active bank to testbank The post_hotkeys_pressed return the state of the SELFTEST pin. The patch moves from the complete POST-memory test that is too long in its SLOW version for our production HW test procedure to the much shorter POST-memory-regions test. Finally, the unused #defines for the not so relevant mtest command are removed. Signed-off-by: Stefan Bigler <stefan.bigler@keymile.com> Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Diffstat (limited to 'include/configs/km')
-rw-r--r--include/configs/km/kmp204x-common.h6
1 files changed, 1 insertions, 5 deletions
diff --git a/include/configs/km/kmp204x-common.h b/include/configs/km/kmp204x-common.h
index 418e3d1298..f9bcef3ff1 100644
--- a/include/configs/km/kmp204x-common.h
+++ b/include/configs/km/kmp204x-common.h
@@ -85,11 +85,7 @@ unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_ADDR_MAP
#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
-#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00800000
-#define CONFIG_SYS_ALT_MEMTEST
-#define CONFIG_PANIC_HANG /* do not reset board on panic */
+#define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS /* POST memory regions test */
/*
* Config the L3 Cache as L3 SRAM
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