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| author | Wolfgang Denk <wd@denx.de> | 2009-10-27 20:56:31 +0100 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2009-10-27 20:56:31 +0100 |
| commit | 98cecb610f3fa53aa7d825a634d35ef9cf6c5487 (patch) | |
| tree | f9a153be5ec31919981e4d53e5ee274cffa3d15b /include/configs/XPEDITE5370.h | |
| parent | a747a7f31059b9069e97c78bba5496409c33aa05 (diff) | |
| parent | 3fca80375981fe83d4674a0267183b469a1ea7ff (diff) | |
| download | blackbird-obmc-uboot-98cecb610f3fa53aa7d825a634d35ef9cf6c5487.tar.gz blackbird-obmc-uboot-98cecb610f3fa53aa7d825a634d35ef9cf6c5487.zip | |
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Diffstat (limited to 'include/configs/XPEDITE5370.h')
| -rw-r--r-- | include/configs/XPEDITE5370.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/include/configs/XPEDITE5370.h b/include/configs/XPEDITE5370.h index 26b798b4d8..7782df3678 100644 --- a/include/configs/XPEDITE5370.h +++ b/include/configs/XPEDITE5370.h @@ -49,6 +49,13 @@ #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ /* + * Multicore config + */ +#define CONFIG_MP +#define CONFIG_BPTR_VIRT_ADDR 0xee000000 /* virt boot page address */ +#define CONFIG_MPC8xxx_DISABLE_BPTR /* Don't leave BPTR enabled */ + +/* * DDR config */ #define CONFIG_FSL_DDR2 @@ -109,6 +116,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable * 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable + * 0xee00_0000 0xee00_ffff Boot page translation 4K non-cacheable * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable |
