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| author | Heiko Schocher <hs@denx.de> | 2013-01-29 08:53:15 +0100 |
|---|---|---|
| committer | Heiko Schocher <hs@denx.de> | 2013-07-23 05:54:29 +0200 |
| commit | ea818dbbcd59300b56014ac2d67798a54994eb9b (patch) | |
| tree | fbdedc80f785873f96e79893a1a813504af57580 /include/configs/TASREG.h | |
| parent | 3f4978c713255c8406875fbdf23ffed1129bc44b (diff) | |
| download | blackbird-obmc-uboot-ea818dbbcd59300b56014ac2d67798a54994eb9b.tar.gz blackbird-obmc-uboot-ea818dbbcd59300b56014ac2d67798a54994eb9b.zip | |
i2c, soft-i2c: switch to new multibus/multiadapter support
- added to soft_i2c driver new multibus/multiadpater support
- adapted all config files, which uses this driver
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Diffstat (limited to 'include/configs/TASREG.h')
| -rw-r--r-- | include/configs/TASREG.h | 28 |
1 files changed, 15 insertions, 13 deletions
diff --git a/include/configs/TASREG.h b/include/configs/TASREG.h index d95a22611d..059fb362f8 100644 --- a/include/configs/TASREG.h +++ b/include/configs/TASREG.h @@ -136,19 +136,11 @@ /*----------------------------------------------------------------------- * I2C */ -#define CONFIG_SOFT_I2C -#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC32 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */ - /* 32 byte page write mode using*/ - /* last 5 bits of the address */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ +#define CONFIG_SYS_I2C_SOFT_SPEED 100000 +#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F -#if defined (CONFIG_SOFT_I2C) #if 0 /* push-pull */ #define SDA 0x00800000 #define SCL 0x00000008 @@ -182,7 +174,17 @@ #define I2C_ACTIVE {DIR1|=SDA;} #define I2C_TRISTATE {DIR1&=~SDA;} #endif -#endif + +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC32 */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ +/* mask of address bits that overflow into the "EEPROM chip address" */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01 +/* + * The Catalyst CAT24WC32 has 32 byte page write mode using + * last 5 bits of the address + */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in DPRAM) |
