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| author | André Schwarz <andre.schwarz@matrix-vision.de> | 2009-08-27 14:48:35 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2009-08-28 00:31:23 +0200 |
| commit | 28887d831b02c66ccc10d7f1379204b5a62f4543 (patch) | |
| tree | c2a5d544587f0535b3de9ba742292195ae63ab7f /include/configs/MVBLM7.h | |
| parent | 05f91a65abc3180e2896cd8ddee7a34b1d1ce6e0 (diff) | |
| download | blackbird-obmc-uboot-28887d831b02c66ccc10d7f1379204b5a62f4543.tar.gz blackbird-obmc-uboot-28887d831b02c66ccc10d7f1379204b5a62f4543.zip | |
Use common code for Matrix Vision boards
Clean up existing boards (mvBC-P/MPC5200 and mvBL-M7/MPC8343) by
using common code.
Signed-off-by: André Schwarz <andre.schwarz@matrix-vision.de>
Diffstat (limited to 'include/configs/MVBLM7.h')
| -rw-r--r-- | include/configs/MVBLM7.h | 49 |
1 files changed, 20 insertions, 29 deletions
diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h index aa91805e1c..80334bd607 100644 --- a/include/configs/MVBLM7.h +++ b/include/configs/MVBLM7.h @@ -46,10 +46,9 @@ #define CONFIG_MPC8XXX_SPI #define CONFIG_HARD_SPI #define MVBLM7_MMC_CS 0x04000000 +#define CONFIG_MISC_INIT_R /* I2C */ -#undef CONFIG_SOFT_I2C - #define CONFIG_FSL_I2C #define CONFIG_I2C_MULTI_BUS #define CONFIG_SYS_I2C_OFFSET 0x3000 @@ -61,44 +60,36 @@ /* * DDR Setup */ +#undef CONFIG_SPD_EEPROM + #define CONFIG_SYS_DDR_BASE 0x00000000 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE #define CONFIG_SYS_83XX_DDR_USES_CS0 1 #define CONFIG_SYS_MEMTEST_START (60<<20) #define CONFIG_SYS_MEMTEST_END (70<<20) +#define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ - DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 - -#define CONFIG_SYS_DDR_SIZE 256 +#define CONFIG_SYS_DDRCDR 0x22000001 +#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 -/* HC, 75Ohm, DDR-II, DRQ */ -#define CONFIG_SYS_DDRCDR 0x80000001 -/* EN, ODT_WR, 3BA, 14row, 10col */ -#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014102 -#define CONFIG_SYS_DDR_CS1_CONFIG 0x0 -#define CONFIG_SYS_DDR_CS2_CONFIG 0x0 -#define CONFIG_SYS_DDR_CS3_CONFIG 0x0 +#define CONFIG_SYS_DDR_SIZE 512 -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f -#define CONFIG_SYS_DDR_CS1_BNDS 0x0 -#define CONFIG_SYS_DDR_CS2_BNDS 0x0 -#define CONFIG_SYS_DDR_CS3_BNDS 0x0 +#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 -#define CONFIG_SYS_DDR_CLK_CNTL 0x02000000 +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f -#define CONFIG_SYS_DDR_TIMING_0 0x00260802 -#define CONFIG_SYS_DDR_TIMING_1 0x2625b221 -#define CONFIG_SYS_DDR_TIMING_2 0x1f9820c7 -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 +#define CONFIG_SYS_DDR_TIMING_0 0x00260802 +#define CONFIG_SYS_DDR_TIMING_1 0x3837c322 +#define CONFIG_SYS_DDR_TIMING_2 0x0f9848c6 +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 -/* ~MEM_EN, SREN, DDR-II, 32_BE */ -#define CONFIG_SYS_DDR_SDRAM_CFG 0x43080000 +#define CONFIG_SYS_DDR_SDRAM_CFG 0x43080008 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 -#define CONFIG_SYS_DDR_INTERVAL 0x04060100 +#define CONFIG_SYS_DDR_INTERVAL 0x02000100 -#define CONFIG_SYS_DDR_MODE 0x078e0232 +#define CONFIG_SYS_DDR_MODE 0x04040242 +#define CONFIG_SYS_DDR_MODE2 0x00800000 /* Flash */ #define CONFIG_SYS_FLASH_CFI @@ -404,8 +395,8 @@ #define MV_CI mvBL-M7 #define MV_VCI mvBL-M7 -#define MV_FPGA_DATA 0xfff80000 -#define MV_FPGA_SIZE 0x00076ca2 +#define MV_FPGA_DATA 0xfff40000 +#define MV_FPGA_SIZE 0 #define MV_KERNEL_ADDR 0xff810000 #define MV_INITRD_ADDR 0xffb00000 #define MV_SOURCE_ADDR 0xff804000 @@ -452,7 +443,7 @@ "static_ipaddr=192.168.90.10\0" \ "static_netmask=255.255.255.0\0" \ "static_gateway=0.0.0.0\0" \ - "initrd_name=uInitrd.mvblm7-xenorfs\0" \ + "initrd_name=uInitrd.mvBL-M7-rfs\0" \ "zcip=no\0" \ "netboot=yes\0" \ "mvtest=Ff\0" \ |
