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| author | stroese <stroese> | 2004-12-16 18:05:42 +0000 |
|---|---|---|
| committer | stroese <stroese> | 2004-12-16 18:05:42 +0000 |
| commit | a20b27a36b7b1f593e18b4efd506e5f01a392dc6 (patch) | |
| tree | f9dc45c287966bb96c38a8267d07b217727efb3c /include/configs/ASH405.h | |
| parent | 44acc8d334a8b9ddb81fc238b094574991f19afa (diff) | |
| download | blackbird-obmc-uboot-a20b27a36b7b1f593e18b4efd506e5f01a392dc6.tar.gz blackbird-obmc-uboot-a20b27a36b7b1f593e18b4efd506e5f01a392dc6.zip | |
esd config files updated
Diffstat (limited to 'include/configs/ASH405.h')
| -rw-r--r-- | include/configs/ASH405.h | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/include/configs/ASH405.h b/include/configs/ASH405.h index 7ed01d16de..8e3f34f98c 100644 --- a/include/configs/ASH405.h +++ b/include/configs/ASH405.h @@ -40,27 +40,24 @@ #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ -#define CONFIG_SYS_CLK_FREQ 33333334 /* external frequency to pll */ +#define CONFIG_SYS_CLK_FREQ 33333300 /* external frequency to pll */ #define CONFIG_BAUDRATE 9600 #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ #undef CONFIG_BOOTARGS -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw nfsroot=$(serverip):$(rootpath) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \ - "bootm ffc00000 ffca0000" -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \ - "bootm ffc00000" -#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND +#undef CONFIG_BOOTCOMMAND + +#define CONFIG_PREBOOT /* enable preboot variable */ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address */ +#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ + +#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ CFG_CMD_DHCP | \ @@ -164,6 +161,9 @@ #define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) #define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) +#define CONFIG_MTD_NAND_VERIFY_WRITE 1 /* verify all writes!!! */ +#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ + /*----------------------------------------------------------------------- * PCI stuff *----------------------------------------------------------------------- |
