ColdFire: Add M5373EVB platform support - 2

Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
Signed-off by: John Rigby <jrigby@freescale.com>

3 files changed, 77 insertions, 21 deletions

diff --git a/include/asm-m68k/immap.h b/include/asm-m68k/immap.h
index 912753d220..852d94158d 100644
--- a/include/asm-m68k/immap.h
+++ b/include/asm-m68k/immap.h
@@ -169,7 +169,7 @@
 #endif
 #endif				/* CONFIG_M5282 */
 
-#ifdef CONFIG_M5329
+#if defined(CONFIG_M5329) || defined(CONFIG_M5373)
 #include <asm/immap_5329.h>
 #include <asm/m5329.h>
 
@@ -197,7 +197,7 @@
 
 #define CFG_INTR_BASE		(MMAP_INTC0)
 #define CFG_NUM_IRQS		(128)
-#endif				/* CONFIG_M5329 */
+#endif				/* CONFIG_M5329 && CONFIG_M5373 */
 
 #ifdef CONFIG_M54455
 #include <asm/immap_5445x.h>
diff --git a/include/asm-m68k/immap_5329.h b/include/asm-m68k/immap_5329.h
index 7ff0b9317b..7678406e51 100644
--- a/include/asm-m68k/immap_5329.h
+++ b/include/asm-m68k/immap_5329.h
@@ -378,91 +378,133 @@ typedef struct rcm {
 /* GPIO port registers */
 typedef struct gpio_ctrl {
 	/* Port Output Data Registers */
+#ifdef CONFIG_M5329
 	u8 podr_fech;		/* 0x00 */
 	u8 podr_fecl;		/* 0x01 */
+#else
+	u16 res00;		/* 0x00 - 0x01 */
+#endif
 	u8 podr_ssi;		/* 0x02 */
 	u8 podr_busctl;		/* 0x03 */
 	u8 podr_be;		/* 0x04 */
 	u8 podr_cs;		/* 0x05 */
 	u8 podr_pwm;		/* 0x06 */
 	u8 podr_feci2c;		/* 0x07 */
-	u8 res1;		/* 0x08 */
+	u8 res08;		/* 0x08 */
 	u8 podr_uart;		/* 0x09 */
 	u8 podr_qspi;		/* 0x0A */
 	u8 podr_timer;		/* 0x0B */
-	u8 res2;		/* 0x0C */
+#ifdef CONFIG_M5329
+	u8 res0C;		/* 0x0C */
 	u8 podr_lcddatah;	/* 0x0D */
 	u8 podr_lcddatam;	/* 0x0E */
 	u8 podr_lcddatal;	/* 0x0F */
 	u8 podr_lcdctlh;	/* 0x10 */
 	u8 podr_lcdctll;	/* 0x11 */
+#else
+	u16 res0C;		/* 0x0C - 0x0D */
+	u8 podr_fech;		/* 0x0E */
+	u8 podr_fecl;		/* 0x0F */
+	u16 res10[3];		/* 0x10 - 0x15 */
+#endif
 
 	/* Port Data Direction Registers */
-	u16 res3;		/* 0x12 - 0x13 */
+#ifdef CONFIG_M5329
+	u16 res12;		/* 0x12 - 0x13 */
 	u8 pddr_fech;		/* 0x14 */
 	u8 pddr_fecl;		/* 0x15 */
+#endif
 	u8 pddr_ssi;		/* 0x16 */
 	u8 pddr_busctl;		/* 0x17 */
 	u8 pddr_be;		/* 0x18 */
 	u8 pddr_cs;		/* 0x19 */
 	u8 pddr_pwm;		/* 0x1A */
 	u8 pddr_feci2c;		/* 0x1B */
-	u8 res4;		/* 0x1C */
+	u8 res1C;		/* 0x1C */
 	u8 pddr_uart;		/* 0x1D */
 	u8 pddr_qspi;		/* 0x1E */
 	u8 pddr_timer;		/* 0x1F */
-	u8 res5;		/* 0x20 */
+#ifdef CONFIG_M5329
+	u8 res20;		/* 0x20 */
 	u8 pddr_lcddatah;	/* 0x21 */
 	u8 pddr_lcddatam;	/* 0x22 */
 	u8 pddr_lcddatal;	/* 0x23 */
 	u8 pddr_lcdctlh;	/* 0x24 */
 	u8 pddr_lcdctll;	/* 0x25 */
-	u16 res6;		/* 0x26 - 0x27 */
+	u16 res26;		/* 0x26 - 0x27 */
+#else
+	u16 res20;		/* 0x20 - 0x21 */
+	u8 pddr_fech;		/* 0x22 */
+	u8 pddr_fecl;		/* 0x23 */
+	u16 res24[3];		/* 0x24 - 0x29 */
+#endif
 
 	/* Port Data Direction Registers */
+#ifdef CONFIG_M5329
 	u8 ppd_fech;		/* 0x28 */
 	u8 ppd_fecl;		/* 0x29 */
+#endif
 	u8 ppd_ssi;		/* 0x2A */
 	u8 ppd_busctl;		/* 0x2B */
 	u8 ppd_be;		/* 0x2C */
 	u8 ppd_cs;		/* 0x2D */
 	u8 ppd_pwm;		/* 0x2E */
 	u8 ppd_feci2c;		/* 0x2F */
-	u8 res7;		/* 0x30 */
+	u8 res30;		/* 0x30 */
 	u8 ppd_uart;		/* 0x31 */
 	u8 ppd_qspi;		/* 0x32 */
 	u8 ppd_timer;		/* 0x33 */
-	u8 res8;		/* 0x34 */
+#ifdef CONFIG_M5329
+	u8 res34;		/* 0x34 */
 	u8 ppd_lcddatah;	/* 0x35 */
 	u8 ppd_lcddatam;	/* 0x36 */
 	u8 ppd_lcddatal;	/* 0x37 */
 	u8 ppd_lcdctlh;		/* 0x38 */
 	u8 ppd_lcdctll;		/* 0x39 */
-	u16 res9;		/* 0x3A - 0x3B */
+	u16 res3A;		/* 0x3A - 0x3B */
+#else
+	u16 res34;		/* 0x34 - 0x35 */
+	u8 ppd_fech;		/* 0x36 */
+	u8 ppd_fecl;		/* 0x37 */
+	u16 res38[3];		/* 0x38 - 0x3D */
+#endif
 
 	/* Port Clear Output Data Registers */
-	u8 pclrr_fech;		/* 0x3C */
-	u8 pclrr_fecl;		/* 0x3D */
+#ifdef CONFIG_M5329
+	u8 res3C;		/* 0x3C */
+	u8 pclrr_fech;		/* 0x3D */
+	u8 pclrr_fecl;		/* 0x3E */
+#else
 	u8 pclrr_ssi;		/* 0x3E */
+#endif
 	u8 pclrr_busctl;	/* 0x3F */
 	u8 pclrr_be;		/* 0x40 */
 	u8 pclrr_cs;		/* 0x41 */
 	u8 pclrr_pwm;		/* 0x42 */
 	u8 pclrr_feci2c;	/* 0x43 */
-	u8 res10;		/* 0x44 */
+	u8 res44;		/* 0x44 */
 	u8 pclrr_uart;		/* 0x45 */
 	u8 pclrr_qspi;		/* 0x46 */
 	u8 pclrr_timer;		/* 0x47 */
-	u8 res11;		/* 0x48 */
-	u8 pclrr_lcddatah;	/* 0x49 */
-	u8 pclrr_lcddatam;	/* 0x4A */
-	u8 pclrr_lcddatal;	/* 0x4B */
+#ifdef CONFIG_M5329
+	u8 pclrr_lcddatah;	/* 0x48 */
+	u8 pclrr_lcddatam;	/* 0x49 */
+	u8 pclrr_lcddatal;	/* 0x4A */
+	u8 pclrr_ssi;		/* 0x4B */
 	u8 pclrr_lcdctlh;	/* 0x4C */
 	u8 pclrr_lcdctll;	/* 0x4D */
-	u16 res12;		/* 0x4E - 0x4F */
+	u16 res4E;		/* 0x4E - 0x4F */
+#else
+	u16 res48;		/* 0x48 - 0x49 */
+	u8 pclrr_fech;		/* 0x4A */
+	u8 pclrr_fecl;		/* 0x4B */
+	u8 res4C[5];		/* 0x4C - 0x50 */
+#endif
 
 	/* Pin Assignment Registers */
+#ifdef CONFIG_M5329
 	u8 par_fec;		/* 0x50 */
+#endif
 	u8 par_pwm;		/* 0x51 */
 	u8 par_busctl;		/* 0x52 */
 	u8 par_feci2c;		/* 0x53 */
@@ -472,15 +514,20 @@ typedef struct gpio_ctrl {
 	u16 par_uart;		/* 0x58 */
 	u16 par_qspi;		/* 0x5A */
 	u8 par_timer;		/* 0x5C */
+#ifdef CONFIG_M5329
 	u8 par_lcddata;		/* 0x5D */
 	u16 par_lcdctl;		/* 0x5E */
+#else
+	u8 par_fec;		/* 0x5D */
+	u16 res5E;		/* 0x5E - 0x5F */
+#endif
 	u16 par_irq;		/* 0x60 */
-	u16 res16;		/* 0x62 - 0x63 */
+	u16 res62;		/* 0x62 - 0x63 */
 
 	/* Mode Select Control Registers */
 	u8 mscr_flexbus;	/* 0x64 */
 	u8 mscr_sdram;		/* 0x65 */
-	u16 res17;		/* 0x66 - 0x67 */
+	u16 res66;		/* 0x66 - 0x67 */
 
 	/* Drive Strength Control Registers */
 	u8 dscr_i2c;		/* 0x68 */
@@ -490,7 +537,11 @@ typedef struct gpio_ctrl {
 	u8 dscr_qspi;		/* 0x6C */
 	u8 dscr_timer;		/* 0x6D */
 	u8 dscr_ssi;		/* 0x6E */
+#ifdef CONFIG_M5329
 	u8 dscr_lcd;		/* 0x6F */
+#else
+	u8 res6F;		/* 0x6F */
+#endif
 	u8 dscr_debug;		/* 0x70 */
 	u8 dscr_clkrst;		/* 0x71 */
 	u8 dscr_irq;		/* 0x72 */
diff --git a/include/asm-m68k/m5329.h b/include/asm-m68k/m5329.h
index 8316fcf205..c1669dcb10 100644
--- a/include/asm-m68k/m5329.h
+++ b/include/asm-m68k/m5329.h
@@ -1118,6 +1118,7 @@
 #define GPIO_PCLRR_LCDCTLL7		(0x80)
 
 /* Bit definitions and macros for GPIO_PAR_FEC */
+#ifdef CONFIG_M5329
 #define GPIO_PAR_FEC_MII(x)		(((x)&0x03)<<0)
 #define GPIO_PAR_FEC_7W(x)		(((x)&0x03)<<2)
 #define GPIO_PAR_FEC_7W_GPIO		(0x00)
@@ -1126,6 +1127,10 @@
 #define GPIO_PAR_FEC_MII_GPIO		(0x00)
 #define GPIO_PAR_FEC_MII_UART		(0x01)
 #define GPIO_PAR_FEC_MII_FEC		(0x03)
+#else
+#define GPIO_PAR_FEC_7W_FEC		(0x08)
+#define GPIO_PAR_FEC_MII_FEC		(0x02)
+#endif
 
 /* Bit definitions and macros for GPIO_PAR_PWM */
 #define GPIO_PAR_PWM1(x)		(((x)&0x03)<<0)