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authorStefan Roese <sr@denx.de>2015-09-02 14:29:12 +0200
committerTom Rini <trini@konsulko.com>2015-09-11 17:15:13 -0400
commit1a103c6caa0b27fcd3798267b980444f5459860f (patch)
tree5cf3d03804ff4d29d1968fefbbcf6ea8a53222b8 /examples
parentb9599dd857b3f6ed9c7c7e7438dffb84ee5ce1a0 (diff)
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mtd: nand: fsmc: Add BCH4 SW ECC support for SPEAr600
This patch adds support for 4-bit ECC BCH4 for the SPEAr600 SoC. This can be used by boards equipped with a NAND chip that requires 4-bit ECC strength. The SPEAr600 HW ECC only supports 1-bit ECC strength. To enable SW BCH4, you need to specify this in your config header: #define CONFIG_NAND_ECC_BCH #define CONFIG_BCH And use the command "nandecc bch4" to select this ECC scheme upon runtime. Tested on SPEAr600 x600 board. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Scott Wood <scottwood@freescale.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
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