Merge branch 'master' of git://git.denx.de/u-boot-arm

7 files changed, 482 insertions, 0 deletions

diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig
index e69de29bb2..415ab4eba9 100644
--- a/drivers/mtd/Kconfig
+++ b/drivers/mtd/Kconfig
@@ -0,0 +1 @@
+source "drivers/mtd/nand/Kconfig"
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
new file mode 100644
index 0000000000..75c2c065c8
--- /dev/null
+++ b/drivers/mtd/nand/Kconfig
@@ -0,0 +1,42 @@
+menu "NAND Device Support"
+
+if !SPL_BUILD
+
+config NAND_DENALI
+	bool "Support Denali NAND controller"
+	help
+	  Enable support for the Denali NAND controller.
+
+config SYS_NAND_DENALI_64BIT
+	bool "Use 64-bit variant of Denali NAND controller"
+	depends on NAND_DENALI
+	help
+	  The Denali NAND controller IP has some variations in terms of
+	  the bus interface.  The DMA setup sequence is completely differenct
+	  between 32bit / 64bit AXI bus variants.
+
+	  If your Denali NAND controller is the 64-bit variant, say Y.
+	  Otherwise (32 bit), say N.
+
+config NAND_DENALI_SPARE_AREA_SKIP_BYTES
+	int "Number of bytes skipped in OOB area"
+	depends on NAND_DENALI
+	range 0 63
+	help
+	  This option specifies the number of bytes to skip from the beginning
+	  of OOB area before last ECC sector data starts.  This is potentially
+	  used to preserve the bad block marker in the OOB area.
+
+endif
+
+if SPL_BUILD
+
+config SPL_NAND_DENALI
+	bool "Support Denali NAND controller for SPL"
+	help
+	  This is a small implementation of the Denali NAND controller
+	  for use on SPL.
+
+endif
+
+endmenu
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index f298f8434a..47eb34f9c5 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -12,6 +12,7 @@ NORMAL_DRIVERS=y
 endif
 
 obj-$(CONFIG_SPL_NAND_AM33XX_BCH) += am335x_spl_bch.o
+obj-$(CONFIG_SPL_NAND_DENALI) += denali_spl.o
 obj-$(CONFIG_SPL_NAND_DOCG4) += docg4_spl.o
 obj-$(CONFIG_SPL_NAND_SIMPLE) += nand_spl_simple.o
 obj-$(CONFIG_SPL_NAND_LOAD) += nand_spl_load.o
diff --git a/drivers/mtd/nand/denali_spl.c b/drivers/mtd/nand/denali_spl.c
new file mode 100644
index 0000000000..65fdde8a65
--- /dev/null
+++ b/drivers/mtd/nand/denali_spl.c
@@ -0,0 +1,231 @@
+/*
+ * Copyright (C) 2014       Panasonic Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/unaligned.h>
+#include <linux/mtd/nand.h>
+#include "denali.h"
+
+#define SPARE_ACCESS		0x41
+#define MAIN_ACCESS		0x42
+#define PIPELINE_ACCESS		0x2000
+
+#define BANK(x) ((x) << 24)
+
+static void __iomem *denali_flash_mem =
+			(void __iomem *)CONFIG_SYS_NAND_DATA_BASE;
+static void __iomem *denali_flash_reg =
+			(void __iomem *)CONFIG_SYS_NAND_REGS_BASE;
+
+static const int flash_bank;
+static uint8_t page_buffer[NAND_MAX_PAGESIZE];
+static int page_size, oob_size, pages_per_block;
+
+static void index_addr(uint32_t address, uint32_t data)
+{
+	writel(address, denali_flash_mem + INDEX_CTRL_REG);
+	writel(data, denali_flash_mem + INDEX_DATA_REG);
+}
+
+static int wait_for_irq(uint32_t irq_mask)
+{
+	unsigned long timeout = 1000000;
+	uint32_t intr_status;
+
+	do {
+		intr_status = readl(denali_flash_reg + INTR_STATUS(flash_bank));
+
+		if (intr_status & INTR_STATUS__ECC_UNCOR_ERR) {
+			debug("Uncorrected ECC detected\n");
+			return -EIO;
+		}
+
+		if (intr_status & irq_mask)
+			break;
+
+		udelay(1);
+		timeout--;
+	} while (timeout);
+
+	if (!timeout) {
+		debug("Timeout with interrupt status %08x\n", intr_status);
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static void read_data_from_flash_mem(uint8_t *buf, int len)
+{
+	int i;
+	uint32_t *buf32;
+
+	/* transfer the data from the flash */
+	buf32 = (uint32_t *)buf;
+
+	/*
+	 * Let's take care of unaligned access although it rarely happens.
+	 * Avoid put_unaligned() for the normal use cases since it leads to
+	 * a bit performance regression.
+	 */
+	if ((unsigned long)buf32 % 4) {
+		for (i = 0; i < len / 4; i++)
+			put_unaligned(readl(denali_flash_mem + INDEX_DATA_REG),
+				      buf32++);
+	} else {
+		for (i = 0; i < len / 4; i++)
+			*buf32++ = readl(denali_flash_mem + INDEX_DATA_REG);
+	}
+
+	if (len % 4) {
+		u32 tmp;
+
+		tmp = cpu_to_le32(readl(denali_flash_mem + INDEX_DATA_REG));
+		buf = (uint8_t *)buf32;
+		for (i = 0; i < len % 4; i++) {
+			*buf++ = tmp;
+			tmp >>= 8;
+		}
+	}
+}
+
+int denali_send_pipeline_cmd(int page, int ecc_en, int access_type)
+{
+	uint32_t addr, cmd;
+	static uint32_t page_count = 1;
+
+	writel(ecc_en, denali_flash_reg + ECC_ENABLE);
+
+	/* clear all bits of intr_status. */
+	writel(0xffff, denali_flash_reg + INTR_STATUS(flash_bank));
+
+	addr = BANK(flash_bank) | page;
+
+	/* setup the acccess type */
+	cmd = MODE_10 | addr;
+	index_addr(cmd, access_type);
+
+	/* setup the pipeline command */
+	index_addr(cmd, PIPELINE_ACCESS | page_count);
+
+	cmd = MODE_01 | addr;
+	writel(cmd, denali_flash_mem + INDEX_CTRL_REG);
+
+	return wait_for_irq(INTR_STATUS__LOAD_COMP);
+}
+
+static int nand_read_oob(void *buf, int page)
+{
+	int ret;
+
+	ret = denali_send_pipeline_cmd(page, 0, SPARE_ACCESS);
+	if (ret < 0)
+		return ret;
+
+	read_data_from_flash_mem(buf, oob_size);
+
+	return 0;
+}
+
+static int nand_read_page(void *buf, int page)
+{
+	int ret;
+
+	ret = denali_send_pipeline_cmd(page, 1, MAIN_ACCESS);
+	if (ret < 0)
+		return ret;
+
+	read_data_from_flash_mem(buf, page_size);
+
+	return 0;
+}
+
+static int nand_block_isbad(int block)
+{
+	int ret;
+
+	ret = nand_read_oob(page_buffer, block * pages_per_block);
+	if (ret < 0)
+		return ret;
+
+	return page_buffer[CONFIG_SYS_NAND_BAD_BLOCK_POS] != 0xff;
+}
+
+/* nand_init() - initialize data to make nand usable by SPL */
+void nand_init(void)
+{
+	/* access to main area */
+	writel(0, denali_flash_reg + TRANSFER_SPARE_REG);
+
+	/*
+	 * These registers are expected to be already set by the hardware
+	 * or earlier boot code.  So we read these values out.
+	 */
+	page_size = readl(denali_flash_reg + DEVICE_MAIN_AREA_SIZE);
+	oob_size = readl(denali_flash_reg + DEVICE_SPARE_AREA_SIZE);
+	pages_per_block = readl(denali_flash_reg + PAGES_PER_BLOCK);
+}
+
+int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
+{
+	int block, page, column, readlen;
+	int ret;
+	int force_bad_block_check = 1;
+
+	page = offs / page_size;
+	column = offs % page_size;
+
+	block = page / pages_per_block;
+	page = page % pages_per_block;
+
+	while (size) {
+		if (force_bad_block_check || page == 0) {
+			ret = nand_block_isbad(block);
+			if (ret < 0)
+				return ret;
+
+			if (ret) {
+				block++;
+				continue;
+			}
+		}
+
+		force_bad_block_check = 0;
+
+		if (unlikely(column || size < page_size)) {
+			/* Partial page read */
+			ret = nand_read_page(page_buffer,
+					     block * pages_per_block + page);
+			if (ret < 0)
+				return ret;
+
+			readlen = min(page_size - column, size);
+			memcpy(dst, page_buffer, readlen);
+
+			column = 0;
+		} else {
+			ret = nand_read_page(dst,
+					     block * pages_per_block + page);
+			if (ret < 0)
+				return ret;
+
+			readlen = page_size;
+		}
+
+		size -= readlen;
+		dst += readlen;
+		page++;
+		if (page == pages_per_block) {
+			block++;
+			page = 0;
+		}
+	}
+
+	return 0;
+}
+
+void nand_deselect(void) {}
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 853a8c6919..b4f299bb0e 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -39,6 +39,7 @@ obj-$(CONFIG_FSL_LPUART) += serial_lpuart.o
 obj-$(CONFIG_MXS_AUART) += mxs_auart.o
 obj-$(CONFIG_ARC_SERIAL) += serial_arc.o
 obj-$(CONFIG_TEGRA_SERIAL) += serial_tegra.o
+obj-$(CONFIG_UNIPHIER_SERIAL) += serial_uniphier.o
 
 ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_USB_TTY) += usbtty.o
diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c
index bbe60af627..82fbbd92e2 100644
--- a/drivers/serial/serial.c
+++ b/drivers/serial/serial.c
@@ -157,6 +157,7 @@ serial_initfunc(sh_serial_initialize);
 serial_initfunc(arm_dcc_initialize);
 serial_initfunc(mxs_auart_initialize);
 serial_initfunc(arc_serial_initialize);
+serial_initfunc(uniphier_serial_initialize);
 
 /**
  * serial_register() - Register serial driver with serial driver core
@@ -250,6 +251,7 @@ void serial_initialize(void)
 	arm_dcc_initialize();
 	mxs_auart_initialize();
 	arc_serial_initialize();
+	uniphier_serial_initialize();
 
 	serial_assign(default_serial_console()->name);
 }
diff --git a/drivers/serial/serial_uniphier.c b/drivers/serial/serial_uniphier.c
new file mode 100644
index 0000000000..f8c9d921e2
--- /dev/null
+++ b/drivers/serial/serial_uniphier.c
@@ -0,0 +1,204 @@
+/*
+ * Copyright (C) 2012-2014 Panasonic Corporation
+ *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * Based on serial_ns16550.c
+ * (C) Copyright 2000
+ * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <serial.h>
+
+#define UART_REG(x)					\
+	u8 x;						\
+	u8 postpad_##x[3];
+
+/*
+ * Note: Register map is slightly different from that of 16550.
+ */
+struct uniphier_serial {
+	UART_REG(rbr);		/* 0x00 */
+	UART_REG(ier);		/* 0x04 */
+	UART_REG(iir);		/* 0x08 */
+	UART_REG(fcr);		/* 0x0c */
+	u8 mcr;			/* 0x10 */
+	u8 lcr;
+	u16 __postpad;
+	UART_REG(lsr);		/* 0x14 */
+	UART_REG(msr);		/* 0x18 */
+	u32 __none1;
+	u32 __none2;
+	u16 dlr;
+	u16 __postpad2;
+};
+
+#define thr rbr
+
+/*
+ * These are the definitions for the Line Control Register
+ */
+#define UART_LCR_WLS_8	0x03		/* 8 bit character length */
+
+/*
+ * These are the definitions for the Line Status Register
+ */
+#define UART_LSR_DR	0x01		/* Data ready */
+#define UART_LSR_THRE	0x20		/* Xmit holding register empty */
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void uniphier_serial_init(struct uniphier_serial *port)
+{
+	const unsigned int mode_x_div = 16;
+	unsigned int divisor;
+
+	writeb(UART_LCR_WLS_8, &port->lcr);
+
+	divisor = DIV_ROUND_CLOSEST(CONFIG_SYS_UNIPHIER_UART_CLK,
+						mode_x_div * gd->baudrate);
+
+	writew(divisor, &port->dlr);
+}
+
+static void uniphier_serial_setbrg(struct uniphier_serial *port)
+{
+	uniphier_serial_init(port);
+}
+
+static int uniphier_serial_tstc(struct uniphier_serial *port)
+{
+	return (readb(&port->lsr) & UART_LSR_DR) != 0;
+}
+
+static int uniphier_serial_getc(struct uniphier_serial *port)
+{
+	while (!uniphier_serial_tstc(port))
+		;
+
+	return readb(&port->rbr);
+}
+
+static void uniphier_serial_putc(struct uniphier_serial *port, const char c)
+{
+	if (c == '\n')
+		uniphier_serial_putc(port, '\r');
+
+	while (!(readb(&port->lsr) & UART_LSR_THRE))
+		;
+
+	writeb(c, &port->thr);
+}
+
+static struct uniphier_serial *serial_ports[4] = {
+#ifdef CONFIG_SYS_UNIPHIER_SERIAL_BASE0
+	(struct uniphier_serial *)CONFIG_SYS_UNIPHIER_SERIAL_BASE0,
+#else
+	NULL,
+#endif
+#ifdef CONFIG_SYS_UNIPHIER_SERIAL_BASE1
+	(struct uniphier_serial *)CONFIG_SYS_UNIPHIER_SERIAL_BASE1,
+#else
+	NULL,
+#endif
+#ifdef CONFIG_SYS_UNIPHIER_SERIAL_BASE2
+	(struct uniphier_serial *)CONFIG_SYS_UNIPHIER_SERIAL_BASE2,
+#else
+	NULL,
+#endif
+#ifdef CONFIG_SYS_UNIPHIER_SERIAL_BASE3
+	(struct uniphier_serial *)CONFIG_SYS_UNIPHIER_SERIAL_BASE3,
+#else
+	NULL,
+#endif
+};
+
+/* Multi serial device functions */
+#define DECLARE_ESERIAL_FUNCTIONS(port) \
+	static int  eserial##port##_init(void) \
+	{ \
+		uniphier_serial_init(serial_ports[port]); \
+		return 0 ; \
+	} \
+	static void eserial##port##_setbrg(void) \
+	{ \
+		uniphier_serial_setbrg(serial_ports[port]); \
+	} \
+	static int  eserial##port##_getc(void) \
+	{ \
+		return uniphier_serial_getc(serial_ports[port]); \
+	} \
+	static int  eserial##port##_tstc(void) \
+	{ \
+		return uniphier_serial_tstc(serial_ports[port]); \
+	} \
+	static void eserial##port##_putc(const char c) \
+	{ \
+		uniphier_serial_putc(serial_ports[port], c); \
+	}
+
+/* Serial device descriptor */
+#define INIT_ESERIAL_STRUCTURE(port, __name) {	\
+	.name	= __name,			\
+	.start	= eserial##port##_init,		\
+	.stop	= NULL,				\
+	.setbrg	= eserial##port##_setbrg,	\
+	.getc	= eserial##port##_getc,		\
+	.tstc	= eserial##port##_tstc,		\
+	.putc	= eserial##port##_putc,		\
+	.puts	= default_serial_puts,		\
+}
+
+#if defined(CONFIG_SYS_UNIPHIER_SERIAL_BASE0)
+DECLARE_ESERIAL_FUNCTIONS(0);
+struct serial_device uniphier_serial0_device =
+	INIT_ESERIAL_STRUCTURE(0, "ttyS0");
+#endif
+#if defined(CONFIG_SYS_UNIPHIER_SERIAL_BASE1)
+DECLARE_ESERIAL_FUNCTIONS(1);
+struct serial_device uniphier_serial1_device =
+	INIT_ESERIAL_STRUCTURE(1, "ttyS1");
+#endif
+#if defined(CONFIG_SYS_UNIPHIER_SERIAL_BASE2)
+DECLARE_ESERIAL_FUNCTIONS(2);
+struct serial_device uniphier_serial2_device =
+	INIT_ESERIAL_STRUCTURE(2, "ttyS2");
+#endif
+#if defined(CONFIG_SYS_UNIPHIER_SERIAL_BASE3)
+DECLARE_ESERIAL_FUNCTIONS(3);
+struct serial_device uniphier_serial3_device =
+	INIT_ESERIAL_STRUCTURE(3, "ttyS3");
+#endif
+
+__weak struct serial_device *default_serial_console(void)
+{
+#if defined(CONFIG_SYS_UNIPHIER_SERIAL_BASE0)
+	return &uniphier_serial0_device;
+#elif defined(CONFIG_SYS_UNIPHIER_SERIAL_BASE1)
+	return &uniphier_serial1_device;
+#elif defined(CONFIG_SYS_UNIPHIER_SERIAL_BASE2)
+	return &uniphier_serial2_device;
+#elif defined(CONFIG_SYS_UNIPHIER_SERIAL_BASE3)
+	return &uniphier_serial3_device;
+#else
+#error "No uniphier serial ports configured."
+#endif
+}
+
+void uniphier_serial_initialize(void)
+{
+#if defined(CONFIG_SYS_UNIPHIER_SERIAL_BASE0)
+	serial_register(&uniphier_serial0_device);
+#endif
+#if defined(CONFIG_SYS_UNIPHIER_SERIAL_BASE1)
+	serial_register(&uniphier_serial1_device);
+#endif
+#if defined(CONFIG_SYS_UNIPHIER_SERIAL_BASE2)
+	serial_register(&uniphier_serial2_device);
+#endif
+#if defined(CONFIG_SYS_UNIPHIER_SERIAL_BASE3)
+	serial_register(&uniphier_serial3_device);
+#endif
+}