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| author | Vishnu Patekar <vishnupatekar0510@gmail.com> | 2015-03-01 23:47:48 +0530 |
|---|---|---|
| committer | Hans de Goede <hdegoede@redhat.com> | 2015-05-04 16:51:51 +0200 |
| commit | 8c3dacff1409109e3697ed60df0e7c93d1309a93 (patch) | |
| tree | 25f0eb800ffc377abfb949dc96b94fe3b06c90bf /drivers | |
| parent | ffc0ae0c70decbe5a91001cbe97e0a511bdf6e88 (diff) | |
| download | blackbird-obmc-uboot-8c3dacff1409109e3697ed60df0e7c93d1309a93.tar.gz blackbird-obmc-uboot-8c3dacff1409109e3697ed60df0e7c93d1309a93.zip | |
sunxi: Add basic A33 basic support
Enable full support for the A33 SoC including display, otg-usb, etc.
Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/usb/musb-new/musb_regs.h | 5 | ||||
| -rw-r--r-- | drivers/video/sunxi_display.c | 3 |
2 files changed, 8 insertions, 0 deletions
diff --git a/drivers/usb/musb-new/musb_regs.h b/drivers/usb/musb-new/musb_regs.h index 27e4ed4ec6..90288c4694 100644 --- a/drivers/usb/musb-new/musb_regs.h +++ b/drivers/usb/musb-new/musb_regs.h @@ -458,8 +458,13 @@ static inline u8 musb_read_ulpi_buscontrol(void __iomem *mbase) static inline u8 musb_read_configdata(void __iomem *mbase) { +#ifdef CONFIG_MACH_SUN8I_A33 + /* <Sigh> allwinner saves a reg, and we need to hardcode this */ + return 0xde; +#else musb_writeb(mbase, MUSB_INDEX, 0); return musb_readb(mbase, 0x10 + MUSB_CONFIGDATA); +#endif } static inline u16 musb_read_hwvers(void __iomem *mbase) diff --git a/drivers/video/sunxi_display.c b/drivers/video/sunxi_display.c index 2ee105690f..1163ecf061 100644 --- a/drivers/video/sunxi_display.c +++ b/drivers/video/sunxi_display.c @@ -947,6 +947,9 @@ static void sunxi_drc_init(void) (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; /* On sun6i the drc must be clocked even when in pass-through mode */ +#ifdef CONFIG_MACH_SUN8I_A33 + setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_SAT); +#endif setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DRC0); clock_set_de_mod_clock(&ccm->iep_drc0_clk_cfg, 300000000); #endif |
