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| author | Jagan Teki <jteki@openedev.com> | 2015-10-22 21:06:37 +0530 |
|---|---|---|
| committer | Jagan Teki <jteki@openedev.com> | 2015-10-27 23:19:15 +0530 |
| commit | 9cf2ffb3c3721c28f8d6473df0fa8693f5bead7d (patch) | |
| tree | 5774b8c3639571c8bf93bda3d7c8fe2f7fb864e6 /drivers/spi/zynq_spi.c | |
| parent | 736b4df15d603325f97663a7a4f26f7abf454dcf (diff) | |
| download | blackbird-obmc-uboot-9cf2ffb3c3721c28f8d6473df0fa8693f5bead7d.tar.gz blackbird-obmc-uboot-9cf2ffb3c3721c28f8d6473df0fa8693f5bead7d.zip | |
spi: zynq_[q]spi: Use GENMASK macro
GENMASK macro used on zynq_spi.c and zynq_qspi.c
GENMASK is used to create a contiguous bitmask([hi:lo]).
Ex: (0x7 << 3) => GENMASK(5, 3)
Cc: Michal Simek <michal.simek@xilinx.com>
Acked-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
Diffstat (limited to 'drivers/spi/zynq_spi.c')
| -rw-r--r-- | drivers/spi/zynq_spi.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c index ce8acb437e..6ed2165355 100644 --- a/drivers/spi/zynq_spi.c +++ b/drivers/spi/zynq_spi.c @@ -18,14 +18,14 @@ DECLARE_GLOBAL_DATA_PTR; /* zynq spi register bit masks ZYNQ_SPI_<REG>_<BIT>_MASK */ #define ZYNQ_SPI_CR_MSA_MASK BIT(15) /* Manual start enb */ #define ZYNQ_SPI_CR_MCS_MASK BIT(14) /* Manual chip select */ -#define ZYNQ_SPI_CR_CS_MASK (0xF << 10) /* Chip select */ -#define ZYNQ_SPI_CR_BAUD_MASK (0x7 << 3) /* Baud rate div */ +#define ZYNQ_SPI_CR_CS_MASK GENMASK(13, 10) /* Chip select */ +#define ZYNQ_SPI_CR_BAUD_MASK GENMASK(5, 3) /* Baud rate div */ #define ZYNQ_SPI_CR_CPHA_MASK BIT(2) /* Clock phase */ #define ZYNQ_SPI_CR_CPOL_MASK BIT(1) /* Clock polarity */ #define ZYNQ_SPI_CR_MSTREN_MASK BIT(0) /* Mode select */ #define ZYNQ_SPI_IXR_RXNEMPTY_MASK BIT(4) /* RX_FIFO_not_empty */ #define ZYNQ_SPI_IXR_TXOW_MASK BIT(2) /* TX_FIFO_not_full */ -#define ZYNQ_SPI_IXR_ALL_MASK 0x7F /* All IXR bits */ +#define ZYNQ_SPI_IXR_ALL_MASK GENMASK(6, 0) /* All IXR bits */ #define ZYNQ_SPI_ENR_SPI_EN_MASK BIT(0) /* SPI Enable */ #define ZYNQ_SPI_CR_BAUD_MAX 8 /* Baud rate divisor max val */ |
