summaryrefslogtreecommitdiffstats
path: root/drivers/pci
diff options
context:
space:
mode:
authorStephen Warren <swarren@nvidia.com>2015-10-05 17:00:40 -0600
committerTom Warren <twarren@nvidia.com>2015-11-12 09:21:05 -0700
commitbec05246f637d2c6f46e6b6a8073d4fa1d6141ec (patch)
treeba759fd02ef4fac16920e3f34219b943be193648 /drivers/pci
parentdfa551e49c072b9f4e1b0486a4091cd80733733b (diff)
downloadblackbird-obmc-uboot-bec05246f637d2c6f46e6b6a8073d4fa1d6141ec.tar.gz
blackbird-obmc-uboot-bec05246f637d2c6f46e6b6a8073d4fa1d6141ec.zip
pci: tegra: clip RAM size to 32-bits
Tegra peripherals can generally access a 32-bit physical address space, and I believe this applies to PCIe. Clip the PCI region that refers to DRAM so it fits into 32-bits to avoid issues. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'drivers/pci')
-rw-r--r--drivers/pci/pci_tegra.c10
1 files changed, 9 insertions, 1 deletions
diff --git a/drivers/pci/pci_tegra.c b/drivers/pci/pci_tegra.c
index ebb959f1f3..357e7793b4 100644
--- a/drivers/pci/pci_tegra.c
+++ b/drivers/pci/pci_tegra.c
@@ -997,6 +997,14 @@ static const struct tegra_pcie_soc tegra124_pcie_soc = {
static int process_nodes(const void *fdt, int nodes[], unsigned int count)
{
unsigned int i;
+ uint64_t dram_end;
+ uint32_t pci_dram_size;
+
+ /* Clip PCI-accessible DRAM to 32-bits */
+ dram_end = ((uint64_t)NV_PA_SDRAM_BASE) + gd->ram_size;
+ if (dram_end > 0x100000000)
+ dram_end = 0x100000000;
+ pci_dram_size = dram_end - NV_PA_SDRAM_BASE;
for (i = 0; i < count; i++) {
const struct tegra_pcie_soc *soc;
@@ -1069,7 +1077,7 @@ static int process_nodes(const void *fdt, int nodes[], unsigned int count)
pcie->hose.last_busno = 0;
pci_set_region(&pcie->hose.regions[0], NV_PA_SDRAM_BASE,
- NV_PA_SDRAM_BASE, gd->ram_size,
+ NV_PA_SDRAM_BASE, pci_dram_size,
PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
pci_set_region(&pcie->hose.regions[1], pcie->io.start,
OpenPOWER on IntegriCloud