[FIX] remove cute code

1 files changed, 118 insertions, 115 deletions

diff --git a/drivers/net/xilinx_emac.c b/drivers/net/xilinx_emac.c
index d44f31e8af..23567cc40a 100644
--- a/drivers/net/xilinx_emac.c
+++ b/drivers/net/xilinx_emac.c
@@ -41,76 +41,78 @@
 
 static unsigned int etherrxbuff[PKTSIZE_ALIGN/4]; /* Receive buffer */
 
-static u8 EMACAddr[ENET_ADDR_LENGTH] = { 0x00, 0x0a, 0x35, 0x00, 0x22, 0x01 };
+static u8 emacaddr[ENET_ADDR_LENGTH] = { 0x00, 0x0a, 0x35, 0x00, 0x22, 0x01 };
 
-static XEmac Emac;
+static xemac emac;
 
 void eth_halt(void)
 {
-	return;
+#ifdef DEBUG
+	puts ("eth_halt\n");
+#endif
 }
 
 int eth_init(bd_t * bis)
 {
-	u32 HelpReg;
+	u32 helpreg;
 #ifdef DEBUG
 	printf("EMAC Initialization Started\n\r");
 #endif
-	if (Emac.IsStarted) {
+	if (emac.isstarted) {
 		puts("Emac is started\n");
 		return 0;
 	}
 
-	memset (&Emac, 0, sizeof (XEmac));
+	memset (&emac, 0, sizeof (xemac));
 
-	Emac.BaseAddress = XILINX_EMAC_BASEADDR;
+	emac.baseaddress = XILINX_EMAC_BASEADDR;
 
 	/* Setting up FIFOs */
-	Emac.RecvFifo.RegBaseAddress = Emac.BaseAddress +
+	emac.recvfifo.regbaseaddress = emac.baseaddress +
 					XEM_PFIFO_RXREG_OFFSET;
-	Emac.RecvFifo.DataBaseAddress = Emac.BaseAddress +
+	emac.recvfifo.databaseaddress = emac.baseaddress +
 					XEM_PFIFO_RXDATA_OFFSET;
-	out_be32 (Emac.RecvFifo.RegBaseAddress, XPF_RESET_FIFO_MASK);
+	out_be32 (emac.recvfifo.regbaseaddress, XPF_RESET_FIFO_MASK);
 
-	Emac.SendFifo.RegBaseAddress = Emac.BaseAddress +
+	emac.sendfifo.regbaseaddress = emac.baseaddress +
 					XEM_PFIFO_TXREG_OFFSET;
-	Emac.SendFifo.DataBaseAddress = Emac.BaseAddress +
+	emac.sendfifo.databaseaddress = emac.baseaddress +
 					XEM_PFIFO_TXDATA_OFFSET;
-	out_be32 (Emac.SendFifo.RegBaseAddress, XPF_RESET_FIFO_MASK);
+	out_be32 (emac.sendfifo.regbaseaddress, XPF_RESET_FIFO_MASK);
 
 	/* Reset the entire IPIF */
-	out_be32 (Emac.BaseAddress + XIIF_V123B_RESETR_OFFSET,
+	out_be32 (emac.baseaddress + XIIF_V123B_RESETR_OFFSET,
 					XIIF_V123B_RESET_MASK);
 
 	/* Stopping EMAC for setting up MAC */
-	HelpReg = in_be32 (Emac.BaseAddress + XEM_ECR_OFFSET);
-	HelpReg &= ~(XEM_ECR_XMIT_ENABLE_MASK | XEM_ECR_RECV_ENABLE_MASK);
-	out_be32 (Emac.BaseAddress + XEM_ECR_OFFSET, HelpReg);
+	helpreg = in_be32 (emac.baseaddress + XEM_ECR_OFFSET);
+	helpreg &= ~(XEM_ECR_XMIT_ENABLE_MASK | XEM_ECR_RECV_ENABLE_MASK);
+	out_be32 (emac.baseaddress + XEM_ECR_OFFSET, helpreg);
 
 	if (!getenv("ethaddr")) {
-		memcpy(bis->bi_enetaddr, EMACAddr, ENET_ADDR_LENGTH);
+		memcpy(bis->bi_enetaddr, emacaddr, ENET_ADDR_LENGTH);
 	}
 
 	/* Set the device station address high and low registers */
-	HelpReg = (bis->bi_enetaddr[0] << 8) | bis->bi_enetaddr[1];
-	out_be32 (Emac.BaseAddress + XEM_SAH_OFFSET, HelpReg);
-	HelpReg = (bis->bi_enetaddr[2] << 24) | (bis->bi_enetaddr[3] << 16) |
+	helpreg = (bis->bi_enetaddr[0] << 8) | bis->bi_enetaddr[1];
+	out_be32 (emac.baseaddress + XEM_SAH_OFFSET, helpreg);
+	helpreg = (bis->bi_enetaddr[2] << 24) | (bis->bi_enetaddr[3] << 16) |
 			(bis->bi_enetaddr[4] << 8) | bis->bi_enetaddr[5];
-	out_be32 (Emac.BaseAddress + XEM_SAL_OFFSET, HelpReg);
+	out_be32 (emac.baseaddress + XEM_SAL_OFFSET, helpreg);
 
 
-	HelpReg = XEM_ECR_UNICAST_ENABLE_MASK | XEM_ECR_BROAD_ENABLE_MASK |
+	helpreg = XEM_ECR_UNICAST_ENABLE_MASK | XEM_ECR_BROAD_ENABLE_MASK |
 		XEM_ECR_FULL_DUPLEX_MASK | XEM_ECR_XMIT_FCS_ENABLE_MASK |
 		XEM_ECR_XMIT_PAD_ENABLE_MASK | XEM_ECR_PHY_ENABLE_MASK;
-	out_be32 (Emac.BaseAddress + XEM_ECR_OFFSET, HelpReg);
+	out_be32 (emac.baseaddress + XEM_ECR_OFFSET, helpreg);
 
-	Emac.IsStarted = 1;
+	emac.isstarted = 1;
 
 	/* Enable the transmitter, and receiver */
-	HelpReg = in_be32 (Emac.BaseAddress + XEM_ECR_OFFSET);
-	HelpReg &= ~(XEM_ECR_XMIT_RESET_MASK | XEM_ECR_RECV_RESET_MASK);
-	HelpReg |= (XEM_ECR_XMIT_ENABLE_MASK | XEM_ECR_RECV_ENABLE_MASK);
-	out_be32 (Emac.BaseAddress + XEM_ECR_OFFSET, HelpReg);
+	helpreg = in_be32 (emac.baseaddress + XEM_ECR_OFFSET);
+	helpreg &= ~(XEM_ECR_XMIT_RESET_MASK | XEM_ECR_RECV_RESET_MASK);
+	helpreg |= (XEM_ECR_XMIT_ENABLE_MASK | XEM_ECR_RECV_ENABLE_MASK);
+	out_be32 (emac.baseaddress + XEM_ECR_OFFSET, helpreg);
 
 	printf("EMAC Initialization complete\n\r");
 	return 0;
@@ -118,12 +120,12 @@ int eth_init(bd_t * bis)
 
 int eth_send(volatile void *ptr, int len)
 {
-	u32 IntrStatus;
-	u32 XmitStatus;
-	u32 FifoCount;
-	u32 WordCount;
-	u32 ExtraByteCount;
-	u32 *WordBuffer = (u32 *) ptr;
+	u32 intrstatus;
+	u32 xmitstatus;
+	u32 fifocount;
+	u32 wordcount;
+	u32 extrabytecount;
+	u32 *wordbuffer = (u32 *) ptr;
 
 	if (len > ENET_MAX_MTU)
 		len = ENET_MAX_MTU;
@@ -135,20 +137,20 @@ int eth_send(volatile void *ptr, int len)
 	 * continue. The upper layer software should reset the device to resolve
 	 * the error.
 	 */
-	IntrStatus = in_be32 ((Emac.BaseAddress) + XIIF_V123B_IISR_OFFSET);
-	if (IntrStatus & (XEM_EIR_XMIT_SFIFO_OVER_MASK |
+	intrstatus = in_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET);
+	if (intrstatus & (XEM_EIR_XMIT_SFIFO_OVER_MASK |
 			XEM_EIR_XMIT_LFIFO_OVER_MASK)) {
 #ifdef DEBUG
 		puts ("Transmitting overrun error\n");
 #endif
 		return 0;
-	} else if (IntrStatus & (XEM_EIR_XMIT_SFIFO_UNDER_MASK |
+	} else if (intrstatus & (XEM_EIR_XMIT_SFIFO_UNDER_MASK |
 			XEM_EIR_XMIT_LFIFO_UNDER_MASK)) {
 #ifdef DEBUG
 		puts ("Transmitting underrun error\n");
 #endif
 		return 0;
-	} else if (in_be32 (Emac.SendFifo.RegBaseAddress +
+	} else if (in_be32 (emac.sendfifo.regbaseaddress +
 			XPF_COUNT_STATUS_REG_OFFSET) & XPF_DEADLOCK_MASK) {
 #ifdef DEBUG
 		puts("Transmitting fifo error\n");
@@ -165,9 +167,9 @@ int eth_send(volatile void *ptr, int len)
 	 * Clear the latched LFIFO_FULL bit so next time around the most
 	 * current status is represented
 	 */
-	if (IntrStatus & XEM_EIR_XMIT_LFIFO_FULL_MASK) {
-		out_be32 ((Emac.BaseAddress) + XIIF_V123B_IISR_OFFSET, IntrStatus
-				& XEM_EIR_XMIT_LFIFO_FULL_MASK);
+	if (intrstatus & XEM_EIR_XMIT_LFIFO_FULL_MASK) {
+		out_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET,
+			intrstatus & XEM_EIR_XMIT_LFIFO_FULL_MASK);
 #ifdef DEBUG
 		puts ("Fifo is full\n");
 #endif
@@ -175,72 +177,72 @@ int eth_send(volatile void *ptr, int len)
 	}
 
 	/* get the count of how many words may be inserted into the FIFO */
-	FifoCount = in_be32 (Emac.SendFifo.RegBaseAddress +
+	fifocount = in_be32 (emac.sendfifo.regbaseaddress +
 				XPF_COUNT_STATUS_REG_OFFSET) & XPF_COUNT_MASK;
-	WordCount = len >> 2;
-	ExtraByteCount = len & 0x3;
+	wordcount = len >> 2;
+	extrabytecount = len & 0x3;
 
-	if (FifoCount < WordCount) {
+	if (fifocount < wordcount) {
 #ifdef DEBUG
 		puts ("Sending packet is larger then size of FIFO\n");
 #endif
 		return 0;
 	}
 
-	for (FifoCount = 0; FifoCount < WordCount; FifoCount++) {
-		out_be32 (Emac.SendFifo.DataBaseAddress, WordBuffer[FifoCount]);
+	for (fifocount = 0; fifocount < wordcount; fifocount++) {
+		out_be32 (emac.sendfifo.databaseaddress, wordbuffer[fifocount]);
 	}
-	if (ExtraByteCount > 0) {
-		u32 LastWord = 0;
-		u8 *ExtraBytesBuffer = (u8 *) (WordBuffer + WordCount);
-
-		if (ExtraByteCount == 1) {
-			LastWord = ExtraBytesBuffer[0] << 24;
-		} else if (ExtraByteCount == 2) {
-			LastWord = ExtraBytesBuffer[0] << 24 |
-				ExtraBytesBuffer[1] << 16;
-		} else if (ExtraByteCount == 3) {
-			LastWord = ExtraBytesBuffer[0] << 24 |
-				ExtraBytesBuffer[1] << 16 |
-				ExtraBytesBuffer[2] << 8;
+	if (extrabytecount > 0) {
+		u32 lastword = 0;
+		u8 *extrabytesbuffer = (u8 *) (wordbuffer + wordcount);
+
+		if (extrabytecount == 1) {
+			lastword = extrabytesbuffer[0] << 24;
+		} else if (extrabytecount == 2) {
+			lastword = extrabytesbuffer[0] << 24 |
+				extrabytesbuffer[1] << 16;
+		} else if (extrabytecount == 3) {
+			lastword = extrabytesbuffer[0] << 24 |
+				extrabytesbuffer[1] << 16 |
+				extrabytesbuffer[2] << 8;
 		}
-		out_be32 (Emac.SendFifo.DataBaseAddress, LastWord);
+		out_be32 (emac.sendfifo.databaseaddress, lastword);
 	}
 
 	/* Loop on the MAC's status to wait for any pause to complete */
-	IntrStatus = in_be32 ((Emac.BaseAddress) + XIIF_V123B_IISR_OFFSET);
-	while ((IntrStatus & XEM_EIR_XMIT_PAUSE_MASK) != 0) {
-		IntrStatus = in_be32 ((Emac.BaseAddress) +
+	intrstatus = in_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET);
+	while ((intrstatus & XEM_EIR_XMIT_PAUSE_MASK) != 0) {
+		intrstatus = in_be32 ((emac.baseaddress) +
 					XIIF_V123B_IISR_OFFSET);
 		/* Clear the pause status from the transmit status register */
-		out_be32 ((Emac.BaseAddress) + XIIF_V123B_IISR_OFFSET,
-				IntrStatus & XEM_EIR_XMIT_PAUSE_MASK);
+		out_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET,
+				intrstatus & XEM_EIR_XMIT_PAUSE_MASK);
 	}
 
 	/*
 	 * Set the MAC's transmit packet length register to tell it to transmit
 	 */
-	out_be32 (Emac.BaseAddress + XEM_TPLR_OFFSET, len);
+	out_be32 (emac.baseaddress + XEM_TPLR_OFFSET, len);
 
 	/*
 	 * Loop on the MAC's status to wait for the transmit to complete.
 	 * The transmit status is in the FIFO when the XMIT_DONE bit is set.
 	 */
 	do {
-		IntrStatus = in_be32 ((Emac.BaseAddress) +
+		intrstatus = in_be32 ((emac.baseaddress) +
 						XIIF_V123B_IISR_OFFSET);
 	}
-	while ((IntrStatus & XEM_EIR_XMIT_DONE_MASK) == 0);
+	while ((intrstatus & XEM_EIR_XMIT_DONE_MASK) == 0);
 
-	XmitStatus = in_be32 (Emac.BaseAddress + XEM_TSR_OFFSET);
+	xmitstatus = in_be32 (emac.baseaddress + XEM_TSR_OFFSET);
 
-	if (IntrStatus & (XEM_EIR_XMIT_SFIFO_OVER_MASK |
+	if (intrstatus & (XEM_EIR_XMIT_SFIFO_OVER_MASK |
 					XEM_EIR_XMIT_LFIFO_OVER_MASK)) {
 #ifdef DEBUG
 		puts ("Transmitting overrun error\n");
 #endif
 		return 0;
-	} else if (IntrStatus & (XEM_EIR_XMIT_SFIFO_UNDER_MASK |
+	} else if (intrstatus & (XEM_EIR_XMIT_SFIFO_UNDER_MASK |
 					XEM_EIR_XMIT_LFIFO_UNDER_MASK)) {
 #ifdef DEBUG
 		puts ("Transmitting underrun error\n");
@@ -249,15 +251,15 @@ int eth_send(volatile void *ptr, int len)
 	}
 
 	/* Clear the interrupt status register of transmit statuses */
-	out_be32 ((Emac.BaseAddress) + XIIF_V123B_IISR_OFFSET,
-				IntrStatus & XEM_EIR_XMIT_ALL_MASK);
+	out_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET,
+				intrstatus & XEM_EIR_XMIT_ALL_MASK);
 
 	/*
 	 * Collision errors are stored in the transmit status register
 	 * instead of the interrupt status register
 	 */
-	if ((XmitStatus & XEM_TSR_EXCESS_DEFERRAL_MASK) ||
-				(XmitStatus & XEM_TSR_LATE_COLLISION_MASK)) {
+	if ((xmitstatus & XEM_TSR_EXCESS_DEFERRAL_MASK) ||
+				(xmitstatus & XEM_TSR_LATE_COLLISION_MASK)) {
 #ifdef DEBUG
 		puts ("Transmitting collision error\n");
 #endif
@@ -268,17 +270,17 @@ int eth_send(volatile void *ptr, int len)
 
 int eth_rx(void)
 {
-	u32 PktLength;
-	u32 IntrStatus;
-	u32 FifoCount;
-	u32 WordCount;
-	u32 ExtraByteCount;
-	u32 LastWord;
-	u8 *ExtraBytesBuffer;
-
-	if (in_be32 (Emac.RecvFifo.RegBaseAddress + XPF_COUNT_STATUS_REG_OFFSET)
+	u32 pktlength;
+	u32 intrstatus;
+	u32 fifocount;
+	u32 wordcount;
+	u32 extrabytecount;
+	u32 lastword;
+	u8 *extrabytesbuffer;
+
+	if (in_be32 (emac.recvfifo.regbaseaddress + XPF_COUNT_STATUS_REG_OFFSET)
 			& XPF_DEADLOCK_MASK) {
-		out_be32 (Emac.RecvFifo.RegBaseAddress, XPF_RESET_FIFO_MASK);
+		out_be32 (emac.recvfifo.regbaseaddress, XPF_RESET_FIFO_MASK);
 #ifdef DEBUG
 		puts ("Receiving FIFO deadlock\n");
 #endif
@@ -286,17 +288,18 @@ int eth_rx(void)
 	}
 
 	/*
-	 * Get the interrupt status to know what happened (whether an error occurred
-	 * and/or whether frames have been received successfully). When clearing the
-	 * intr status register, clear only statuses that pertain to receive.
+	 * Get the interrupt status to know what happened (whether an error
+	 * occurred and/or whether frames have been received successfully).
+	 * When clearing the intr status register, clear only statuses that
+	 * pertain to receive.
 	 */
-	IntrStatus = in_be32 ((Emac.BaseAddress) + XIIF_V123B_IISR_OFFSET);
+	intrstatus = in_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET);
 	/*
 	 * Before reading from the length FIFO, make sure the length FIFO is not
 	 * empty. We could cause an underrun error if we try to read from an
 	 * empty FIFO.
 	 */
-	if (!(IntrStatus & XEM_EIR_RECV_DONE_MASK)) {
+	if (!(intrstatus & XEM_EIR_RECV_DONE_MASK)) {
 #ifdef DEBUG
 		/* puts("Receiving FIFO is empty\n"); */
 #endif
@@ -307,8 +310,8 @@ int eth_rx(void)
 	 * Determine, from the MAC, the length of the next packet available
 	 * in the data FIFO (there should be a non-zero length here)
 	 */
-	PktLength = in_be32 (Emac.BaseAddress + XEM_RPLR_OFFSET);
-	if (!PktLength) {
+	pktlength = in_be32 (emac.baseaddress + XEM_RPLR_OFFSET);
+	if (!pktlength) {
 		return 0;
 	}
 
@@ -320,53 +323,53 @@ int eth_rx(void)
 	 * in the IPIF, which means it may indicate a non-empty condition even
 	 * though there is something in the FIFO.
 	 */
-	out_be32 ((Emac.BaseAddress) + XIIF_V123B_IISR_OFFSET,
+	out_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET,
 						XEM_EIR_RECV_DONE_MASK);
 
-	FifoCount = in_be32 (Emac.RecvFifo.RegBaseAddress +
+	fifocount = in_be32 (emac.recvfifo.regbaseaddress +
 				XPF_COUNT_STATUS_REG_OFFSET) & XPF_COUNT_MASK;
 
-	if ((FifoCount * 4) < PktLength) {
+	if ((fifocount * 4) < pktlength) {
 #ifdef DEBUG
 		puts ("Receiving FIFO is smaller than packet size.\n");
 #endif
 		return 0;
 	}
 
-	WordCount = PktLength >> 2;
-	ExtraByteCount = PktLength & 0x3;
+	wordcount = pktlength >> 2;
+	extrabytecount = pktlength & 0x3;
 
-	for (FifoCount = 0; FifoCount < WordCount; FifoCount++) {
-		etherrxbuff[FifoCount] =
-				in_be32 (Emac.RecvFifo.DataBaseAddress);
+	for (fifocount = 0; fifocount < wordcount; fifocount++) {
+		etherrxbuff[fifocount] =
+				in_be32 (emac.recvfifo.databaseaddress);
 	}
 
 	/*
 	 * if there are extra bytes to handle, read the last word from the FIFO
 	 * and insert the extra bytes into the buffer
 	 */
-	if (ExtraByteCount > 0) {
-		ExtraBytesBuffer = (u8 *) (etherrxbuff + WordCount);
+	if (extrabytecount > 0) {
+		extrabytesbuffer = (u8 *) (etherrxbuff + wordcount);
 
-		LastWord = in_be32 (Emac.RecvFifo.DataBaseAddress);
+		lastword = in_be32 (emac.recvfifo.databaseaddress);
 
 		/*
 		 * one extra byte in the last word, put the byte into the next
 		 * location of the buffer, bytes in a word of the FIFO are
 		 * ordered from most significant byte to least
 		 */
-		if (ExtraByteCount == 1) {
-			ExtraBytesBuffer[0] = (u8) (LastWord >> 24);
-		} else if (ExtraByteCount == 2) {
-			ExtraBytesBuffer[0] = (u8) (LastWord >> 24);
-			ExtraBytesBuffer[1] = (u8) (LastWord >> 16);
-		} else if (ExtraByteCount == 3) {
-			ExtraBytesBuffer[0] = (u8) (LastWord >> 24);
-			ExtraBytesBuffer[1] = (u8) (LastWord >> 16);
-			ExtraBytesBuffer[2] = (u8) (LastWord >> 8);
+		if (extrabytecount == 1) {
+			extrabytesbuffer[0] = (u8) (lastword >> 24);
+		} else if (extrabytecount == 2) {
+			extrabytesbuffer[0] = (u8) (lastword >> 24);
+			extrabytesbuffer[1] = (u8) (lastword >> 16);
+		} else if (extrabytecount == 3) {
+			extrabytesbuffer[0] = (u8) (lastword >> 24);
+			extrabytesbuffer[1] = (u8) (lastword >> 16);
+			extrabytesbuffer[2] = (u8) (lastword >> 8);
 		}
 	}
-	NetReceive((uchar *)etherrxbuff, PktLength);
+	NetReceive((uchar *)etherrxbuff, pktlength);
 	return 1;
 }
 #endif