arm: mvebu: Add Armada 38x DDR3 training code from Marvell bin_hdr

This patch adds the DDR3 setup and training code taken from the Marvell
U-Boot repository. This code used to be included as a binary (bin_hdr)
into the Armada A38x boot image. Not linked with the main U-Boot. With this
code addition and the serdes/PHY setup code, the Armada A38x support
in mainline U-Boot is finally self-contained. So the complete image
for booting can be built from mainline U-Boot. Without any additional
external inclusion.

Note:
This code has undergone many hours (days!) of coding-style cleanup and
refactoring. It still is not checkpatch clean though, I'm afraid. As the
factoring of the code has so many levels of indentation that many lines
are longer than 80 chars.

Signed-off-by: Stefan Roese <sr@denx.de>

1 files changed, 41 insertions, 0 deletions

diff --git a/drivers/ddr/marvell/a38x/ddr3_training_ip_pbs.h b/drivers/ddr/marvell/a38x/ddr3_training_ip_pbs.h
new file mode 100644
index 0000000000..c6be67c40a
--- /dev/null
+++ b/drivers/ddr/marvell/a38x/ddr3_training_ip_pbs.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef _DDR3_TRAINING_IP_PBS_H_
+#define _DDR3_TRAINING_IP_PBS_H_
+
+enum {
+	EBA_CONFIG,
+	EEBA_CONFIG,
+	SBA_CONFIG
+};
+
+enum hws_training_load_op {
+	TRAINING_LOAD_OPERATION_UNLOAD,
+	TRAINING_LOAD_OPERATION_LOAD
+};
+
+enum hws_edge {
+	TRAINING_EDGE_1,
+	TRAINING_EDGE_2
+};
+
+enum hws_edge_search {
+	TRAINING_EDGE_MAX,
+	TRAINING_EDGE_MIN
+};
+
+enum pbs_dir {
+	PBS_TX_MODE = 0,
+	PBS_RX_MODE,
+	NUM_OF_PBS_MODES
+};
+
+int ddr3_tip_pbs_rx(u32 dev_num);
+int ddr3_tip_print_all_pbs_result(u32 dev_num);
+int ddr3_tip_pbs_tx(u32 dev_num);
+
+#endif /* _DDR3_TRAINING_IP_PBS_H_ */