diff options
author | Tom Rini <trini@konsulko.com> | 2015-07-23 09:02:28 -0400 |
---|---|---|
committer | Tom Rini <trini@konsulko.com> | 2015-07-23 09:02:28 -0400 |
commit | 3c9cc70d7153da442575112d9a2643eecd17d534 (patch) | |
tree | b7f2abf20d86dfcb99e4a5406c3dd1b85c176b9f /drivers/ddr/marvell/a38x/ddr3_hws_hw_training.h | |
parent | 6b9f9eadffb5f64801746593784e12f07f2fadd0 (diff) | |
parent | 9e30b31d20f0b793465d07f056b3d9885f578c0d (diff) | |
download | blackbird-obmc-uboot-3c9cc70d7153da442575112d9a2643eecd17d534.tar.gz blackbird-obmc-uboot-3c9cc70d7153da442575112d9a2643eecd17d534.zip |
Merge git://git.denx.de/u-boot-marvell
Diffstat (limited to 'drivers/ddr/marvell/a38x/ddr3_hws_hw_training.h')
-rw-r--r-- | drivers/ddr/marvell/a38x/ddr3_hws_hw_training.h | 49 |
1 files changed, 49 insertions, 0 deletions
diff --git a/drivers/ddr/marvell/a38x/ddr3_hws_hw_training.h b/drivers/ddr/marvell/a38x/ddr3_hws_hw_training.h new file mode 100644 index 0000000000..17a09530d7 --- /dev/null +++ b/drivers/ddr/marvell/a38x/ddr3_hws_hw_training.h @@ -0,0 +1,49 @@ +/* + * Copyright (C) Marvell International Ltd. and its affiliates + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _DDR3_HWS_HW_TRAINING_H +#define _DDR3_HWS_HW_TRAINING_H + +/* struct used for DLB configuration array */ +struct dlb_config { + u32 reg_addr; + u32 reg_data; +}; + +/* Topology update structure */ +struct topology_update_info { + int update_ecc; + u8 ecc; + int update_width; + u8 width; + int update_ecc_pup3_mode; + u8 ecc_pup_mode_offset; +}; + +/* Topology update defines */ +#define TOPOLOGY_UPDATE_WIDTH_16BIT 1 +#define TOPOLOGY_UPDATE_WIDTH_32BIT 0 +#define TOPOLOGY_UPDATE_WIDTH_32BIT_MASK 0xf +#define TOPOLOGY_UPDATE_WIDTH_16BIT_MASK 0x3 + +#define TOPOLOGY_UPDATE_ECC_ON 1 +#define TOPOLOGY_UPDATE_ECC_OFF 0 +#define TOPOLOGY_UPDATE_ECC_OFFSET_PUP4 4 +#define TOPOLOGY_UPDATE_ECC_OFFSET_PUP3 3 + +/* + * 1. L2 filter should be set at binary header to 0xd000000, + * to avoid conflict with internal register IO. + * 2. U-Boot modifies internal registers base to 0xf100000, + * and than should update L2 filter accordingly to 0xf000000 (3.75 GB) + */ +/* temporary limit l2 filter to 3GiB (LSP issue) */ +#define L2_FILTER_FOR_MAX_MEMORY_SIZE 0xc0000000 +#define ADDRESS_FILTERING_END_REGISTER 0x8c04 + +#define SUB_VERSION 0 + +#endif /* _DDR3_HWS_HW_TRAINING_H */ |