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| author | Simon Glass <sjg@chromium.org> | 2016-01-21 19:43:38 -0700 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2016-01-21 20:42:34 -0700 |
| commit | 898d64395c6f8889fc9fd09a0a4dc6a6f018598f (patch) | |
| tree | 8d4c42a6cf349f0e86671623e4db83956d7e4930 /drivers/clk/clk_rk3036.c | |
| parent | f4adc9a50475e0c07ea5441e12e2f3caa54a76d3 (diff) | |
| download | blackbird-obmc-uboot-898d64395c6f8889fc9fd09a0a4dc6a6f018598f.tar.gz blackbird-obmc-uboot-898d64395c6f8889fc9fd09a0a4dc6a6f018598f.zip | |
rockchip: Use a separate clock ID for clocks
At present we use the same peripheral ID for clocks and pinctrl. While this
works it is probably better to use the device tree clock binding ID for
clocks. We can use the clk_get_by_index() function to find this.
Update the clock drivers and the code that uses them.
Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'drivers/clk/clk_rk3036.c')
| -rw-r--r-- | drivers/clk/clk_rk3036.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/drivers/clk/clk_rk3036.c b/drivers/clk/clk_rk3036.c index f650810250..dfecc24ece 100644 --- a/drivers/clk/clk_rk3036.c +++ b/drivers/clk/clk_rk3036.c @@ -13,8 +13,8 @@ #include <asm/arch/clock.h> #include <asm/arch/cru_rk3036.h> #include <asm/arch/hardware.h> -#include <asm/arch/periph.h> #include <dm/lists.h> +#include <dt-bindings/clock/rk3036-cru.h> DECLARE_GLOBAL_DATA_PTR; @@ -233,19 +233,19 @@ static uint32_t rkclk_pll_get_rate(struct rk3036_cru *cru, } static ulong rockchip_mmc_get_clk(struct rk3036_cru *cru, uint clk_general_rate, - enum periph_id periph) + int periph) { uint src_rate; uint div, mux; u32 con; switch (periph) { - case PERIPH_ID_EMMC: + case HCLK_EMMC: con = readl(&cru->cru_clksel_con[12]); mux = (con >> EMMC_PLL_SHIFT) & EMMC_PLL_MASK; div = (con >> EMMC_DIV_SHIFT) & EMMC_DIV_MASK; break; - case PERIPH_ID_SDCARD: + case HCLK_SDIO: con = readl(&cru->cru_clksel_con[12]); mux = (con >> MMC0_PLL_SHIFT) & MMC0_PLL_MASK; div = (con >> MMC0_DIV_SHIFT) & MMC0_DIV_MASK; @@ -259,7 +259,7 @@ static ulong rockchip_mmc_get_clk(struct rk3036_cru *cru, uint clk_general_rate, } static ulong rockchip_mmc_set_clk(struct rk3036_cru *cru, uint clk_general_rate, - enum periph_id periph, uint freq) + int periph, uint freq) { int src_clk_div; int mux; @@ -277,14 +277,14 @@ static ulong rockchip_mmc_set_clk(struct rk3036_cru *cru, uint clk_general_rate, } switch (periph) { - case PERIPH_ID_EMMC: + case HCLK_EMMC: rk_clrsetreg(&cru->cru_clksel_con[12], EMMC_PLL_MASK << EMMC_PLL_SHIFT | EMMC_DIV_MASK << EMMC_DIV_SHIFT, mux << EMMC_PLL_SHIFT | (src_clk_div - 1) << EMMC_DIV_SHIFT); break; - case PERIPH_ID_SDCARD: + case HCLK_SDIO: rk_clrsetreg(&cru->cru_clksel_con[11], MMC0_PLL_MASK << MMC0_PLL_SHIFT | MMC0_DIV_MASK << MMC0_DIV_SHIFT, @@ -320,7 +320,7 @@ static ulong rk3036_set_periph_rate(struct udevice *dev, int periph, ulong rate) ulong new_rate; switch (periph) { - case PERIPH_ID_EMMC: + case HCLK_EMMC: new_rate = rockchip_mmc_set_clk(priv->cru, clk_get_rate(dev), periph, rate); break; |
