Merge branch 'master' of git://git.denx.de/u-boot-arm

Bringing in the MMC tree means that CONFIG_BOUNCE_BUFFER needed to be
added to include/configs/exynos5-dt.h now.

Conflicts:
	include/configs/exynos5250-dt.h

Signed-off-by: Tom Rini <trini@ti.com>

4 files changed, 250 insertions, 15 deletions

diff --git a/doc/README.arm64 b/doc/README.arm64
new file mode 100644
index 0000000000..75586dbaa7
--- /dev/null
+++ b/doc/README.arm64
@@ -0,0 +1,46 @@
+U-boot for arm64
+
+Summary
+=======
+No hardware platform of arm64 is available now. The u-boot is
+simulated on Foundation Model and Fast Model for ARMv8.
+
+Notes
+=====
+
+1. Currenly, u-boot run at the highest exception level processor
+   supported and jump to EL2 or optionally EL1 before enter OS.
+
+2. U-boot for arm64 is compiled with AArch64-gcc. AArch64-gcc
+   use rela relocation format, a tool(tools/relocate-rela) by Scott Wood
+   is used to encode the initial addend of rela to u-boot.bin. After running,
+   the u-boot will be relocated to destination again.
+
+3. Fdt should be placed at a 2-megabyte boundary and within the first 512
+   megabytes from the start of the kernel image. So, fdt_high should be
+   defined specially.
+   Please reference linux/Documentation/arm64/booting.txt for detail.
+
+4. Spin-table is used to wake up secondary processors. One location
+   (or per processor location) is defined to hold the kernel entry point
+   for secondary processors. It must be ensured that the location is
+   accessible and zero immediately after secondary processor
+   enter slave_cpu branch execution in start.S. The location address
+   is encoded in cpu node of DTS. Linux kernel store the entry point
+   of secondary processors to it and send event to wakeup secondary
+   processors.
+   Please reference linux/Documentation/arm64/booting.txt for detail.
+
+5. Generic board is supported.
+
+6. CONFIG_ARM64 instead of CONFIG_ARMV8 is used to distinguish aarch64 and
+   aarch32 specific codes.
+
+Contributor
+===========
+   Tom Rini       <trini@ti.com>
+   Scott Wood     <scottwood@freescale.com>
+   York Sun       <yorksun@freescale.com>
+   Simon Glass    <sjg@chromium.org>
+   Sharma Bhupesh <bhupesh.sharma@freescale.com>
+   Rob Herring    <robherring2@gmail.com>
diff --git a/doc/README.imx6 b/doc/README.imx6
index 513a06ee86..437af2fd9a 100644
--- a/doc/README.imx6
+++ b/doc/README.imx6
@@ -8,3 +8,79 @@ SoC.
 
 1.1 MAC Address: It is stored in fuse bank 4, with the 32 lsbs in word 2 and the
     16 msbs in word 3.
+
+Example:
+
+For reading the MAC address fuses on a MX6Q:
+
+- The MAC address is stored in two fuse addresses (the fuse addresses are
+described in the Fusemap Descriptions table from the mx6q Reference Manual):
+
+0x620[31:0] - MAC_ADDR[31:0]
+0x630[15:0] - MAC_ADDR[47:32]
+
+In order to use the fuse API, we need to pass the bank and word values, which
+are calculated as below:
+
+Fuse address for the lower MAC address: 0x620
+Base address for the fuses: 0x400
+
+(0x620 - 0x400)/0x10 = 0x22 = 34 decimal
+
+As the fuses are arranged in banks of 8 words:
+
+34 / 8 = 4 and the remainder is 2, so in this case:
+
+bank = 4
+word = 2
+
+And the U-boot command would be:
+
+=> fuse read 4 2
+Reading bank 4:
+
+Word 0x00000002: 9f027772
+
+Doing the same for the upper MAC address:
+
+Fuse address for the upper MAC address: 0x630
+Base address for the fuses: 0x400
+
+(0x630 - 0x400)/0x10 = 0x23 = 35 decimal
+
+As the fuses are arranged in banks of 8 words:
+
+35 / 8 = 4 and the remainder is 3, so in this case:
+
+bank = 4
+word = 3
+
+And the U-boot command would be:
+
+=> fuse read 4 3
+Reading bank 4:
+
+Word 0x00000003: 00000004
+
+,which matches the ethaddr value:
+=> echo ${ethaddr}
+00:04:9f:02:77:72
+
+Some other useful hints:
+
+- The 'bank' and 'word' numbers can be easily obtained from the mx6 Reference
+Manual. For the mx6quad case, please check the "46.5 OCOTP Memory Map/Register
+Definition" from the "i.MX 6Dual/6Quad Applications Processor Reference Manual,
+Rev. 1, 04/2013" document. For example, for the MAC fuses we have:
+
+Address:
+21B_C620	Value of OTP Bank4 Word2 (MAC Address)(OCOTP_MAC0)
+
+21B_C630	Value of OTP Bank4 Word3 (MAC Address)(OCOTP_MAC1)
+
+- The command '=> fuse read 4 2 2' reads the whole MAC addresses at once:
+
+=> fuse read 4 2 2
+Reading bank 4:
+
+Word 0x00000002: 9f027772 00000004
diff --git a/doc/README.rmobile b/doc/README.rmobile
index 7ec63f13ce..4fbbcb3ef7 100644
--- a/doc/README.rmobile
+++ b/doc/README.rmobile
@@ -2,13 +2,15 @@ Summary
 =======
 
 This README is about U-Boot support for Renesas's ARM Cortex-A9 based RMOBILE[1]
-family of SoCs. Renesas's RMOBILE SoC family contains an ARM Cortex-A9.
+and R-Car[2]family of SoCs. Renesas's RMOBILE/R-Car SoC family contains an ARM
+Cortex-A9.
 
 Currently the following boards are supported:
 
-* KMC KZM-A9-GT [2]
-
-* Atmark-Techno Armadillo-800-EVA [3]
+* KMC KZM-A9-GT [3]
+* Atmark-Techno Armadillo-800-EVA [4]
+* Renesas Electronics Lager
+* Renesas Electronics Koelsch
 
 Toolchain
 =========
@@ -17,7 +19,7 @@ ARM Cortex-A9 support ARM v7 instruction set (-march=armv7a).
 But currently we compile with -march=armv5 to allow more compilers to work.
 (For U-Boot code this has no performance impact.)
 Because there was no compiler which is supporting armv7a not much before.
-Currently, ELDK[4], Linaro[5], CodeSourcey[6] and Emdebian[7] supports -march=armv7a
+Currently, ELDK[5], Linaro[6], CodeSourcey[7] and Emdebian[8] supports -march=armv7a
 and you can get.
 
 Build
@@ -25,13 +27,26 @@ Build
 
 * KZM-A9-GT
 
-make kzm9g_config
-make
+  make kzm9g_config
+  make
 
 * Armadillo-800-EVA
 
-make armadillo-800eva_config
-make
+  make armadillo-800eva_config
+  make
+
+  Note: Armadillo-800-EVA's U-Boot supports booting from SDcard only.
+        Please see "B.2 Appendix B Boot Specifications" in hardware manual.
+
+* Lager
+
+  make lager_config
+  make
+
+* Koelsch
+
+  make koelsch_config
+  make
 
 Links
 =====
@@ -40,26 +55,30 @@ Links
 
 http://am.renesas.com/products/soc/assp/mobile/r_mobile/index.jsp
 
-[2] KZM-A9-GT
+[2] Renesas R-Car:
+
+http://am.renesas.com/products/soc/assp/automotive/index.jsp
+
+[3] KZM-A9-GT
 
 http://www.kmckk.co.jp/kzma9-gt/index.html
 
-[3] Armadillo-800-EVA
+[4] Armadillo-800-EVA
 
 http://armadillo.atmark-techno.com/armadillo-800-EVA
 
-[4] ELDK
+[5] ELDK
 
 http://www.denx.de/wiki/view/ELDK-5/WebHome#Section_1.6.
 
-[5] Linaro
+[6] Linaro
 
 http://www.linaro.org/downloads/
 
-[6] CodeSourcey
+[7] CodeSourcey
 
 http://www.mentor.com/embedded-software/codesourcery
 
-[7] Emdebian
+[8] Emdebian
 
 http://www.emdebian.org/crosstools.html
diff --git a/doc/README.zynq b/doc/README.zynq
new file mode 100644
index 0000000000..043c970140
--- /dev/null
+++ b/doc/README.zynq
@@ -0,0 +1,94 @@
+#
+# Xilinx ZYNQ U-Boot
+#
+# (C) Copyright 2013 Xilinx, Inc.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+1. About this
+
+This document describes the information about Xilinx Zynq U-Boot -
+like supported boards, ML status and TODO list.
+
+2. Zynq boards
+
+Xilinx Zynq-7000 All Programmable SoCs enable extensive system level
+differentiation, integration, and flexibility through hardware, software,
+and I/O programmability.
+
+* zc70x
+  - zc702 (single qspi, gem0, mmc) [1]
+  - zc706 (dual parallel qspi, gem0, mmc) [2]
+* zed (single qspi, gem0, mmc) [3]
+* microzed (single qspi, gem0, mmc) [4]
+* zc770
+  - zc770-xm010 (single qspi, gem0, mmc)
+  - zc770-xm011 (8 or 16 bit nand)
+  - zc770-xm012 (nor)
+  - zc770-xm013 (dual parallel qspi, gem1)
+
+3. Building
+
+ # Configure for zc70x board
+   $ make zynq_zc70x_config
+     Configuring for zynq_zc70x board...
+
+ # Building default dts for zc702 board
+   $ make
+
+ # Building specified dts for zc706 board
+   $ make DEVICE_TREE=zynq-zc706
+
+4. Bootmode
+
+Zynq has a facility to read the bootmode from the slcr bootmode register
+once user is setting through jumpers on the board - see page no:1546 on [5]
+
+All possible bootmode values are defined in Table 6-2:Boot_Mode MIO Pins
+on [5].
+
+board_late_init() will read the bootmode values using slcr bootmode register
+at runtime and assign the modeboot variable to specific bootmode string which
+is intern used in autoboot.
+
+SLCR bootmode register Bit[3:0] values
+#define ZYNQ_BM_NOR		0x02
+#define ZYNQ_BM_SD		0x05
+#define ZYNQ_BM_JTAG		0x0
+
+"modeboot" variable can assign any of "norboot", "sdboot" or "jtagboot"
+bootmode strings at runtime.
+
+5. Mainline status
+
+- Added basic board configurations support.
+- Added zynq u-boot bsp code - arch/arm/cpu/armv7/zynq
+- Added zynq boards named - zc70x, zed, microzed, zc770_xm010, zc770_xm012, zc770_xm013
+- Added zynq drivers:
+  serial - drivers/serial/serial_zynq.c
+  net - drivers/net/zynq_gem.c
+  mmc - drivers/mmc/zynq_sdhci.c
+  mmc - drivers/mmc/zynq_sdhci.c
+  spi-  drivers/spi/zynq_spi.c
+  i2c - drivers/i2c/zynq_i2c.c
+- Done proper cleanups on board configurations
+- Added basic FDT support for zynq boards
+- d-cache support for zynq_gem.c
+
+6. TODO
+
+- Add zynq boards support - zc770_xm011
+- Add zynq qspi controller driver
+- Add zynq nand controller driver
+- Add FDT support on individual drivers
+
+[1] http://www.xilinx.com/products/boards-and-kits/EK-Z7-ZC702-G.htm
+[2] http://www.xilinx.com/products/boards-and-kits/EK-Z7-ZC706-G.htm
+[3] http://zedboard.org/product/zedboard
+[4] http://zedboard.org/product/microzed
+[5] http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf
+
+--
+Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
+Sun Dec 15 14:52:41 IST 2013