x86: ivybridge: Add early LPC init so that serial works

The PCH (Platform Controller Hub) includes an LPC (Low Pin Count) device
which provides a serial port. This is accessible on Chromebooks, so enable
it early in the boot process.

Signed-off-by: Simon Glass <sjg@chromium.org>

1 files changed, 23 insertions, 0 deletions

diff --git a/doc/device-tree-bindings/misc/intel-lpc.txt b/doc/device-tree-bindings/misc/intel-lpc.txt
new file mode 100644
index 0000000000..7e1b389237
--- /dev/null
+++ b/doc/device-tree-bindings/misc/intel-lpc.txt
@@ -0,0 +1,23 @@
+Intel LPC Device Binding
+========================
+
+The device tree node which describes the operation of the Intel Low Pin
+Count device is as follows:
+
+Required properties :
+- compatible = "intel,lpc"
+- gen-dec : Specifies the values for the gen-dec registers. Up to four cell
+   pairs can be provided - the first of each pair is the base address and
+   the second is the size. These are written into the GENx_DEC registers of
+   the LPC device
+
+
+Example
+-------
+
+lpc {
+	compatible = "intel,lpc";
+	#address-cells = <1>;
+	#size-cells = <1>;
+	gen-dec = <0x800 0xfc 0x900 0xfc>;
+};