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authorPaul Gortmaker <paul.gortmaker@windriver.com>2007-01-16 11:38:14 -0500
committerKim Phillips <kim.phillips@freescale.com>2007-03-02 11:05:53 -0600
commit91e25769771c1164ed63ffca0add49f934ae3343 (patch)
treec76a51da2252d0362745e443a37059e965201036 /cpu/mpc83xx
parent05031db456ab227f3e3752f37b9b812b65bb83ad (diff)
downloadblackbird-obmc-uboot-91e25769771c1164ed63ffca0add49f934ae3343.tar.gz
blackbird-obmc-uboot-91e25769771c1164ed63ffca0add49f934ae3343.zip
mpc83xx: U-Boot support for Wind River SBC8349
I've redone the SBC8349 support to match git-current, which incorporates all the MPC834x updates from Freescale since the 1.1.6 release, including the DDR changes. I've kept all the SBC8349 files as parallel as possible to the MPC8349EMDS ones for ease of maintenance and to allow for easy inspection of what was changed to support this board. Hence the SBC8349 U-Boot has FDT support and everything else that the MPC8349EMDS has. Fortunately the Freescale updates added support for boards using CS0, but I had to change spd_sdram.c to allow for board specific settings for the sdram_clk_cntl (it is/was hard coded to zero, and that remains the default if the board doesn't specify a value.) Hopefully this should be mergeable as-is and require no whitespace cleanups or similar, but if something doesn't measure up then let me know and I'll fix it. Thanks, Paul.
Diffstat (limited to 'cpu/mpc83xx')
-rw-r--r--cpu/mpc83xx/spd_sdram.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c
index 0d93f2e1ea..108328a7f4 100644
--- a/cpu/mpc83xx/spd_sdram.c
+++ b/cpu/mpc83xx/spd_sdram.c
@@ -440,10 +440,14 @@ long int spd_sdram()
ddr->sdram_interval = ((refresh_clk & 0x3fff) << 16) | 0x100;
debug("DDR:sdram_interval=0x%08x\n", ddr->sdram_interval);
+#ifdef CFG_DDR_SDRAM_CLK_CNTL /* Optional platform specific value */
+ ddr->sdram_clk_cntl = CFG_DDR_SDRAM_CLK_CNTL;
+#else
/* SS_EN = 0, source synchronous disable
* CLK_ADJST = 0, MCK/MCK# is launched aligned with addr/cmd
*/
ddr->sdram_clk_cntl = 0x00000000;
+#endif
debug("DDR:sdram_clk_cntl=0x%08x\n", ddr->sdram_clk_cntl);
asm("sync;isync");
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