m68k: Move cpu/$CPU to arch/m68k/cpu/$CPU

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>

8 files changed, 0 insertions, 1843 deletions

diff --git a/cpu/mcf52x2/Makefile b/cpu/mcf52x2/Makefile
deleted file mode 100644
index 937cdd0584..0000000000
--- a/cpu/mcf52x2/Makefile
+++ /dev/null
@@ -1,49 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-# CFLAGS += -DET_DEBUG
-
-LIB	= $(obj)lib$(CPU).a
-
-START	= start.o
-COBJS	= interrupts.o cpu.o speed.o cpu_init.o
-
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-START	:= $(addprefix $(obj),$(START))
-
-all:	$(obj).depend $(START) $(LIB)
-
-$(LIB):	$(OBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS)
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/cpu/mcf52x2/config.mk b/cpu/mcf52x2/config.mk
deleted file mode 100644
index 52751be3e4..0000000000
--- a/cpu/mcf52x2/config.mk
+++ /dev/null
@@ -1,64 +0,0 @@
-#
-# (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
-#
-# (C) Copyright 2000-2004
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
-
-cfg=$(shell grep configs $(OBJTREE)/include/config.h | sed 's/.*<\(configs.*\)>/\1/')
-is5208:=$(shell grep CONFIG_M5208 $(TOPDIR)/include/$(cfg))
-is5249:=$(shell grep CONFIG_M5249 $(TOPDIR)/include/$(cfg))
-is5253:=$(shell grep CONFIG_M5253 $(TOPDIR)/include/$(cfg))
-is5271:=$(shell grep CONFIG_M5271 $(TOPDIR)/include/$(cfg))
-is5272:=$(shell grep CONFIG_M5272 $(TOPDIR)/include/$(cfg))
-is5275:=$(shell grep CONFIG_M5275 $(TOPDIR)/include/$(cfg))
-is5282:=$(shell grep CONFIG_M5282 $(TOPDIR)/include/$(cfg))
-
-
-ifneq ($(findstring 4.1,$(shell $(CC) --version)),4.1)
-
-ifneq (,$(findstring CONFIG_M5208,$(is5208)))
-PLATFORM_CPPFLAGS += -mcpu=5208
-endif
-ifneq (,$(findstring CONFIG_M5249,$(is5249)))
-PLATFORM_CPPFLAGS += -mcpu=5249
-endif
-ifneq (,$(findstring CONFIG_M5253,$(is5253)))
-PLATFORM_CPPFLAGS += -mcpu=5253
-endif
-ifneq (,$(findstring CONFIG_M5271,$(is5271)))
-PLATFORM_CPPFLAGS += -mcpu=5271
-endif
-ifneq (,$(findstring CONFIG_M5272,$(is5272)))
-PLATFORM_CPPFLAGS += -mcpu=5272
-endif
-ifneq (,$(findstring CONFIG_M5275,$(is5275)))
-PLATFORM_CPPFLAGS += -mcpu=5275
-endif
-ifneq (,$(findstring CONFIG_M5282,$(is5282)))
-PLATFORM_CPPFLAGS += -mcpu=5282
-endif
-
-else
-PLATFORM_CPPFLAGS += -m5307
-endif
diff --git a/cpu/mcf52x2/cpu.c b/cpu/mcf52x2/cpu.c
deleted file mode 100644
index c4c5d50604..0000000000
--- a/cpu/mcf52x2/cpu.c
+++ /dev/null
@@ -1,408 +0,0 @@
-/*
- * (C) Copyright 2003
- * Josef Baumgartner <josef.baumgartner@telex.de>
- *
- * MCF5282 additionals
- * (C) Copyright 2005
- * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
- *
- * MCF5275 additions
- * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <watchdog.h>
-#include <command.h>
-#include <asm/immap.h>
-#include <netdev.h>
-#include "cpu.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef	CONFIG_M5208
-int do_reset(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
-{
-	volatile rcm_t *rcm = (rcm_t *)(MMAP_RCM);
-
-	udelay(1000);
-
-	rcm->rcr = RCM_RCR_SOFTRST;
-
-	/* we don't return! */
-	return 0;
-};
-
-int checkcpu(void)
-{
-	char buf1[32], buf2[32];
-
-	printf("CPU:   Freescale Coldfire MCF5208\n"
-	       "       CPU CLK %s MHz BUS CLK %s MHz\n",
-	       strmhz(buf1, gd->cpu_clk),
-	       strmhz(buf2, gd->bus_clk));
-	return 0;
-};
-
-#if defined(CONFIG_WATCHDOG)
-/* Called by macro WATCHDOG_RESET */
-void watchdog_reset(void)
-{
-	volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
-	wdt->sr = 0x5555;
-	wdt->sr = 0xAAAA;
-}
-
-int watchdog_disable(void)
-{
-	volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
-
-	wdt->sr = 0x5555; /* reset watchdog counteDECLARE_GLOBAL_DATA_PTR;
-r */
-	wdt->sr = 0xAAAA;
-	wdt->cr = 0;	/* disable watchdog timer */
-
-	puts("WATCHDOG:disabled\n");
-	return (0);
-}
-
-int watchdog_init(void)
-{
-	volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
-
-	wdt->cr = 0;	/* disable watchdog */
-
-	/* set timeout and enable watchdog */
-	wdt->mr =
-		((CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000)) - 1;
-	wdt->sr = 0x5555; /* reset watchdog counter */
-	wdt->sr = 0xAAAA;
-
-	puts("WATCHDOG:enabled\n");
-	return (0);
-}
-#endif				/* #ifdef CONFIG_WATCHDOG */
-#endif				/* #ifdef CONFIG_M5208 */
-
-#ifdef  CONFIG_M5271
-/*
- * Both MCF5270 and MCF5271 are members of the MPC5271 family. Try to
- * determine which one we are running on, based on the Chip Identification
- * Register (CIR).
- */
-int checkcpu(void)
-{
-	char buf[32];
-	unsigned short cir;	/* Chip Identification Register */
-	unsigned short pin;	/* Part identification number */
-	unsigned char prn;	/* Part revision number */
-	char *cpu_model;
-
-	cir = mbar_readShort(MCF_CCM_CIR);
-	pin = cir >> MCF_CCM_CIR_PIN_LEN;
-	prn = cir & MCF_CCM_CIR_PRN_MASK;
-
-	switch (pin) {
-	case MCF_CCM_CIR_PIN_MCF5270:
-		cpu_model = "5270";
-		break;
-	case MCF_CCM_CIR_PIN_MCF5271:
-		cpu_model = "5271";
-		break;
-	default:
-		cpu_model = NULL;
-		break;
-	}
-
-	if (cpu_model)
-		printf("CPU:   Freescale ColdFire MCF%s rev. %hu, at %s MHz\n",
-		       cpu_model, prn, strmhz(buf, CONFIG_SYS_CLK));
-	else
-		printf("CPU:   Unknown - Freescale ColdFire MCF5271 family"
-		       " (PIN: 0x%x) rev. %hu, at %s MHz\n",
-		       pin, prn, strmhz(buf, CONFIG_SYS_CLK));
-
-	return 0;
-}
-
-int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
-{
-	/* Call the board specific reset actions first. */
-	if(board_reset) {
-		board_reset();
-	}
-
-	mbar_writeByte(MCF_RCM_RCR,
-		       MCF_RCM_RCR_SOFTRST | MCF_RCM_RCR_FRCRSTOUT);
-	return 0;
-};
-
-#if defined(CONFIG_WATCHDOG)
-void watchdog_reset(void)
-{
-	mbar_writeShort(MCF_WTM_WSR, 0x5555);
-	mbar_writeShort(MCF_WTM_WSR, 0xAAAA);
-}
-
-int watchdog_disable(void)
-{
-	mbar_writeShort(MCF_WTM_WCR, 0);
-	return (0);
-}
-
-int watchdog_init(void)
-{
-	mbar_writeShort(MCF_WTM_WCR, MCF_WTM_WCR_EN);
-	return (0);
-}
-#endif				/* #ifdef CONFIG_WATCHDOG */
-
-#endif
-
-#ifdef	CONFIG_M5272
-int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
-{
-	volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
-
-	wdp->wdog_wrrr = 0;
-	udelay(1000);
-
-	/* enable watchdog, set timeout to 0 and wait */
-	wdp->wdog_wrrr = 1;
-	while (1) ;
-
-	/* we don't return! */
-	return 0;
-};
-
-int checkcpu(void)
-{
-	volatile sysctrl_t *sysctrl = (sysctrl_t *) (MMAP_CFG);
-	uchar msk;
-	char *suf;
-
-	puts("CPU:   ");
-	msk = (sysctrl->sc_dir > 28) & 0xf;
-	switch (msk) {
-	case 0x2:
-		suf = "1K75N";
-		break;
-	case 0x4:
-		suf = "3K75N";
-		break;
-	default:
-		suf = NULL;
-		printf("Freescale MCF5272 (Mask:%01x)\n", msk);
-		break;
-	}
-
-	if (suf)
-		printf("Freescale MCF5272 %s\n", suf);
-	return 0;
-};
-
-#if defined(CONFIG_WATCHDOG)
-/* Called by macro WATCHDOG_RESET */
-void watchdog_reset(void)
-{
-	volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
-	wdt->wdog_wcr = 0;
-}
-
-int watchdog_disable(void)
-{
-	volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
-
-	wdt->wdog_wcr = 0;	/* reset watchdog counter */
-	wdt->wdog_wirr = 0;	/* disable watchdog interrupt */
-	wdt->wdog_wrrr = 0;	/* disable watchdog timer */
-
-	puts("WATCHDOG:disabled\n");
-	return (0);
-}
-
-int watchdog_init(void)
-{
-	volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
-
-	wdt->wdog_wirr = 0;	/* disable watchdog interrupt */
-
-	/* set timeout and enable watchdog */
-	wdt->wdog_wrrr =
-	    ((CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000)) - 1;
-	wdt->wdog_wcr = 0;	/* reset watchdog counter */
-
-	puts("WATCHDOG:enabled\n");
-	return (0);
-}
-#endif				/* #ifdef CONFIG_WATCHDOG */
-
-#endif				/* #ifdef CONFIG_M5272 */
-
-#ifdef	CONFIG_M5275
-int do_reset(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
-{
-	volatile rcm_t *rcm = (rcm_t *)(MMAP_RCM);
-
-	udelay(1000);
-
-	rcm->rcr = RCM_RCR_SOFTRST;
-
-	/* we don't return! */
-	return 0;
-};
-
-int checkcpu(void)
-{
-	char buf[32];
-
-	printf("CPU:   Freescale Coldfire MCF5275 at %s MHz\n",
-			strmhz(buf, CONFIG_SYS_CLK));
-	return 0;
-};
-
-
-#if defined(CONFIG_WATCHDOG)
-/* Called by macro WATCHDOG_RESET */
-void watchdog_reset(void)
-{
-	volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
-	wdt->wsr = 0x5555;
-	wdt->wsr = 0xAAAA;
-}
-
-int watchdog_disable(void)
-{
-	volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
-
-	wdt->wsr = 0x5555; /* reset watchdog counter */
-	wdt->wsr = 0xAAAA;
-	wdt->wcr = 0;	/* disable watchdog timer */
-
-	puts("WATCHDOG:disabled\n");
-	return (0);
-}
-
-int watchdog_init(void)
-{
-	volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
-
-	wdt->wcr = 0;	/* disable watchdog */
-
-	/* set timeout and enable watchdog */
-	wdt->wmr =
-		((CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000)) - 1;
-	wdt->wsr = 0x5555; /* reset watchdog counter */
-	wdt->wsr = 0xAAAA;
-
-	puts("WATCHDOG:enabled\n");
-	return (0);
-}
-#endif				/* #ifdef CONFIG_WATCHDOG */
-
-#endif				/* #ifdef CONFIG_M5275 */
-
-#ifdef	CONFIG_M5282
-int checkcpu(void)
-{
-	unsigned char resetsource = MCFRESET_RSR;
-
-	printf("CPU:   Freescale Coldfire MCF5282 (PIN: %2.2x REV: %2.2x)\n",
-	       MCFCCM_CIR >> 8, MCFCCM_CIR & MCFCCM_CIR_PRN_MASK);
-	printf("Reset:%s%s%s%s%s%s%s\n",
-	       (resetsource & MCFRESET_RSR_LOL) ? " Loss of Lock" : "",
-	       (resetsource & MCFRESET_RSR_LOC) ? " Loss of Clock" : "",
-	       (resetsource & MCFRESET_RSR_EXT) ? " External" : "",
-	       (resetsource & MCFRESET_RSR_POR) ? " Power On" : "",
-	       (resetsource & MCFRESET_RSR_WDR) ? " Watchdog" : "",
-	       (resetsource & MCFRESET_RSR_SOFT) ? " Software" : "",
-	       (resetsource & MCFRESET_RSR_LVD) ? " Low Voltage" : "");
-	return 0;
-}
-
-int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
-{
-	MCFRESET_RCR = MCFRESET_RCR_SOFTRST;
-	return 0;
-};
-#endif
-
-#ifdef CONFIG_M5249
-int checkcpu(void)
-{
-	char buf[32];
-
-	printf("CPU:   Freescale Coldfire MCF5249 at %s MHz\n",
-	       strmhz(buf, CONFIG_SYS_CLK));
-	return 0;
-}
-
-int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
-{
-	/* enable watchdog, set timeout to 0 and wait */
-	mbar_writeByte(MCFSIM_SYPCR, 0xc0);
-	while (1) ;
-
-	/* we don't return! */
-	return 0;
-};
-#endif
-
-#ifdef CONFIG_M5253
-int checkcpu(void)
-{
-	char buf[32];
-
-	unsigned char resetsource = mbar_readLong(SIM_RSR);
-	printf("CPU:   Freescale Coldfire MCF5253 at %s MHz\n",
-	       strmhz(buf, CONFIG_SYS_CLK));
-
-	if ((resetsource & SIM_RSR_HRST) || (resetsource & SIM_RSR_SWTR)) {
-		printf("Reset:%s%s\n",
-		       (resetsource & SIM_RSR_HRST) ? " Hardware/ System Reset"
-		       : "",
-		       (resetsource & SIM_RSR_SWTR) ? " Software Watchdog" :
-		       "");
-	}
-	return 0;
-}
-
-int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
-{
-	/* enable watchdog, set timeout to 0 and wait */
-	mbar_writeByte(SIM_SYPCR, 0xc0);
-	while (1) ;
-
-	/* we don't return! */
-	return 0;
-};
-#endif
-
-#if defined(CONFIG_MCFFEC)
-/* Default initializations for MCFFEC controllers.  To override,
- * create a board-specific function called:
- * 	int board_eth_init(bd_t *bis)
- */
-
-int cpu_eth_init(bd_t *bis)
-{
-	return mcffec_initialize(bis);
-}
-#endif
diff --git a/cpu/mcf52x2/cpu.h b/cpu/mcf52x2/cpu.h
deleted file mode 100644
index c1227eb1ce..0000000000
--- a/cpu/mcf52x2/cpu.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- *  cpu.h
- *
- *  Copyright (c) 2009 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#ifndef _CPU_H_
-#define _CPU_H_
-
-#include <command.h>
-
-/* Use this to create board specific reset functions */
-void board_reset(void) __attribute__((__weak__));
-
-#endif /* _CPU_H_ */
diff --git a/cpu/mcf52x2/cpu_init.c b/cpu/mcf52x2/cpu_init.c
deleted file mode 100644
index 170bbfc356..0000000000
--- a/cpu/mcf52x2/cpu_init.c
+++ /dev/null
@@ -1,747 +0,0 @@
-/*
- * (C) Copyright 2003
- * Josef Baumgartner <josef.baumgartner@telex.de>
- *
- * MCF5282 additionals
- * (C) Copyright 2005
- * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
- * (c) Copyright 2010
- * Arcturus Networks Inc. <www.arcturusnetworks.com>
- *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
- * Hayden Fraser (Hayden.Fraser@freescale.com)
- *
- * MCF5275 additions
- * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <watchdog.h>
-#include <asm/immap.h>
-
-#if defined(CONFIG_CMD_NET)
-#include <config.h>
-#include <net.h>
-#include <asm/fec.h>
-#endif
-
-#ifndef CONFIG_M5272
-/* Only 5272 Flexbus chipselect is different from the rest */
-void init_fbcs(void)
-{
-	volatile fbcs_t *fbcs = (fbcs_t *) (MMAP_FBCS);
-
-#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
-     && defined(CONFIG_SYS_CS0_CTRL))
-	fbcs->csar0 = CONFIG_SYS_CS0_BASE;
-	fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
-	fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
-#else
-#warning "Chip Select 0 are not initialized/used"
-#endif
-#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
-     && defined(CONFIG_SYS_CS1_CTRL))
-	fbcs->csar1 = CONFIG_SYS_CS1_BASE;
-	fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
-	fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
-#endif
-#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
-     && defined(CONFIG_SYS_CS2_CTRL))
-	fbcs->csar2 = CONFIG_SYS_CS2_BASE;
-	fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
-	fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
-#endif
-#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
-     && defined(CONFIG_SYS_CS3_CTRL))
-	fbcs->csar3 = CONFIG_SYS_CS3_BASE;
-	fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
-	fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
-#endif
-#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
-     && defined(CONFIG_SYS_CS4_CTRL))
-	fbcs->csar4 = CONFIG_SYS_CS4_BASE;
-	fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
-	fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
-#endif
-#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
-     && defined(CONFIG_SYS_CS5_CTRL))
-	fbcs->csar5 = CONFIG_SYS_CS5_BASE;
-	fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
-	fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
-#endif
-#if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) \
-     && defined(CONFIG_SYS_CS6_CTRL))
-	fbcs->csar6 = CONFIG_SYS_CS6_BASE;
-	fbcs->cscr6 = CONFIG_SYS_CS6_CTRL;
-	fbcs->csmr6 = CONFIG_SYS_CS6_MASK;
-#endif
-#if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) \
-     && defined(CONFIG_SYS_CS7_CTRL))
-	fbcs->csar7 = CONFIG_SYS_CS7_BASE;
-	fbcs->cscr7 = CONFIG_SYS_CS7_CTRL;
-	fbcs->csmr7 = CONFIG_SYS_CS7_MASK;
-#endif
-}
-#endif
-
-#if defined(CONFIG_M5208)
-void cpu_init_f(void)
-{
-	volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
-
-#ifndef CONFIG_WATCHDOG
-	volatile wdog_t *wdg = (wdog_t *) MMAP_WDOG;
-
-	/* Disable the watchdog if we aren't using it */
-	wdg->cr = 0;
-#endif
-
-	scm1->mpr = 0x77777777;
-	scm1->pacra = 0;
-	scm1->pacrb = 0;
-	scm1->pacrc = 0;
-	scm1->pacrd = 0;
-	scm1->pacre = 0;
-	scm1->pacrf = 0;
-
-	/* FlexBus Chipselect */
-	init_fbcs();
-
-	icache_enable();
-}
-
-/* initialize higher level parts of CPU like timers */
-int cpu_init_r(void)
-{
-	return (0);
-}
-
-void uart_port_conf(int port)
-{
-	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-
-	/* Setup Ports: */
-	switch (port) {
-	case 0:
-		gpio->par_uart &= GPIO_PAR_UART0_UNMASK;
-		gpio->par_uart |= (GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
-		break;
-	case 1:
-		gpio->par_uart &= GPIO_PAR_UART0_UNMASK;
-		gpio->par_uart |= (GPIO_PAR_UART_U1TXD | GPIO_PAR_UART_U1RXD);
-		break;
-	case 2:
-#ifdef CONFIG_SYS_UART2_PRI_GPIO
-		gpio->par_timer &=
-		    (GPIO_PAR_TMR_TIN0_UNMASK | GPIO_PAR_TMR_TIN1_UNMASK);
-		gpio->par_timer |=
-		    (GPIO_PAR_TMR_TIN0_U2TXD | GPIO_PAR_TMR_TIN1_U2RXD);
-#endif
-#ifdef CONFIG_SYS_UART2_ALT1_GPIO
-		gpio->par_feci2c &=
-		    (GPIO_PAR_FECI2C_MDC_UNMASK | GPIO_PAR_FECI2C_MDIO_UNMASK);
-		gpio->par_feci2c |=
-		    (GPIO_PAR_FECI2C_MDC_U2TXD | GPIO_PAR_FECI2C_MDIO_U2RXD);
-#endif
-#ifdef CONFIG_SYS_UART2_ALT1_GPIO
-		gpio->par_feci2c &=
-		    (GPIO_PAR_FECI2C_SDA_UNMASK | GPIO_PAR_FECI2C_SCL_UNMASK);
-		gpio->par_feci2c |=
-		    (GPIO_PAR_FECI2C_SDA_U2TXD | GPIO_PAR_FECI2C_SCL_U2RXD);
-#endif
-		break;
-	}
-}
-
-#if defined(CONFIG_CMD_NET)
-int fecpin_setclear(struct eth_device *dev, int setclear)
-{
-	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-
-	if (setclear) {
-		gpio->par_fec |=
-		    GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC;
-		gpio->par_feci2c |=
-		    GPIO_PAR_FECI2C_MDC_MDC | GPIO_PAR_FECI2C_MDIO_MDIO;
-	} else {
-		gpio->par_fec &=
-		    (GPIO_PAR_FEC_7W_UNMASK & GPIO_PAR_FEC_MII_UNMASK);
-		gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII_UNMASK;
-	}
-	return 0;
-}
-#endif				/* CONFIG_CMD_NET */
-#endif				/* CONFIG_M5208 */
-
-#if defined(CONFIG_M5253)
-/*
- * Breath some life into the CPU...
- *
- * Set up the memory map,
- * initialize a bunch of registers,
- * initialize the UPM's
- */
-void cpu_init_f(void)
-{
-	mbar_writeByte(MCFSIM_MPARK, 0x40);	/* 5249 Internal Core takes priority over DMA */
-	mbar_writeByte(MCFSIM_SYPCR, 0x00);
-	mbar_writeByte(MCFSIM_SWIVR, 0x0f);
-	mbar_writeByte(MCFSIM_SWSR, 0x00);
-	mbar_writeByte(MCFSIM_SWDICR, 0x00);
-	mbar_writeByte(MCFSIM_TIMER1ICR, 0x00);
-	mbar_writeByte(MCFSIM_TIMER2ICR, 0x88);
-	mbar_writeByte(MCFSIM_I2CICR, 0x00);
-	mbar_writeByte(MCFSIM_UART1ICR, 0x00);
-	mbar_writeByte(MCFSIM_UART2ICR, 0x00);
-	mbar_writeByte(MCFSIM_ICR6, 0x00);
-	mbar_writeByte(MCFSIM_ICR7, 0x00);
-	mbar_writeByte(MCFSIM_ICR8, 0x00);
-	mbar_writeByte(MCFSIM_ICR9, 0x00);
-	mbar_writeByte(MCFSIM_QSPIICR, 0x00);
-
-	mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080);
-	mbar2_writeByte(MCFSIM_INTBASE, 0x40);	/* Base interrupts at 64 */
-	mbar2_writeByte(MCFSIM_SPURVEC, 0x00);
-
-	/*mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); */ /* Enable a 1 cycle pre-drive cycle on CS1 */
-
-	/* FlexBus Chipselect */
-	init_fbcs();
-
-#ifdef CONFIG_FSL_I2C
-	CONFIG_SYS_I2C_PINMUX_REG =
-	    CONFIG_SYS_I2C_PINMUX_REG & CONFIG_SYS_I2C_PINMUX_CLR;
-	CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
-#ifdef CONFIG_SYS_I2C2_OFFSET
-	CONFIG_SYS_I2C2_PINMUX_REG &= CONFIG_SYS_I2C2_PINMUX_CLR;
-	CONFIG_SYS_I2C2_PINMUX_REG |= CONFIG_SYS_I2C2_PINMUX_SET;
-#endif
-#endif
-
-	/* enable instruction cache now */
-	icache_enable();
-}
-
-/*initialize higher level parts of CPU like timers */
-int cpu_init_r(void)
-{
-	return (0);
-}
-
-void uart_port_conf(int port)
-{
-	volatile u32 *par = (u32 *) MMAP_PAR;
-
-	/* Setup Ports: */
-	switch (port) {
-	case 1:
-		*par &= 0xFFE7FFFF;
-		*par |= 0x00180000;
-		break;
-	case 2:
-		*par &= 0xFFFFFFFC;
-		*par &= 0x00000003;
-		break;
-	}
-}
-#endif				/* #if defined(CONFIG_M5253) */
-
-#if defined(CONFIG_M5271)
-void cpu_init_f(void)
-{
-#ifndef CONFIG_WATCHDOG
-	/* Disable the watchdog if we aren't using it */
-	mbar_writeShort(MCF_WTM_WCR, 0);
-#endif
-
-	/* FlexBus Chipselect */
-	init_fbcs();
-
-#ifdef CONFIG_SYS_MCF_SYNCR
-	/* Set clockspeed according to board header file */
-	mbar_writeLong(MCF_FMPLL_SYNCR, CONFIG_SYS_MCF_SYNCR);
-#else
-	/* Set clockspeed to 100MHz */
-	mbar_writeLong(MCF_FMPLL_SYNCR,
-			MCF_FMPLL_SYNCR_MFD(0) | MCF_FMPLL_SYNCR_RFD(0));
-#endif
-	while (!mbar_readByte(MCF_FMPLL_SYNSR) & MCF_FMPLL_SYNSR_LOCK) ;
-}
-
-/*
- * initialize higher level parts of CPU like timers
- */
-int cpu_init_r(void)
-{
-	return (0);
-}
-
-void uart_port_conf(int port)
-{
-	u16 temp;
-
-	/* Setup Ports: */
-	switch (port) {
-	case 0:
-		temp = mbar_readShort(MCF_GPIO_PAR_UART) & 0xFFF3;
-		temp |= (MCF_GPIO_PAR_UART_U0TXD | MCF_GPIO_PAR_UART_U0RXD);
-		mbar_writeShort(MCF_GPIO_PAR_UART, temp);
-		break;
-	case 1:
-		temp = mbar_readShort(MCF_GPIO_PAR_UART) & 0xF0FF;
-		temp |= (MCF_GPIO_PAR_UART_U1RXD_UART1 | MCF_GPIO_PAR_UART_U1TXD_UART1);
-		mbar_writeShort(MCF_GPIO_PAR_UART, temp);
-		break;
-	case 2:
-		temp = mbar_readShort(MCF_GPIO_PAR_UART) & 0xCFFF;
-		temp |= (0x3000);
-		mbar_writeShort(MCF_GPIO_PAR_UART, temp);
-		break;
-	}
-}
-
-#if defined(CONFIG_CMD_NET)
-int fecpin_setclear(struct eth_device *dev, int setclear)
-{
-	if (setclear) {
-		/* Enable Ethernet pins */
-		mbar_writeByte(MCF_GPIO_PAR_FECI2C,
-			       (mbar_readByte(MCF_GPIO_PAR_FECI2C) | 0xF0));
-	} else {
-	}
-
-	return 0;
-}
-#endif				/* CONFIG_CMD_NET */
-#endif
-
-#if defined(CONFIG_M5272)
-/*
- * Breath some life into the CPU...
- *
- * Set up the memory map,
- * initialize a bunch of registers,
- * initialize the UPM's
- */
-void cpu_init_f(void)
-{
-	/* if we come from RAM we assume the CPU is
-	 * already initialized.
-	 */
-#ifndef CONFIG_MONITOR_IS_IN_RAM
-	volatile sysctrl_t *sysctrl = (sysctrl_t *) (CONFIG_SYS_MBAR);
-	volatile gpio_t *gpio = (gpio_t *) (MMAP_GPIO);
-	volatile csctrl_t *csctrl = (csctrl_t *) (MMAP_FBCS);
-
-	sysctrl->sc_scr = CONFIG_SYS_SCR;
-	sysctrl->sc_spr = CONFIG_SYS_SPR;
-
-	/* Setup Ports: */
-	gpio->gpio_pacnt = CONFIG_SYS_PACNT;
-	gpio->gpio_paddr = CONFIG_SYS_PADDR;
-	gpio->gpio_padat = CONFIG_SYS_PADAT;
-	gpio->gpio_pbcnt = CONFIG_SYS_PBCNT;
-	gpio->gpio_pbddr = CONFIG_SYS_PBDDR;
-	gpio->gpio_pbdat = CONFIG_SYS_PBDAT;
-	gpio->gpio_pdcnt = CONFIG_SYS_PDCNT;
-
-	/* Memory Controller: */
-	csctrl->cs_br0 = CONFIG_SYS_BR0_PRELIM;
-	csctrl->cs_or0 = CONFIG_SYS_OR0_PRELIM;
-
-#if (defined(CONFIG_SYS_OR1_PRELIM) && defined(CONFIG_SYS_BR1_PRELIM))
-	csctrl->cs_br1 = CONFIG_SYS_BR1_PRELIM;
-	csctrl->cs_or1 = CONFIG_SYS_OR1_PRELIM;
-#endif
-
-#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
-	csctrl->cs_br2 = CONFIG_SYS_BR2_PRELIM;
-	csctrl->cs_or2 = CONFIG_SYS_OR2_PRELIM;
-#endif
-
-#if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM)
-	csctrl->cs_br3 = CONFIG_SYS_BR3_PRELIM;
-	csctrl->cs_or3 = CONFIG_SYS_OR3_PRELIM;
-#endif
-
-#if defined(CONFIG_SYS_OR4_PRELIM) && defined(CONFIG_SYS_BR4_PRELIM)
-	csctrl->cs_br4 = CONFIG_SYS_BR4_PRELIM;
-	csctrl->cs_or4 = CONFIG_SYS_OR4_PRELIM;
-#endif
-
-#if defined(CONFIG_SYS_OR5_PRELIM) && defined(CONFIG_SYS_BR5_PRELIM)
-	csctrl->cs_br5 = CONFIG_SYS_BR5_PRELIM;
-	csctrl->cs_or5 = CONFIG_SYS_OR5_PRELIM;
-#endif
-
-#if defined(CONFIG_SYS_OR6_PRELIM) && defined(CONFIG_SYS_BR6_PRELIM)
-	csctrl->cs_br6 = CONFIG_SYS_BR6_PRELIM;
-	csctrl->cs_or6 = CONFIG_SYS_OR6_PRELIM;
-#endif
-
-#if defined(CONFIG_SYS_OR7_PRELIM) && defined(CONFIG_SYS_BR7_PRELIM)
-	csctrl->cs_br7 = CONFIG_SYS_BR7_PRELIM;
-	csctrl->cs_or7 = CONFIG_SYS_OR7_PRELIM;
-#endif
-
-#endif				/* #ifndef CONFIG_MONITOR_IS_IN_RAM */
-
-	/* enable instruction cache now */
-	icache_enable();
-
-}
-
-/*
- * initialize higher level parts of CPU like timers
- */
-int cpu_init_r(void)
-{
-	return (0);
-}
-
-void uart_port_conf(int port)
-{
-	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-
-	/* Setup Ports: */
-	switch (port) {
-	case 0:
-		gpio->gpio_pbcnt &= ~(GPIO_PBCNT_PB0MSK | GPIO_PBCNT_PB1MSK);
-		gpio->gpio_pbcnt |= (GPIO_PBCNT_URT0_TXD | GPIO_PBCNT_URT0_RXD);
-		break;
-	case 1:
-		gpio->gpio_pdcnt &= ~(GPIO_PDCNT_PD1MSK | GPIO_PDCNT_PD4MSK);
-		gpio->gpio_pdcnt |= (GPIO_PDCNT_URT1_RXD | GPIO_PDCNT_URT1_TXD);
-		break;
-	}
-}
-
-#if defined(CONFIG_CMD_NET)
-int fecpin_setclear(struct eth_device *dev, int setclear)
-{
-	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-
-	if (setclear) {
-		gpio->gpio_pbcnt |= GPIO_PBCNT_E_MDC | GPIO_PBCNT_E_RXER |
-				    GPIO_PBCNT_E_RXD1 | GPIO_PBCNT_E_RXD2 |
-				    GPIO_PBCNT_E_RXD3 | GPIO_PBCNT_E_TXD1 |
-				    GPIO_PBCNT_E_TXD2 | GPIO_PBCNT_E_TXD3;
-	} else {
-	}
-	return 0;
-}
-#endif				/* CONFIG_CMD_NET */
-#endif				/* #if defined(CONFIG_M5272) */
-
-#if defined(CONFIG_M5275)
-
-/*
- * Breathe some life into the CPU...
- *
- * Set up the memory map,
- * initialize a bunch of registers,
- * initialize the UPM's
- */
-void cpu_init_f(void)
-{
-	/*
-	 * if we come from RAM we assume the CPU is
-	 * already initialized.
-	 */
-
-#ifndef CONFIG_MONITOR_IS_IN_RAM
-	volatile wdog_t *wdog_reg = (wdog_t *) (MMAP_WDOG);
-	volatile gpio_t *gpio_reg = (gpio_t *) (MMAP_GPIO);
-
-	/* Kill watchdog so we can initialize the PLL */
-	wdog_reg->wcr = 0;
-
-	/* FlexBus Chipselect */
-	init_fbcs();
-#endif				/* #ifndef CONFIG_MONITOR_IS_IN_RAM */
-
-#ifdef CONFIG_FSL_I2C
-	CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR;
-	CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
-#endif
-
-	/* enable instruction cache now */
-	icache_enable();
-}
-
-/*
- * initialize higher level parts of CPU like timers
- */
-int cpu_init_r(void)
-{
-	return (0);
-}
-
-void uart_port_conf(int port)
-{
-	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-
-	/* Setup Ports: */
-	switch (port) {
-	case 0:
-		gpio->par_uart &= ~UART0_ENABLE_MASK;
-		gpio->par_uart |= UART0_ENABLE_MASK;
-		break;
-	case 1:
-		gpio->par_uart &= ~UART1_ENABLE_MASK;
-		gpio->par_uart |= UART1_ENABLE_MASK;
-		break;
-	case 2:
-		gpio->par_uart &= ~UART2_ENABLE_MASK;
-		gpio->par_uart |= UART2_ENABLE_MASK;
-		break;
-	}
-}
-
-#if defined(CONFIG_CMD_NET)
-int fecpin_setclear(struct eth_device *dev, int setclear)
-{
-	struct fec_info_s *info = (struct fec_info_s *) dev->priv;
-	volatile gpio_t *gpio = (gpio_t *)MMAP_GPIO;
-
-	if (setclear) {
-		/* Enable Ethernet pins */
-		if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
-			gpio->par_feci2c |= 0x0F00;
-			gpio->par_fec0hl |= 0xC0;
-		} else {
-			gpio->par_feci2c |= 0x00A0;
-			gpio->par_fec1hl |= 0xC0;
-		}
-	} else {
-		if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
-			gpio->par_feci2c &= ~0x0F00;
-			gpio->par_fec0hl &= ~0xC0;
-		} else {
-			gpio->par_feci2c &= ~0x00A0;
-			gpio->par_fec1hl &= ~0xC0;
-		}
-	}
-
-	return 0;
-}
-#endif				/* CONFIG_CMD_NET */
-#endif				/* #if defined(CONFIG_M5275) */
-
-#if defined(CONFIG_M5282)
-/*
- * Breath some life into the CPU...
- *
- * Set up the memory map,
- * initialize a bunch of registers,
- * initialize the UPM's
- */
-void cpu_init_f(void)
-{
-#ifndef CONFIG_WATCHDOG
-	/* disable watchdog if we aren't using it */
-	MCFWTM_WCR = 0;
-#endif
-
-#ifndef CONFIG_MONITOR_IS_IN_RAM
-	/* Set speed /PLL */
-	MCFCLOCK_SYNCR =
-	    MCFCLOCK_SYNCR_MFD(CONFIG_SYS_MFD) |
-	    MCFCLOCK_SYNCR_RFD(CONFIG_SYS_RFD);
-	while (!(MCFCLOCK_SYNSR & MCFCLOCK_SYNSR_LOCK)) ;
-
-	MCFGPIO_PBCDPAR = 0xc0;
-
-	/* Set up the GPIO ports */
-#ifdef CONFIG_SYS_PEPAR
-	MCFGPIO_PEPAR = CONFIG_SYS_PEPAR;
-#endif
-#ifdef	CONFIG_SYS_PFPAR
-	MCFGPIO_PFPAR = CONFIG_SYS_PFPAR;
-#endif
-#ifdef CONFIG_SYS_PJPAR
-	MCFGPIO_PJPAR = CONFIG_SYS_PJPAR;
-#endif
-#ifdef CONFIG_SYS_PSDPAR
-	MCFGPIO_PSDPAR = CONFIG_SYS_PSDPAR;
-#endif
-#ifdef CONFIG_SYS_PASPAR
-	MCFGPIO_PASPAR = CONFIG_SYS_PASPAR;
-#endif
-#ifdef CONFIG_SYS_PEHLPAR
-	MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR;
-#endif
-#ifdef CONFIG_SYS_PQSPAR
-	MCFGPIO_PQSPAR = CONFIG_SYS_PQSPAR;
-#endif
-#ifdef CONFIG_SYS_PTCPAR
-	MCFGPIO_PTCPAR = CONFIG_SYS_PTCPAR;
-#endif
-#if defined(CONFIG_SYS_PORTTC)
-	MCFGPIO_PORTTC = CONFIG_SYS_PORTTC;
-#endif
-#if defined(CONFIG_SYS_DDRTC)
-	MCFGPIO_DDRTC  = CONFIG_SYS_DDRTC;
-#endif
-#ifdef CONFIG_SYS_PTDPAR
-	MCFGPIO_PTDPAR = CONFIG_SYS_PTDPAR;
-#endif
-#ifdef CONFIG_SYS_PUAPAR
-	MCFGPIO_PUAPAR = CONFIG_SYS_PUAPAR;
-#endif
-
-#if defined(CONFIG_SYS_DDRD)
-	MCFGPIO_DDRD = CONFIG_SYS_DDRD;
-#endif
-#ifdef CONFIG_SYS_DDRUA
-	MCFGPIO_DDRUA = CONFIG_SYS_DDRUA;
-#endif
-
-	/* FlexBus Chipselect */
-	init_fbcs();
-
-#endif				/* CONFIG_MONITOR_IS_IN_RAM */
-
-	/* defer enabling cache until boot (see do_go) */
-	/* icache_enable(); */
-}
-
-/*
- * initialize higher level parts of CPU like timers
- */
-int cpu_init_r(void)
-{
-	return (0);
-}
-
-void uart_port_conf(int port)
-{
-	/* Setup Ports: */
-	switch (port) {
-	case 0:
-		MCFGPIO_PUAPAR &= 0xFc;
-		MCFGPIO_PUAPAR |= 0x03;
-		break;
-	case 1:
-		MCFGPIO_PUAPAR &= 0xF3;
-		MCFGPIO_PUAPAR |= 0x0C;
-		break;
-	case 2:
-		MCFGPIO_PASPAR &= 0xFF0F;
-		MCFGPIO_PASPAR |= 0x00A0;
-		break;
-	}
-}
-
-#if defined(CONFIG_CMD_NET)
-int fecpin_setclear(struct eth_device *dev, int setclear)
-{
-	if (setclear) {
-		MCFGPIO_PASPAR |= 0x0F00;
-		MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR;
-	} else {
-		MCFGPIO_PASPAR &= 0xF0FF;
-		MCFGPIO_PEHLPAR &= ~CONFIG_SYS_PEHLPAR;
-	}
-	return 0;
-}
-#endif			/* CONFIG_CMD_NET */
-#endif
-
-#if defined(CONFIG_M5249)
-/*
- * Breath some life into the CPU...
- *
- * Set up the memory map,
- * initialize a bunch of registers,
- * initialize the UPM's
- */
-void cpu_init_f(void)
-{
-	/*
-	 *  NOTE: by setting the GPIO_FUNCTION registers, we ensure that the UART pins
-	 *        (UART0: gpio 30,27, UART1: gpio 31, 28) will be used as UART pins
-	 *        which is their primary function.
-	 *        ~Jeremy
-	 */
-	mbar2_writeLong(MCFSIM_GPIO_FUNC, CONFIG_SYS_GPIO_FUNC);
-	mbar2_writeLong(MCFSIM_GPIO1_FUNC, CONFIG_SYS_GPIO1_FUNC);
-	mbar2_writeLong(MCFSIM_GPIO_EN, CONFIG_SYS_GPIO_EN);
-	mbar2_writeLong(MCFSIM_GPIO1_EN, CONFIG_SYS_GPIO1_EN);
-	mbar2_writeLong(MCFSIM_GPIO_OUT, CONFIG_SYS_GPIO_OUT);
-	mbar2_writeLong(MCFSIM_GPIO1_OUT, CONFIG_SYS_GPIO1_OUT);
-
-	/*
-	 *  dBug Compliance:
-	 *    You can verify these values by using dBug's 'ird'
-	 *    (Internal Register Display) command
-	 *    ~Jeremy
-	 *
-	 */
-	mbar_writeByte(MCFSIM_MPARK, 0x30);	/* 5249 Internal Core takes priority over DMA */
-	mbar_writeByte(MCFSIM_SYPCR, 0x00);
-	mbar_writeByte(MCFSIM_SWIVR, 0x0f);
-	mbar_writeByte(MCFSIM_SWSR, 0x00);
-	mbar_writeLong(MCFSIM_IMR, 0xfffffbff);
-	mbar_writeByte(MCFSIM_SWDICR, 0x00);
-	mbar_writeByte(MCFSIM_TIMER1ICR, 0x00);
-	mbar_writeByte(MCFSIM_TIMER2ICR, 0x88);
-	mbar_writeByte(MCFSIM_I2CICR, 0x00);
-	mbar_writeByte(MCFSIM_UART1ICR, 0x00);
-	mbar_writeByte(MCFSIM_UART2ICR, 0x00);
-	mbar_writeByte(MCFSIM_ICR6, 0x00);
-	mbar_writeByte(MCFSIM_ICR7, 0x00);
-	mbar_writeByte(MCFSIM_ICR8, 0x00);
-	mbar_writeByte(MCFSIM_ICR9, 0x00);
-	mbar_writeByte(MCFSIM_QSPIICR, 0x00);
-
-	mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080);
-	mbar2_writeByte(MCFSIM_INTBASE, 0x40);	/* Base interrupts at 64 */
-	mbar2_writeByte(MCFSIM_SPURVEC, 0x00);
-	mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020);	/* Enable a 1 cycle pre-drive cycle on CS1 */
-
-	/* Setup interrupt priorities for gpio7 */
-	/* mbar2_writeLong(MCFSIM_INTLEV5, 0x70000000); */
-
-	/* IDE Config registers */
-	mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020);
-	mbar2_writeLong(MCFSIM_IDECONFIG2, 0x00000000);
-
-	/* FlexBus Chipselect */
-	init_fbcs();
-
-	/* enable instruction cache now */
-	icache_enable();
-}
-
-/*
- * initialize higher level parts of CPU like timers
- */
-int cpu_init_r(void)
-{
-	return (0);
-}
-
-void uart_port_conf(int port)
-{
-}
-#endif				/* #if defined(CONFIG_M5249) */
diff --git a/cpu/mcf52x2/interrupts.c b/cpu/mcf52x2/interrupts.c
deleted file mode 100644
index dff8c6aa88..0000000000
--- a/cpu/mcf52x2/interrupts.c
+++ /dev/null
@@ -1,107 +0,0 @@
-/*
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
- * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <watchdog.h>
-#include <asm/processor.h>
-#include <asm/immap.h>
-
-#ifdef	CONFIG_M5272
-int interrupt_init(void)
-{
-	volatile intctrl_t *intp = (intctrl_t *) (MMAP_INTC);
-
-	/* disable all external interrupts */
-	intp->int_icr1 = 0x88888888;
-	intp->int_icr2 = 0x88888888;
-	intp->int_icr3 = 0x88888888;
-	intp->int_icr4 = 0x88888888;
-	intp->int_pitr = 0x00000000;
-	/* initialize vector register */
-	intp->int_pivr = 0x40;
-
-	enable_interrupts();
-
-	return 0;
-}
-
-#if defined(CONFIG_MCFTMR)
-void dtimer_intr_setup(void)
-{
-	volatile intctrl_t *intp = (intctrl_t *) (CONFIG_SYS_INTR_BASE);
-
-	intp->int_icr1 &= ~INT_ICR1_TMR3MASK;
-	intp->int_icr1 |= CONFIG_SYS_TMRINTR_PRI;
-}
-#endif				/* CONFIG_MCFTMR */
-#endif				/* CONFIG_M5272 */
-
-#if defined(CONFIG_M5208) || defined(CONFIG_M5282) || \
-    defined(CONFIG_M5271) || defined(CONFIG_M5275)
-int interrupt_init(void)
-{
-	volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
-
-	/* Make sure all interrupts are disabled */
-#if defined(CONFIG_M5208)
-	intp->imrl0 = 0xFFFFFFFF;
-	intp->imrh0 = 0xFFFFFFFF;
-#else
-	intp->imrl0 |= 0x1;
-#endif
-
-	enable_interrupts();
-	return 0;
-}
-
-#if defined(CONFIG_MCFTMR)
-void dtimer_intr_setup(void)
-{
-	volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
-
-	intp->icr0[CONFIG_SYS_TMRINTR_NO] = CONFIG_SYS_TMRINTR_PRI;
-	intp->imrl0 &= 0xFFFFFFFE;
-	intp->imrl0 &= ~CONFIG_SYS_TMRINTR_MASK;
-}
-#endif				/* CONFIG_MCFTMR */
-#endif				/* CONFIG_M5282 | CONFIG_M5271 | CONFIG_M5275 */
-
-#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
-int interrupt_init(void)
-{
-	enable_interrupts();
-
-	return 0;
-}
-
-#if defined(CONFIG_MCFTMR)
-void dtimer_intr_setup(void)
-{
-	mbar_writeLong(MCFSIM_IMR, mbar_readLong(MCFSIM_IMR) & ~0x00000400);
-	mbar_writeByte(MCFSIM_TIMER2ICR, CONFIG_SYS_TMRINTR_PRI);
-}
-#endif				/* CONFIG_MCFTMR */
-#endif				/* CONFIG_M5249 || CONFIG_M5253 */
diff --git a/cpu/mcf52x2/speed.c b/cpu/mcf52x2/speed.c
deleted file mode 100644
index b485e1cccc..0000000000
--- a/cpu/mcf52x2/speed.c
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * (C) Copyright 2003
- * Josef Baumgartner <josef.baumgartner@telex.de>
- *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
- * Hayden Fraser (Hayden.Fraser@freescale.com)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/immap.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* get_clocks() fills in gd->cpu_clock and gd->bus_clk */
-int get_clocks (void)
-{
-#if defined(CONFIG_M5208)
-	volatile pll_t *pll = (pll_t *) MMAP_PLL;
-
-	pll->odr = CONFIG_SYS_PLL_ODR;
-	pll->fdr = CONFIG_SYS_PLL_FDR;
-#endif
-
-#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
-	volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR);
-	unsigned long pllcr;
-
-#ifndef CONFIG_SYS_PLL_BYPASS
-
-#ifdef CONFIG_M5249
-	/* Setup the PLL to run at the specified speed */
-#ifdef CONFIG_SYS_FAST_CLK
-	pllcr = 0x925a3100;	/* ~140MHz clock (PLL bypass = 0) */
-#else
-	pllcr = 0x135a4140;	/* ~72MHz clock (PLL bypass = 0) */
-#endif
-#endif				/* CONFIG_M5249 */
-
-#ifdef CONFIG_M5253
-	pllcr = CONFIG_SYS_PLLCR;
-#endif				/* CONFIG_M5253 */
-
-	cpll = cpll & 0xfffffffe;	/* Set PLL bypass mode = 0 (PSTCLK = crystal) */
-	mbar2_writeLong(MCFSIM_PLLCR, cpll);	/* Set the PLL to bypass mode (PSTCLK = crystal) */
-	mbar2_writeLong(MCFSIM_PLLCR, pllcr);	/* set the clock speed */
-	pllcr ^= 0x00000001;	/* Set pll bypass to 1 */
-	mbar2_writeLong(MCFSIM_PLLCR, pllcr);	/* Start locking (pll bypass = 1) */
-	udelay(0x20);		/* Wait for a lock ... */
-#endif				/* #ifndef CONFIG_SYS_PLL_BYPASS */
-
-#endif				/* CONFIG_M5249 || CONFIG_M5253 */
-
-#if defined(CONFIG_M5275)
-	volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL);
-
-	/* Setup PLL */
-	pll->syncr = 0x01080000;
-	while (!(pll->synsr & FMPLL_SYNSR_LOCK))
-		;
-	pll->syncr = 0x01000000;
-	while (!(pll->synsr & FMPLL_SYNSR_LOCK))
-		;
-#endif
-
-	gd->cpu_clk = CONFIG_SYS_CLK;
-#if defined(CONFIG_M5208) || defined(CONFIG_M5249) || defined(CONFIG_M5253) || \
-    defined(CONFIG_M5271) || defined(CONFIG_M5275)
-	gd->bus_clk = gd->cpu_clk / 2;
-#else
-	gd->bus_clk = gd->cpu_clk;
-#endif
-
-#ifdef CONFIG_FSL_I2C
-	gd->i2c1_clk = gd->bus_clk;
-#ifdef CONFIG_SYS_I2C2_OFFSET
-	gd->i2c2_clk = gd->bus_clk;
-#endif
-#endif
-
-	return (0);
-}
diff --git a/cpu/mcf52x2/start.S b/cpu/mcf52x2/start.S
deleted file mode 100644
index 9ef206aa0f..0000000000
--- a/cpu/mcf52x2/start.S
+++ /dev/null
@@ -1,335 +0,0 @@
-/*
- * Copyright (C) 2003	Josef Baumgartner <josef.baumgartner@telex.de>
- * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <timestamp.h>
-#include "version.h"
-#include <asm/cache.h>
-
-#ifndef	 CONFIG_IDENT_STRING
-#define	 CONFIG_IDENT_STRING ""
-#endif
-
-#define _START	_start
-#define _FAULT	_fault
-
-
-#define SAVE_ALL						\
-	move.w	#0x2700,%sr;		/* disable intrs */	\
-	subl	#60,%sp;		/* space for 15 regs */ \
-	moveml	%d0-%d7/%a0-%a6,%sp@;				\
-
-#define RESTORE_ALL						\
-	moveml	%sp@,%d0-%d7/%a0-%a6;				\
-	addl	#60,%sp;		/* space for 15 regs */ \
-	rte
-
-/* If we come from a pre-loader we don't need an initial exception
- * table.
- */
-#if !defined(CONFIG_MONITOR_IS_IN_RAM)
-
-.text
-/*
- *	Vector table. This is used for initial platform startup.
- *	These vectors are to catch any un-intended traps.
- */
-_vectors:
-
-.long	0x00000000		/* Flash offset is 0 until we setup CS0 */
-#if defined(CONFIG_M5282) && (TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
-.long	_start - TEXT_BASE
-#else
-.long	_START
-#endif
-
-.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-
-.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-
-.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-
-.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-.long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
-
-#endif
-
-	.text
-
-
-#if defined(CONFIG_SYS_INT_FLASH_BASE) && \
-    (defined(CONFIG_M5282) || defined(CONFIG_M5281))
-	#if (TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
-		.long	0x55AA55AA,0xAA55AA55 /* CFM Backdoorkey */
-		.long	0xFFFFFFFF /* all sectors protected */
-		.long	0x00000000 /* supervisor/User restriction */
-		.long	0x00000000 /* programm/data space restriction */
-		.long	0x00000000 /* Flash security */
-	#endif
-#endif
-	.globl	_start
-_start:
-	nop
-	nop
-	move.w #0x2700,%sr
-
-#if defined(CONFIG_M5208)
-	/* Initialize RAMBAR: locate SRAM and validate it */
-	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
-	movec	%d0, %RAMBAR1
-#endif
-
-#if defined(CONFIG_M5272) || defined(CONFIG_M5249) || defined(CONFIG_M5253)
-	move.l	#(CONFIG_SYS_MBAR + 1), %d0		/* set MBAR address + valid flag */
-	move.c	%d0, %MBAR
-
-	/*** The 5249 has MBAR2 as well ***/
-#ifdef CONFIG_SYS_MBAR2
-	move.l	#(CONFIG_SYS_MBAR2 + 1), %d0	        /* Get MBAR2 address */
-	movec	%d0, #0xc0e		        /* Set MBAR2 */
-#endif
-
-	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + 1), %d0
-	movec	%d0, %RAMBAR0
-#endif /* CONFIG_M5272 || CONFIG_M5249 || CONFIG_M5253 */
-
-#if defined(CONFIG_M5282) || defined(CONFIG_M5271)
-	/* Initialize IPSBAR */
-	move.l	#(CONFIG_SYS_MBAR + 1), %d0		/* set IPSBAR address + valid flag */
-	move.l	%d0, 0x40000000
-
-	/* Initialize RAMBAR1: locate SRAM and validate it */
-	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + 0x21), %d0
-	movec	%d0, %RAMBAR1
-
-#if defined(CONFIG_M5282)
-#if (TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
-	/* Setup code in SRAM to initialize FLASHBAR, if start from internal Flash */
-
-	move.l #(_flashbar_setup-CONFIG_SYS_INT_FLASH_BASE), %a0
-	move.l #(_flashbar_setup_end-CONFIG_SYS_INT_FLASH_BASE), %a1
-	move.l #(CONFIG_SYS_INIT_RAM_ADDR), %a2
-_copy_flash:
-	move.l (%a0)+, (%a2)+
-	cmp.l %a0, %a1
-	bgt.s _copy_flash
-	jmp CONFIG_SYS_INIT_RAM_ADDR
-
-_flashbar_setup:
-	/* Initialize FLASHBAR: locate internal Flash and validate it */
-	move.l	#(CONFIG_SYS_INT_FLASH_BASE + CONFIG_SYS_INT_FLASH_ENABLE), %d0
-	movec	%d0, %FLASHBAR
-	jmp _after_flashbar_copy.L	/* Force jump to absolute address */
-_flashbar_setup_end:
-	nop
-_after_flashbar_copy:
-#else
-	/* Setup code to initialize FLASHBAR, if start from external Memory */
-	move.l	#(CONFIG_SYS_INT_FLASH_BASE + CONFIG_SYS_INT_FLASH_ENABLE), %d0
-	movec	%d0, %FLASHBAR
-#endif /* (TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE) */
-
-#endif
-#endif
-	/* if we come from a pre-loader we have no exception table and
-	 * therefore no VBR to set
-	 */
-#if !defined(CONFIG_MONITOR_IS_IN_RAM)
-#if defined(CONFIG_M5282) && (TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
-	move.l	#CONFIG_SYS_INT_FLASH_BASE, %d0
-#else
-	move.l	#CONFIG_SYS_FLASH_BASE, %d0
-#endif
-	movec	%d0, %VBR
-#endif
-
-#ifdef CONFIG_M5275
-	/* Initialize IPSBAR */
-	move.l	#(CONFIG_SYS_MBAR + 1), %d0		/* set IPSBAR address + valid flag */
-	move.l	%d0, 0x40000000
-/*	movec	%d0, %MBAR */
-
-	/* Initialize RAMBAR: locate SRAM and validate it */
-	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + 0x21), %d0
-	movec	%d0, %RAMBAR1
-#endif
-
-	/* initialize general use internal ram */
-	move.l #0, %d0
-	move.l #(ICACHE_STATUS), %a1	/* icache */
-	move.l #(DCACHE_STATUS), %a2	/* icache */
-	move.l %d0, (%a1)
-	move.l %d0, (%a2)
-
-	/* set stackpointer to end of internal ram to get some stackspace for the first c-code */
-	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
-	clr.l %sp@-
-
-	move.l #__got_start, %a5		/* put relocation table address to a5 */
-
-	bsr cpu_init_f				/* run low-level CPU init code (from flash) */
-	bsr board_init_f			/* run low-level board init code (from flash) */
-
-	/* board_init_f() does not return */
-
-/*------------------------------------------------------------------------------*/
-
-/*
- * void relocate_code (addr_sp, gd, addr_moni)
- *
- * This "function" does not return, instead it continues in RAM
- * after relocating the monitor code.
- *
- * r3 = dest
- * r4 = src
- * r5 = length in bytes
- * r6 = cachelinesize
- */
-	.globl	relocate_code
-relocate_code:
-	link.w %a6,#0
-	move.l 8(%a6), %sp		/* set new stack pointer */
-
-	move.l 12(%a6), %d0		/* Save copy of Global Data pointer */
-	move.l 16(%a6), %a0		/* Save copy of Destination Address */
-
-	move.l #CONFIG_SYS_MONITOR_BASE, %a1
-	move.l #__init_end, %a2
-	move.l %a0, %a3
-	/* copy the code to RAM */
-1:
-	move.l (%a1)+, (%a3)+
-	cmp.l  %a1,%a2
-	bgt.s	 1b
-
-/*
- * We are done. Do not return, instead branch to second part of board
- * initialization, now running from RAM.
- */
-	move.l	%a0, %a1
-	add.l	#(in_ram - CONFIG_SYS_MONITOR_BASE), %a1
-	jmp	(%a1)
-
-in_ram:
-
-clear_bss:
-	/*
-	 * Now clear BSS segment
-	 */
-	move.l	%a0, %a1
-	add.l	#(_sbss - CONFIG_SYS_MONITOR_BASE),%a1
-	move.l	%a0, %d1
-	add.l	#(_ebss - CONFIG_SYS_MONITOR_BASE),%d1
-6:
-	clr.l	(%a1)+
-	cmp.l	%a1,%d1
-	bgt.s	6b
-
-	/*
-	 * fix got table in RAM
-	 */
-	move.l	%a0, %a1
-	add.l	#(__got_start - CONFIG_SYS_MONITOR_BASE),%a1
-	move.l	%a1,%a5		/* * fix got pointer register a5 */
-
-	move.l	%a0, %a2
-	add.l	#(__got_end - CONFIG_SYS_MONITOR_BASE),%a2
-
-7:
-	move.l	(%a1),%d1
-	sub.l	#_start,%d1
-	add.l	%a0,%d1
-	move.l	%d1,(%a1)+
-	cmp.l	%a2, %a1
-	bne	7b
-
-	/* calculate relative jump to board_init_r in ram */
-	move.l %a0, %a1
-	add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
-
-	/* set parameters for board_init_r */
-	move.l %a0,-(%sp)		/* dest_addr */
-	move.l %d0,-(%sp)		/* gd */
-#if defined(DEBUG) && (TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE) && \
-    defined(CONFIG_SYS_HALT_BEFOR_RAM_JUMP)
-	halt
-#endif
-	jsr	(%a1)
-
-/*------------------------------------------------------------------------------*/
-/* exception code */
-	.globl _fault
-_fault:
-	jmp _fault
-
-	.globl	_exc_handler
-_exc_handler:
-	SAVE_ALL
-	movel	%sp,%sp@-
-	bsr exc_handler
-	addql	#4,%sp
-	RESTORE_ALL
-
-	.globl	_int_handler
-_int_handler:
-	SAVE_ALL
-	movel	%sp,%sp@-
-	bsr int_handler
-	addql	#4,%sp
-	RESTORE_ALL
-
-/*------------------------------------------------------------------------------*/
-
-	.globl	version_string
-version_string:
-	.ascii U_BOOT_VERSION
-	.ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
-	.ascii CONFIG_IDENT_STRING, "\0"
-	.align 4