diff options
| author | Wolfgang Denk <wd@denx.de> | 2012-05-20 21:31:26 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2012-05-20 21:31:26 +0200 |
| commit | ee3a55fdf00b54391e406217e53674449e70d78b (patch) | |
| tree | 0c7edb3ba668e5a215c42e8b1429cc3f394351b2 /board | |
| parent | 6bc337fb13003a9a949dfb2713e308fb97faae8a (diff) | |
| parent | 2ca4a209a5b961ad1be8782c68dabe326d77dfaf (diff) | |
| download | blackbird-obmc-uboot-ee3a55fdf00b54391e406217e53674449e70d78b.tar.gz blackbird-obmc-uboot-ee3a55fdf00b54391e406217e53674449e70d78b.zip | |
Merge branch 'master' of git://git.denx.de/u-boot-arm
* 'master' of git://git.denx.de/u-boot-arm: (167 commits)
OMAP4/5: Change omap4_sdp, omap4_panda, omap5_evm maintainer
ARM: omap3: Add CONFIG_SPL_BOARD_INIT for CONFIG_SPL_MMC_SUPPORT
ARM: omap3: Set SPL stack size to 8KB, image to 54KB.
arm, omap3: fix warm reset serial output on OMAP36xx/AM/DM37xx
OMAP4: Set fdt_high for OMAP4 devices to enable booting with Device Tree
omap4: do not enable auxiliary cores
omap4: do not enable fs-usb module
omap4: panda: disable uart2 pads during boot
igep00x0: change mpurate from 500 to auto
igep00x0: enable the use of a plain text file
tegra2: trivially enable 13 mhz crystal frequency
tegra: Enable keyboard for Seaboard
tegra: Switch on console mux and use environment for console
tegra: Add tegra keyboard driver
tegra: fdt: Add keyboard definitions for Seaboard
tegra: fdt: Add keyboard controller definition
tegra: Add keyboard support to funcmux
input: Add support for keyboard matrix decoding from an fdt
input: Add generic keyboard input handler
input: Add linux/input.h for key code support
fdt: Add fdtdec functions to read byte array
tegra: Enable LP0 on Seaboard
tegra: fdt: Add EMC data for Tegra2 Seaboard
tegra: i2c: Add function to find DVC bus
fdt: tegra: Add EMC node to device tree
tegra: Add EMC settings for Seaboard
tegra: Turn off power detect in board init
tegra: Set up warmboot code on Nvidia boards
tegra: Setup PMC scratch info from ap20 setup
tegra: Add warmboot implementation
tegra: Set up PMU for Nvidia boards
tegra: Add PMU to manage power supplies
tegra: Add EMC support for optimal memory timings
tegra: Add header file for APB_MISC register
tegra: Add tegra_get_chip_type() to detect SKU
tegra: Add flow, gp_padctl, fuse, sdram headers
tegra: Add crypto library for warmboot code
tegra: Add functions to access low-level Osc/PLL details
tegra: Move ap20.h header into arch location
Add AES crypto library
i2c: Add TPS6586X driver
Add abs() macro to return absolute value
fdt: Add function to return next compatible subnode
fdt: Add function to locate an array in the device tree
i.MX28: Avoid redefining serial_put[cs]()
i.MX28: Check if WP detection is implemented at all
i.MX28: Add battery boot components to SPL
i.MX28: Reorder battery status functions in SPL
i.MX28: Add LRADC init to i.MX28 SPL
i.MX28: Add LRADC register definitions
i.MX28: Shut down the LCD controller before reset
i.MX28: Add LCDIF register definitions
i.MX28: Implement boot pads sampling and reporting
i.MX28: Improve passing of data from SPL to U-Boot
M28EVK: Add SD update command
M28EVK: Implement support for new board V2.0
FEC: Abstract out register setup
MX5: PAD_CTL_DRV_VOT_LOW and PAD_CTL_DRV_VOT_HIGH exchanged
i.MX28: Add delay after CPU bypass is cleared
spi: mxs: Allow other chip selects to work
spi: mxs: Introduce spi_cs_is_valid()
mx53loco: Remove unneeded gpio_set_value()
mx53loco: Add CONFIG_REVISION_TAG
mx53loco: Turn on VUSB regulator
mx53loco: Add mc34708 support and set mx53 frequency at 1GHz
pmic: dialog: Avoid name conflicts
imx: Add u-boot.imx as target for ARM9 i.MX SOCs
i.MX2: Include asm/types.h in arch-mx25/imx-regs.h
imx: usb: There is no such register
i.MX25: usb: Set PORTSCx register
imx: nand: Support flash based BBT
i.MX25: This architecture has a GPIO4 too
i.MX25: esdhc: Add mxc_get_clock infrastructure
i.MX6: mx6q_sabrelite: add SATA bindings
i.MX6: add enable_sata_clock()
i.MX6: Add ANATOP regulator init
mx28evk: add NAND support
USB: ehci-mx6: Fix broken IO access
M28: Scan only first 512 MB of DRAM to avoid memory wraparound
Revert "i.MX28: Enable additional DRAM address bits"
M28: Enable FDT support
mx53loco: Add support for 1GHz operation for DA9053-based boards
mx53loco: Allow to print CPU information at a later stage
mx5: Add clock config interface
imx-common: Factor out get_ahb_clk()
i.MX6Q: mx6qsabrelite: Add keypress support to alter boot flow
mx31pdk: Allow booting a zImage kernel
mx6qarm2: Allow booting a zImage kernel
mx6qsabrelite: Allow booting a zImage kernel
mx28evk: Allow booting a zImage kernel
m28evk: Allow to booting a dt kernel
mx28evk: Allow to booting a dt kernel
mx6qsabrelite: No need to set the direction for GPIO3_23 again
pmic: Add support for the Dialog DA9053 PMIC
MX53: mx53loco: Add SATA support
MX53: Add support to ESG ima3 board
SATA: add driver for MX5 / MX6 SOCs
MX53: add function to set SATA clock to internal
SATA: check for return value from sata functions
MX5: Add definitions for SATA controller
NET: fec_mxc.c: Add a way to disable auto negotiation
Define UART4 and UART5 base addresses
EXYNOS: Change bits per pixel value proper for u-boot.
EXYNOS: support TRATS board display function
LCD: support S6E8AX0 amoled driver based on EXYNOS MIPI DSI
EXYNOS: support EXYNOS MIPI DSI interface driver.
EXYNOS: support EXYNOS framebuffer and FIMD display drivers.
LCD: add data structure for EXYNOS display driver
EXYNOS: add LCD and MIPI DSI clock interface.
EXYNOS: definitions of system resgister and power management registers.
SMDK5250: fix compiler warning
misc:pmic:samsung Convert TRATS target to use MAX8997 instead of MAX8998
misc:pmic:max8997 MAX8997 support for PMIC driver
TRATS: modify the trats's configuration
ARM: Exynos4: ADC: Universal_C210: Enable LDO4 power line for ADC measurement
EXYNOS: Rename exynos5_tzpc structure to exynos_tzpc
arm: ea20: Change macro from BOARD_LATE_INIT to CONFIG_BOARD_LATE_INIT
arm: cam_enc_4xx: Change macro from BOARD_LATE_INIT to CONFIG_BOARD_LATE_INIT
cm-t35: add I2C multi-bus support
include/configs: Remove CONFIG_SYS_64BIT_STRTOUL
include/configs: Remove CONFIG_SYS_64BIT_VSPRINTF
omap3: Introduce weak misc_init_r
omap730p2: Remove empty misc_init_r
omap5912osk: Remove empty misc_init_r
omap4+: Remove CONFIG_ARCH_CPU_INIT
omap4: Remove CONFIG_SYS_MMC_SET_DEV
OMAP3: pandora: drop console kernel argument
OMAP3: pandora: revise GPIO configuration
...
Diffstat (limited to 'board')
56 files changed, 2326 insertions, 369 deletions
diff --git a/board/cloudengines/pogo_e02/Makefile b/board/cloudengines/pogo_e02/Makefile new file mode 100644 index 0000000000..7f866910e8 --- /dev/null +++ b/board/cloudengines/pogo_e02/Makefile @@ -0,0 +1,43 @@ +# +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar <prafulla@marvell.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; If not, see <http://www.gnu.org/licenses/>. +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := pogo_e02.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/cloudengines/pogo_e02/kwbimage.cfg b/board/cloudengines/pogo_e02/kwbimage.cfg new file mode 100644 index 0000000000..a02e88d97b --- /dev/null +++ b/board/cloudengines/pogo_e02/kwbimage.cfg @@ -0,0 +1,169 @@ +# +# Copyright (C) 2012 +# David Purdy <david.c.purdy@gmail.com> +# +# Based on Kirkwood support: +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar <prafulla <at> marvell.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; If not, see <http://www.gnu.org/licenses/>. +# +# Refer docs/README.kwimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations +BOOT_FROM nand +NAND_ECC_MODE default +NAND_PAGE_SIZE 0x0800 + +# SOC registers configuration using bootrom header extension +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed + +# Configure RGMII-0 interface pad voltage to 1.8V +DATA 0xffd100e0 0x1b1b1b9b + +#Dram initalization for SINGLE x16 CL=5 @ 400MHz +DATA 0xffd01400 0x43000c30 # DDR Configuration register +# bit13-0: 0xc30 (3120 DDR2 clks refresh rate) +# bit23-14: zero +# bit24: 1= enable exit self refresh mode on DDR access +# bit25: 1 required +# bit29-26: zero +# bit31-30: 01 + +DATA 0xffd01404 0x37543000 # DDR Controller Control Low +# bit 4: 0=addr/cmd in smame cycle +# bit 5: 0=clk is driven during self refresh, we don't care for APX +# bit 6: 0=use recommended falling edge of clk for addr/cmd +# bit14: 0=input buffer always powered up +# bit18: 1=cpu lock transaction enabled +# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 +# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM +# bit30-28: 3 required +# bit31: 0=no additional STARTBURST delay + +DATA 0xffd01408 0x22125451 # DDR Timing (Low) (active cycles value +1) +# bit3-0: TRAS lsbs +# bit7-4: TRCD +# bit11- 8: TRP +# bit15-12: TWR +# bit19-16: TWTR +# bit20: TRAS msb +# bit23-21: 0x0 +# bit27-24: TRRD +# bit31-28: TRTP + +DATA 0xffd0140c 0x00000a33 # DDR Timing (High) +# bit6-0: TRFC +# bit8-7: TR2R +# bit10-9: TR2W +# bit12-11: TW2W +# bit31-13: zero required + +DATA 0xffd01410 0x000000cc # DDR Address Control +# bit1-0: 00, Cs0width=x8 +# bit3-2: 11, Cs0size=1Gb +# bit5-4: 00, Cs1width=x8 +# bit7-6: 11, Cs1size=1Gb +# bit9-8: 00, Cs2width=nonexistent +# bit11-10: 00, Cs2size =nonexistent +# bit13-12: 00, Cs3width=nonexistent +# bit15-14: 00, Cs3size =nonexistent +# bit16: 0, Cs0AddrSel +# bit17: 0, Cs1AddrSel +# bit18: 0, Cs2AddrSel +# bit19: 0, Cs3AddrSel +# bit31-20: 0 required + +DATA 0xffd01414 0x00000000 # DDR Open Pages Control +# bit0: 0, OpenPage enabled +# bit31-1: 0 required + +DATA 0xffd01418 0x00000000 # DDR Operation +# bit3-0: 0x0, DDR cmd +# bit31-4: 0 required + +DATA 0xffd0141c 0x00000c52 # DDR Mode +# bit2-0: 2, BurstLen=2 required +# bit3: 0, BurstType=0 required +# bit6-4: 4, CL=5 +# bit7: 0, TestMode=0 normal +# bit8: 0, DLL reset=0 normal +# bit11-9: 6, auto-precharge write recovery ???????????? +# bit12: 0, PD must be zero +# bit31-13: 0 required + +DATA 0xffd01420 0x00000040 # DDR Extended Mode +# bit0: 0, DDR DLL enabled +# bit1: 0, DDR drive strenght normal +# bit2: 0, DDR ODT control lsd (disabled) +# bit5-3: 000, required +# bit6: 1, DDR ODT control msb, (disabled) +# bit9-7: 000, required +# bit10: 0, differential DQS enabled +# bit11: 0, required +# bit12: 0, DDR output buffer enabled +# bit31-13: 0 required + +DATA 0xffd01424 0x0000f17f # DDR Controller Control High +# bit2-0: 111, required +# bit3 : 1 , MBUS Burst Chop disabled +# bit6-4: 111, required +# bit7 : 0 +# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz +# bit9 : 0 , no half clock cycle addition to dataout +# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals +# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh +# bit15-12: 1111 required +# bit31-16: 0 required + +DATA 0xffd01428 0x00085520 # DDR2 ODT Read Timing (default values) +DATA 0xffd0147c 0x00008552 # DDR2 ODT Write Timing (default values) + +DATA 0xffd01500 0x00000000 # CS[0]n Base address to 0x0 +DATA 0xffd01504 0x0ffffff1 # CS[0]n Size +# bit0: 1, Window enabled +# bit1: 0, Write Protect disabled +# bit3-2: 00, CS0 hit selected +# bit23-4: ones, required +# bit31-24: 0x0F, Size (i.e. 256MB) + +DATA 0xffd01508 0x10000000 # CS[1]n Base address to 256Mb +DATA 0xffd0150c 0x00000000 # CS[2]n Size, window disabled + +DATA 0xffd01514 0x00000000 # CS[2]n Size, window disabled +DATA 0xffd0151c 0x00000000 # CS[3]n Size, window disabled + +DATA 0xffd01494 0x00030000 # DDR ODT Control (Low) +# bit3-0: 2, ODT0Rd, MODT[0] asserted during read from DRAM CS1 +# bit7-4: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0 +# bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1 +# bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 + +DATA 0xffd01498 0x00000000 # DDR ODT Control (High) +# bit1-0: 00, ODT0 controlled by ODT Control (low) register above +# bit3-2: 01, ODT1 active NEVER! +# bit31-4: zero, required + +DATA 0xffd0149c 0x0000e803 # CPU ODT Control +DATA 0xffd01480 0x00000001 # DDR Initialization Control +#bit0=1, enable DDR init upon this register write + +# End of Header extension +DATA 0x0 0x0 diff --git a/board/cloudengines/pogo_e02/pogo_e02.c b/board/cloudengines/pogo_e02/pogo_e02.c new file mode 100644 index 0000000000..ff3421d576 --- /dev/null +++ b/board/cloudengines/pogo_e02/pogo_e02.c @@ -0,0 +1,118 @@ +/* + * Copyright (C) 2012 + * David Purdy <david.c.purdy@gmail.com> + * + * Based on Kirkwood support: + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar <prafulla@marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; If not, see <http://www.gnu.org/licenses/>. + */ + +#include <common.h> +#include <miiphy.h> +#include <asm/arch/cpu.h> +#include <asm/arch/kirkwood.h> +#include <asm/arch/mpp.h> +#include "pogo_e02.h" + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + /* + * default gpio configuration + * There are maximum 64 gpios controlled through 2 sets of registers + * the below configuration configures mainly initial LED status + */ + kw_config_gpio(POGO_E02_OE_VAL_LOW, + POGO_E02_OE_VAL_HIGH, + POGO_E02_OE_LOW, POGO_E02_OE_HIGH); + + /* Multi-Purpose Pins Functionality configuration */ + u32 kwmpp_config[] = { + MPP0_NF_IO2, + MPP1_NF_IO3, + MPP2_NF_IO4, + MPP3_NF_IO5, + MPP4_NF_IO6, + MPP5_NF_IO7, + MPP6_SYSRST_OUTn, + MPP7_GPO, + MPP8_UART0_RTS, + MPP9_UART0_CTS, + MPP10_UART0_TXD, + MPP11_UART0_RXD, + MPP12_SD_CLK, + MPP13_SD_CMD, + MPP14_SD_D0, + MPP15_SD_D1, + MPP16_SD_D2, + MPP17_SD_D3, + MPP18_NF_IO0, + MPP19_NF_IO1, + MPP29_TSMP9, /* USB Power Enable */ + MPP48_GPIO, /* LED green */ + MPP49_GPIO, /* LED orange */ + 0 + }; + kirkwood_mpp_conf(kwmpp_config); + return 0; +} + +int board_init(void) +{ + /* Boot parameters address */ + gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + + return 0; +} + +#ifdef CONFIG_RESET_PHY_R +/* Configure and initialize PHY */ +void reset_phy(void) +{ + u16 reg; + u16 devadr; + char *name = "egiga0"; + + if (miiphy_set_current_dev(name)) + return; + + /* command to read PHY dev address */ + if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { + printf("Err..(%s) could not read PHY dev address\n", __func__); + return; + } + + /* + * Enable RGMII delay on Tx and Rx for CPU port + * Ref: sec 4.7.2 of chip datasheet + */ + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); + miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®); + reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); + miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); + + /* reset the phy */ + miiphy_reset(name, devadr); + + debug("88E1116 Initialized on %s\n", name); +} +#endif /* CONFIG_RESET_PHY_R */ diff --git a/board/cloudengines/pogo_e02/pogo_e02.h b/board/cloudengines/pogo_e02/pogo_e02.h new file mode 100644 index 0000000000..40b4bab9e0 --- /dev/null +++ b/board/cloudengines/pogo_e02/pogo_e02.h @@ -0,0 +1,44 @@ +/* + * Copyright (C) 2012 + * David Purdy <david.c.purdy@gmail.com> + * + * Based on Kirkwood support: + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar <prafulla@marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef __POGO_E02_H +#define __POGO_E02_H + +/* GPIO configuration */ +#define POGO_E02_OE_LOW (~(0)) +#define POGO_E02_OE_HIGH (~(0)) +#define POGO_E02_OE_VAL_LOW (1 << 29) +#define POGO_E02_OE_VAL_HIGH 0 + +/* PHY related */ +#define MV88E1116_LED_FCTRL_REG 10 +#define MV88E1116_CPRSP_CR3_REG 21 +#define MV88E1116_MAC_CTRL_REG 21 +#define MV88E1116_PGADR_REG 22 +#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) +#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) + +#endif /* __POGO_E02_H */ diff --git a/board/cm_t35/cm_t35.c b/board/cm_t35/cm_t35.c index 7af1f41af2..89e6b08e7f 100644 --- a/board/cm_t35/cm_t35.c +++ b/board/cm_t35/cm_t35.c @@ -100,17 +100,6 @@ int board_init(void) } /* - * Routine: misc_init_r - * Description: display die ID - */ -int misc_init_r(void) -{ - dieid_num_r(); - - return 0; -} - -/* * Routine: set_muxconf_regs * Description: Setting up the configuration Mux registers specific to the * hardware. Many pins need to be moved from protect to primary @@ -241,6 +230,12 @@ static void cm_t3x_set_common_muxconf(void) /* I2C1 */ MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)); /*I2C1_SCL*/ MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)); /*I2C1_SDA*/ + /* I2C2 */ + MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)); /*I2C2_SCL*/ + MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)); /*I2C2_SDA*/ + /* I2C3 */ + MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)); /*I2C3_SCL*/ + MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)); /*I2C3_SDA*/ /* control and debug */ MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)); /*SYS_32K*/ @@ -318,7 +313,7 @@ void set_muxconf_regs(void) #ifdef CONFIG_GENERIC_MMC int board_mmc_init(bd_t *bis) { - return omap_mmc_init(0); + return omap_mmc_init(0, 0, 0); } #endif diff --git a/board/comelit/dig297/dig297.c b/board/comelit/dig297/dig297.c index 65482813d2..c6c10717b7 100644 --- a/board/comelit/dig297/dig297.c +++ b/board/comelit/dig297/dig297.c @@ -147,7 +147,7 @@ void set_muxconf_regs(void) #ifdef CONFIG_GENERIC_MMC int board_mmc_init(bd_t *bis) { - omap_mmc_init(0); + omap_mmc_init(0, 0, 0); return 0; } #endif diff --git a/board/corscience/tricorder/tricorder.c b/board/corscience/tricorder/tricorder.c index 435711a2ab..aaff2e868b 100644 --- a/board/corscience/tricorder/tricorder.c +++ b/board/corscience/tricorder/tricorder.c @@ -80,7 +80,7 @@ void set_muxconf_regs(void) #if defined(CONFIG_GENERIC_MMC) && !(defined(CONFIG_SPL_BUILD)) int board_mmc_init(bd_t *bis) { - return omap_mmc_init(0); + return omap_mmc_init(0, 0, 0); } #endif diff --git a/board/davinci/ea20/ea20.c b/board/davinci/ea20/ea20.c index 43632c2fd8..7e000404ee 100644 --- a/board/davinci/ea20/ea20.c +++ b/board/davinci/ea20/ea20.c @@ -272,7 +272,7 @@ int board_init(void) return 0; } -#ifdef BOARD_LATE_INIT +#ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) { @@ -287,7 +287,7 @@ int board_late_init(void) return 0; } -#endif /* BOARD_LATE_INIT */ +#endif /* CONFIG_BOARD_LATE_INIT */ #ifdef CONFIG_DRIVER_TI_EMAC diff --git a/board/denx/m28evk/m28evk.c b/board/denx/m28evk/m28evk.c index 53df4761f6..3d28ea84de 100644 --- a/board/denx/m28evk/m28evk.c +++ b/board/denx/m28evk/m28evk.c @@ -90,6 +90,8 @@ int board_mmc_init(bd_t *bis) { /* Configure WP as input. */ gpio_direction_input(MX28_PAD_AUART2_CTS__GPIO_3_10); + /* Turn on the power to the card. */ + gpio_direction_output(MX28_PAD_PWM3__GPIO_3_28, 0); return mxsmmc_initialize(bis, 0, m28_mmc_wp); } @@ -103,10 +105,18 @@ int board_mmc_init(bd_t *bis) int fecmxc_mii_postcall(int phy) { +#if defined(CONFIG_DENX_M28_V11) || defined(CONFIG_DENX_M28_V10) + /* KZ8031 PHY on old boards. */ + const uint32_t freq = 0x0080; +#else + /* KZ8021 PHY on new boards. */ + const uint32_t freq = 0x0000; +#endif + miiphy_write("FEC1", phy, MII_BMCR, 0x9000); miiphy_write("FEC1", phy, MII_OPMODE_STRAP_OVERRIDE, 0x0202); if (phy == 3) - miiphy_write("FEC1", 3, MII_PHY_CTRL2, 0x8180); + miiphy_write("FEC1", 3, MII_PHY_CTRL2, 0x8100 | freq); return 0; } @@ -123,6 +133,14 @@ int board_eth_init(bd_t *bis) CLKCTRL_ENET_TIME_SEL_MASK | CLKCTRL_ENET_CLK_OUT_EN, CLKCTRL_ENET_TIME_SEL_RMII_CLK); +#if !defined(CONFIG_DENX_M28_V11) && !defined(CONFIG_DENX_M28_V10) + /* Reset the new PHY */ + gpio_direction_output(MX28_PAD_AUART2_RTS__GPIO_3_11, 0); + udelay(10000); + gpio_set_value(MX28_PAD_AUART2_RTS__GPIO_3_11, 1); + udelay(10000); +#endif + ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE); if (ret) { printf("FEC MXS: Unable to init FEC0\n"); diff --git a/board/denx/m28evk/spl_boot.c b/board/denx/m28evk/spl_boot.c index a04fe180c1..7a125925de 100644 --- a/board/denx/m28evk/spl_boot.c +++ b/board/denx/m28evk/spl_boot.c @@ -109,8 +109,9 @@ const iomux_cfg_t iomux_setup[] = { (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL), MX28_PAD_SSP0_SCK__SSP0_SCK | (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL), - MX28_PAD_PWM3__GPIO_3_28 | MUX_CONFIG_SSP0, /* Power .. FIXME */ - MX28_PAD_AUART2_CTS__GPIO_3_10, /* WP ... FIXME */ + MX28_PAD_PWM3__GPIO_3_28 | MUX_CONFIG_SSP0 | + (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL), /* Power */ + MX28_PAD_AUART2_CTS__GPIO_3_10, /* WP */ /* GPMI NAND */ MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI, @@ -147,6 +148,9 @@ const iomux_cfg_t iomux_setup[] = { MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MUX_CONFIG_ENET, MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MUX_CONFIG_ENET, MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MUX_CONFIG_ENET, +#if !defined(CONFIG_DENX_M28_V11) && !defined(CONFIG_DENX_M28_V10) + MX28_PAD_AUART2_RTS__GPIO_3_11, /* PHY reset */ +#endif /* I2C */ MX28_PAD_I2C0_SCL__I2C0_SCL, diff --git a/board/esg/ima3-mx53/Makefile b/board/esg/ima3-mx53/Makefile new file mode 100644 index 0000000000..f3b13bccaf --- /dev/null +++ b/board/esg/ima3-mx53/Makefile @@ -0,0 +1,41 @@ +# +# Copyright (C) 2012, Stefano Babic <sbabic@denx.de> +# +# Based on ti/evm/Makefile +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := ima3-mx53.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/esg/ima3-mx53/ima3-mx53.c b/board/esg/ima3-mx53/ima3-mx53.c new file mode 100644 index 0000000000..9ecf31d7c2 --- /dev/null +++ b/board/esg/ima3-mx53/ima3-mx53.c @@ -0,0 +1,302 @@ +/* + * (C) Copyright 2012, Stefano Babic <sbabic@denx.de> + * + * (C) Copyright 2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ +#include <common.h> +#include <asm/io.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/mx5x_pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/clock.h> +#include <asm/arch/iomux.h> +#include <asm/errno.h> +#include <netdev.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include <asm/gpio.h> + +/* NOR flash configuration */ +#define IMA3_MX53_CS0GCR1 (CSEN | DSZ(2)) +#define IMA3_MX53_CS0GCR2 0 +#define IMA3_MX53_CS0RCR1 (RCSN(2) | OEN(1) | RWSC(15)) +#define IMA3_MX53_CS0RCR2 0 +#define IMA3_MX53_CS0WCR1 (WBED1 | WCSN(2) | WEN(1) | WWSC(15)) +#define IMA3_MX53_CS0WCR2 0 + +DECLARE_GLOBAL_DATA_PTR; + +static void weim_nor_settings(void) +{ + struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR; + + writel(IMA3_MX53_CS0GCR1, &weim_regs->cs0gcr1); + writel(IMA3_MX53_CS0GCR2, &weim_regs->cs0gcr2); + writel(IMA3_MX53_CS0RCR1, &weim_regs->cs0rcr1); + writel(IMA3_MX53_CS0RCR2, &weim_regs->cs0rcr2); + writel(IMA3_MX53_CS0WCR1, &weim_regs->cs0wcr1); + writel(IMA3_MX53_CS0WCR2, &weim_regs->cs0wcr2); + writel(0x0, &weim_regs->wcr); + + set_chipselect_size(CS0_128); +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE, + PHYS_SDRAM_1_SIZE); + return 0; +} + +static void setup_iomux_uart(void) +{ + /* UART4 RXD */ + mxc_request_iomux(MX53_PIN_CSI0_D13, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX53_PIN_CSI0_D13, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | + PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE); + mxc_iomux_set_input(MX53_UART4_IPP_UART_RXD_MUX_SELECT_INPUT, 0x3); + + /* UART4 TXD */ + mxc_request_iomux(MX53_PIN_CSI0_D12, IOMUX_CONFIG_ALT2); + mxc_iomux_set_pad(MX53_PIN_CSI0_D12, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | + PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE); +} + +static void setup_iomux_fec(void) +{ + /*FEC_MDIO*/ + mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_FEC_MDIO, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | PAD_CTL_22K_PU | + PAD_CTL_ODE_OPENDRAIN_ENABLE); + mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1); + + /*FEC_MDC*/ + mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH); + + /* FEC RXD3 */ + mxc_request_iomux(MX53_PIN_KEY_COL0, IOMUX_CONFIG_ALT6); + mxc_iomux_set_pad(MX53_PIN_KEY_COL0, PAD_CTL_HYS_ENABLE | + PAD_CTL_PKE_ENABLE); + + /* FEC RXD2 */ + mxc_request_iomux(MX53_PIN_KEY_COL2, IOMUX_CONFIG_ALT6); + mxc_iomux_set_pad(MX53_PIN_KEY_COL2, PAD_CTL_HYS_ENABLE | + PAD_CTL_PKE_ENABLE); + + /* FEC RXD1 */ + mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_FEC_RXD1, PAD_CTL_HYS_ENABLE | + PAD_CTL_PKE_ENABLE); + + /* FEC RXD0 */ + mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_FEC_RXD0, PAD_CTL_HYS_ENABLE | + PAD_CTL_PKE_ENABLE); + + /* FEC TXD3 */ + mxc_request_iomux(MX53_PIN_GPIO_19, IOMUX_CONFIG_ALT6); + mxc_iomux_set_pad(MX53_PIN_GPIO_19, PAD_CTL_DRV_HIGH); + + /* FEC TXD2 */ + mxc_request_iomux(MX53_PIN_KEY_ROW2, IOMUX_CONFIG_ALT6); + mxc_iomux_set_pad(MX53_PIN_KEY_ROW2, PAD_CTL_DRV_HIGH); + + /* FEC TXD1 */ + mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH); + + /* FEC TXD0 */ + mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH); + + /* FEC TX_EN */ + mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH); + + /* FEC TX_CLK */ + mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK, PAD_CTL_HYS_ENABLE | + PAD_CTL_PKE_ENABLE); + + /* FEC RX_ER */ + mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER, PAD_CTL_HYS_ENABLE | + PAD_CTL_PKE_ENABLE); + + /* FEC RX_DV */ + mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV, PAD_CTL_HYS_ENABLE | + PAD_CTL_PKE_ENABLE); + + /* FEC CRS */ + mxc_request_iomux(MX53_PIN_KEY_COL3, IOMUX_CONFIG_ALT6); + mxc_iomux_set_pad(MX53_PIN_KEY_COL3, PAD_CTL_HYS_ENABLE | + PAD_CTL_PKE_ENABLE); + + /* FEC COL */ + mxc_request_iomux(MX53_PIN_KEY_ROW1, IOMUX_CONFIG_ALT6); + mxc_iomux_set_pad(MX53_PIN_KEY_ROW1, PAD_CTL_HYS_ENABLE | + PAD_CTL_PKE_ENABLE); + mxc_iomux_set_input(MX53_FEC_FEC_COL_SELECT_INPUT, 0x0); + + /* FEC RX_CLK */ + mxc_request_iomux(MX53_PIN_KEY_COL1, IOMUX_CONFIG_ALT6); + mxc_iomux_set_pad(MX53_PIN_KEY_COL1, PAD_CTL_HYS_ENABLE | + PAD_CTL_PKE_ENABLE); + mxc_iomux_set_input(MX53_FEC_FEC_RX_CLK_SELECT_INPUT, 0x0); +} + +#ifdef CONFIG_FSL_ESDHC +struct fsl_esdhc_cfg esdhc_cfg = { MMC_SDHC1_BASE_ADDR, 1 }; + +int board_mmc_getcd(struct mmc *mmc) +{ + int ret; + + ret = !gpio_get_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_1)); + + return ret; +} + +int board_mmc_init(bd_t *bis) +{ + mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_GPIO_1, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX53_PIN_GPIO_1, + PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | + PAD_CTL_PUE_KEEPER | PAD_CTL_100K_PU | + PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_PKE_ENABLE); + gpio_direction_input(IOMUX_TO_GPIO(MX53_PIN_GPIO_1)); + + mxc_iomux_set_pad(MX53_PIN_SD1_CMD, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU); + mxc_iomux_set_pad(MX53_PIN_SD1_CLK, + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | + PAD_CTL_47K_PU | PAD_CTL_DRV_HIGH); + mxc_iomux_set_pad(MX53_PIN_SD1_DATA0, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); + mxc_iomux_set_pad(MX53_PIN_SD1_DATA1, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); + mxc_iomux_set_pad(MX53_PIN_SD1_DATA2, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); + mxc_iomux_set_pad(MX53_PIN_SD1_DATA3, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); + + return fsl_esdhc_initialize(bis, &esdhc_cfg); +} +#endif + +static void setup_iomux_spi(void) +{ + /* SCLK */ + mxc_request_iomux(MX53_PIN_CSI0_D8, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX53_PIN_CSI0_D8, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); + mxc_iomux_set_input(MX53_ECSPI2_IPP_CSPI_CLK_IN_SELECT_INPUT, 0x1); + /* MOSI */ + mxc_request_iomux(MX53_PIN_CSI0_D9, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX53_PIN_CSI0_D9, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); + mxc_iomux_set_input(MX53_ECSPI2_IPP_IND_MOSI_SELECT_INPUT, 0x1); + /* MISO */ + mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX53_PIN_CSI0_D10, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); + mxc_iomux_set_input(MX53_ECSPI2_IPP_IND_MISO_SELECT_INPUT, 0x1); + /* SSEL 0 */ + mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_GPIO); + mxc_iomux_set_pad(MX53_PIN_CSI0_D11, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL | + PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU); + gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_CSI0_D11), 1); +} + +int board_early_init_f(void) +{ + /* configure I/O pads */ + setup_iomux_uart(); + setup_iomux_fec(); + + weim_nor_settings(); + + /* configure spi */ + setup_iomux_spi(); + + return 0; +} + +int board_init(void) +{ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + mxc_set_sata_internal_clock(); + + return 0; +} + +#if defined(CONFIG_RESET_PHY_R) +#include <miiphy.h> + +void reset_phy(void) +{ + unsigned short reg; + + /* reset the phy */ + miiphy_reset("FEC", CONFIG_PHY_ADDR); + + /* set hard link to 100Mbit, full-duplex */ + miiphy_read("FEC", CONFIG_PHY_ADDR, MII_BMCR, ®); + reg &= ~BMCR_ANENABLE; + reg |= (BMCR_SPEED100 | BMCR_FULLDPLX); + miiphy_write("FEC", CONFIG_PHY_ADDR, MII_BMCR, reg); + + miiphy_read("FEC", CONFIG_PHY_ADDR, 0x16, ®); + reg |= (1 << 5); + miiphy_write("FEC", CONFIG_PHY_ADDR, 0x16, reg); +} +#endif + +int checkboard(void) +{ + puts("Board: IMA3_MX53\n"); + + return 0; +} diff --git a/board/esg/ima3-mx53/imximage.cfg b/board/esg/ima3-mx53/imximage.cfg new file mode 100644 index 0000000000..fa6b42ddcc --- /dev/null +++ b/board/esg/ima3-mx53/imximage.cfg @@ -0,0 +1,108 @@ +# +# (C) Copyright 2012 +# Stefano Babic DENX Software Engineering sbabic@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not write to the Free Software +# Foundation Inc. 51 Franklin Street Fifth Floor Boston, +# MA 02110-1301 USA +# +# Refer docs/README.imxmage for more details about how-to configure +# and create imximage boot image +# +# The syntax is taken as close as possible with the kwbimage + +# image version + +IMAGE_VERSION 2 + +# Boot Device : one of +# spi, sd (the board has no nand neither onenand) + +BOOT_FROM nor + +# Device Configuration Data (DCD) +# +# Each entry must have the format: +# Addr-type Address Value +# +# where: +# Addr-type register length (1,2 or 4 bytes) +# Address absolute address of the register +# value value to be stored in the register + +# IOMUX for RAM only +DATA 4 0x53fa8554 0x300020 +DATA 4 0x53fa8560 0x300020 +DATA 4 0x53fa8594 0x300020 +DATA 4 0x53fa8584 0x300020 +DATA 4 0x53fa8558 0x300040 +DATA 4 0x53fa8568 0x300040 +DATA 4 0x53fa8590 0x300040 +DATA 4 0x53fa857c 0x300040 +DATA 4 0x53fa8564 0x300040 +DATA 4 0x53fa8580 0x300040 +DATA 4 0x53fa8570 0x300220 +DATA 4 0x53fa8578 0x300220 +DATA 4 0x53fa872c 0x300000 +DATA 4 0x53fa8728 0x300000 +DATA 4 0x53fa871c 0x300000 +DATA 4 0x53fa8718 0x300000 +DATA 4 0x53fa8574 0x300020 +DATA 4 0x53fa8588 0x300020 +DATA 4 0x53fa855c 0x0 +DATA 4 0x53fa858c 0x0 +DATA 4 0x53fa856c 0x300040 +DATA 4 0x53fa86f0 0x300000 +DATA 4 0x53fa8720 0x300000 +DATA 4 0x53fa86fc 0x0 +DATA 4 0x53fa86f4 0x0 +DATA 4 0x53fa8714 0x0 +DATA 4 0x53fa8724 0x4000000 +# +# DDR RAM +DATA 4 0x63fd9088 0x40404040 +DATA 4 0x63fd9090 0x40404040 +DATA 4 0x63fd907C 0x01420143 +DATA 4 0x63fd9080 0x01450146 +DATA 4 0x63fd9018 0x00111740 +DATA 4 0x63fd9000 0x84190000 +# esdcfgX +DATA 4 0x63fd900C 0x9f5152e3 +DATA 4 0x63fd9010 0xb68e8a63 +DATA 4 0x63fd9014 0x01ff00db +# Read/Write command delay +DATA 4 0x63fd902c 0x000026d2 +# Out of reset delays +DATA 4 0x63fd9030 0x00ff0e21 +# ESDCTL ODT timing control +DATA 4 0x63fd9008 0x12273030 +# ESDCTL power down control +DATA 4 0x63fd9004 0x0002002d +# Set registers in DDR memory chips +DATA 4 0x63fd901c 0x00008032 +DATA 4 0x63fd901c 0x00008033 +DATA 4 0x63fd901c 0x00028031 +DATA 4 0x63fd901c 0x052080b0 +DATA 4 0x63fd901c 0x04008040 +# ESDCTL refresh control +DATA 4 0x63fd9020 0x00005800 +# PHY ZQ HW control +DATA 4 0x63fd9040 0x05380003 +# PHY ODT control +DATA 4 0x63fd9058 0x00022222 +# start DDR3 +DATA 4 0x63fd901c 0x00000000 diff --git a/board/freescale/mx28evk/iomux.c b/board/freescale/mx28evk/iomux.c index 396761bdff..6587c454fe 100644 --- a/board/freescale/mx28evk/iomux.c +++ b/board/freescale/mx28evk/iomux.c @@ -26,6 +26,7 @@ #include <asm/arch/sys_proto.h> #define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) +#define MUX_CONFIG_GPMI (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) #define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) #define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL) #define MUX_CONFIG_SSP2 (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP) @@ -55,6 +56,26 @@ const iomux_cfg_t iomux_setup[] = { MX28_PAD_PWM3__GPIO_3_28 | (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), +#ifdef CONFIG_NAND_MXS + /* GPMI NAND */ + MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_RDN__GPMI_RDN | + (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP), + MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_RESETN__GPMI_RESETN | MUX_CONFIG_GPMI, +#endif + /* FEC0 */ MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET, MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET, diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c index d736141e28..dec966ddd6 100644 --- a/board/freescale/mx53loco/mx53loco.c +++ b/board/freescale/mx53loco/mx53loco.c @@ -27,6 +27,7 @@ #include <asm/arch/mx5x_pins.h> #include <asm/arch/sys_proto.h> #include <asm/arch/crm_regs.h> +#include <asm/arch/clock.h> #include <asm/arch/iomux.h> #include <asm/arch/clock.h> #include <asm/errno.h> @@ -35,6 +36,9 @@ #include <mmc.h> #include <fsl_esdhc.h> #include <asm/gpio.h> +#include <pmic.h> +#include <dialog_pmic.h> +#include <fsl_pmic.h> DECLARE_GLOBAL_DATA_PTR; @@ -58,6 +62,18 @@ void dram_init_banksize(void) gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; } +u32 get_board_rev(void) +{ + struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; + struct fuse_bank *bank = &iim->bank[0]; + struct fuse_bank0_regs *fuse = + (struct fuse_bank0_regs *)bank->fuse_regs; + + int rev = readl(&fuse->gp[6]); + + return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8; +} + static void setup_iomux_uart(void) { /* UART1 RXD */ @@ -81,10 +97,9 @@ static void setup_iomux_uart(void) #ifdef CONFIG_USB_EHCI_MX5 int board_ehci_hcd_init(int port) { - /* request VBUS power enable pin, GPIO[8}, gpio7 */ + /* request VBUS power enable pin, GPIO7_8 */ mxc_request_iomux(MX53_PIN_ATA_DA_2, IOMUX_CONFIG_ALT1); - gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2), 0); - gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2), 1); + gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2), 1); return 0; } #endif @@ -290,6 +305,103 @@ int board_mmc_init(bd_t *bis) } #endif +static void setup_iomux_i2c(void) +{ + /* I2C1 SDA */ + mxc_request_iomux(MX53_PIN_CSI0_D8, + IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION); + mxc_iomux_set_input(MX53_I2C1_IPP_SDA_IN_SELECT_INPUT, + INPUT_CTL_PATH0); + mxc_iomux_set_pad(MX53_PIN_CSI0_D8, + PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | + PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PULL | + PAD_CTL_ODE_OPENDRAIN_ENABLE); + /* I2C1 SCL */ + mxc_request_iomux(MX53_PIN_CSI0_D9, + IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION); + mxc_iomux_set_input(MX53_I2C1_IPP_SCL_IN_SELECT_INPUT, + INPUT_CTL_PATH0); + mxc_iomux_set_pad(MX53_PIN_CSI0_D9, + PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | + PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PULL | + PAD_CTL_ODE_OPENDRAIN_ENABLE); +} + +static int power_init(void) +{ + unsigned int val; + int ret = -1; + struct pmic *p; + + if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR)) { + pmic_dialog_init(); + p = get_pmic(); + + /* Set VDDA to 1.25V */ + val = DA9052_BUCKCORE_BCOREEN | DA_BUCKCORE_VBCORE_1_250V; + ret = pmic_reg_write(p, DA9053_BUCKCORE_REG, val); + + ret |= pmic_reg_read(p, DA9053_SUPPLY_REG, &val); + val |= DA9052_SUPPLY_VBCOREGO; + ret |= pmic_reg_write(p, DA9053_SUPPLY_REG, val); + + /* Set Vcc peripheral to 1.30V */ + ret |= pmic_reg_write(p, DA9053_BUCKPRO_REG, 0x62); + ret |= pmic_reg_write(p, DA9053_SUPPLY_REG, 0x62); + } + + if (!i2c_probe(CONFIG_SYS_FSL_PMIC_I2C_ADDR)) { + pmic_init(); + p = get_pmic(); + + /* Set VDDGP to 1.25V for 1GHz on SW1 */ + pmic_reg_read(p, REG_SW_0, &val); + val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_250V_MC34708; + ret = pmic_reg_write(p, REG_SW_0, val); + + /* Set VCC as 1.30V on SW2 */ + pmic_reg_read(p, REG_SW_1, &val); + val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_300V_MC34708; + ret |= pmic_reg_write(p, REG_SW_1, val); + + /* Set global reset timer to 4s */ + pmic_reg_read(p, REG_POWER_CTL2, &val); + val = (val & ~TIMER_MASK_MC34708) | TIMER_4S_MC34708; + ret |= pmic_reg_write(p, REG_POWER_CTL2, val); + + /* Set VUSBSEL and VUSBEN for USB PHY supply*/ + pmic_reg_read(p, REG_MODE_0, &val); + val |= (VUSBSEL_MC34708 | VUSBEN_MC34708); + ret |= pmic_reg_write(p, REG_MODE_0, val); + + /* Set SWBST to 5V in auto mode */ + val = SWBST_AUTO; + ret |= pmic_reg_write(p, SWBST_CTRL, val); + } + + return ret; +} + +static void clock_1GHz(void) +{ + int ret; + u32 ref_clk = CONFIG_SYS_MX5_HCLK; + /* + * After increasing voltage to 1.25V, we can switch + * CPU clock to 1GHz and DDR to 400MHz safely + */ + ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK); + if (ret) + printf("CPU: Switch CPU clock to 1GHZ failed\n"); + + ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK); + ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK); + if (ret) + printf("CPU: Switch DDR clock to 400MHz failed\n"); +} + int board_early_init_f(void) { setup_iomux_uart(); @@ -298,10 +410,38 @@ int board_early_init_f(void) return 0; } +int print_cpuinfo(void) +{ + u32 cpurev; + + cpurev = get_cpu_rev(); + printf("CPU: Freescale i.MX%x family rev%d.%d at %d MHz\n", + (cpurev & 0xFF000) >> 12, + (cpurev & 0x000F0) >> 4, + (cpurev & 0x0000F) >> 0, + mxc_get_clock(MXC_ARM_CLK) / 1000000); + printf("Reset cause: %s\n", get_reset_cause()); + return 0; +} + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ + setup_iomux_i2c(); + if (!power_init()) + clock_1GHz(); + print_cpuinfo(); + + return 0; +} +#endif + int board_init(void) { gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + mxc_set_sata_internal_clock(); + return 0; } diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c index fda3e41a03..29cbfed120 100644 --- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c +++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c @@ -25,6 +25,7 @@ #include <asm/arch/imx-regs.h> #include <asm/arch/mx6x_pins.h> #include <asm/arch/iomux-v3.h> +#include <asm/arch/clock.h> #include <asm/errno.h> #include <asm/gpio.h> #include <mmc.h> @@ -50,6 +51,10 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) +#define BUTTON_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + int dram_init(void) { gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); @@ -122,6 +127,22 @@ iomux_v3_cfg_t enet_pads2[] = { MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), }; +/* Button assignments for J14 */ +static iomux_v3_cfg_t button_pads[] = { + /* Menu */ + MX6Q_PAD_NANDF_D1__GPIO_2_1 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + /* Back */ + MX6Q_PAD_NANDF_D2__GPIO_2_2 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + /* Labelled Search (mapped to Power under Android) */ + MX6Q_PAD_NANDF_D3__GPIO_2_3 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + /* Home */ + MX6Q_PAD_NANDF_D4__GPIO_2_4 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + /* Volume Down */ + MX6Q_PAD_GPIO_19__GPIO_4_5 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), + /* Volume Up */ + MX6Q_PAD_GPIO_18__GPIO_7_13 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), +}; + static void setup_iomux_enet(void) { gpio_direction_output(87, 0); /* GPIO 3-23 */ @@ -135,7 +156,7 @@ static void setup_iomux_enet(void) /* Need delay 10ms according to KSZ9021 spec */ udelay(1000 * 10); - gpio_direction_output(87, 1); /* GPIO 3-23 */ + gpio_set_value(87, 1); /* GPIO 3-23 */ imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2)); } @@ -267,11 +288,44 @@ int board_eth_init(bd_t *bis) return 0; } +static void setup_buttons(void) +{ + imx_iomux_v3_setup_multiple_pads(button_pads, + ARRAY_SIZE(button_pads)); +} + +#ifdef CONFIG_CMD_SATA + +int setup_sata(void) +{ + struct iomuxc_base_regs *const iomuxc_regs + = (struct iomuxc_base_regs *) IOMUXC_BASE_ADDR; + int ret = enable_sata_clock(); + if (ret) + return ret; + + clrsetbits_le32(&iomuxc_regs->gpr[13], + IOMUXC_GPR13_SATA_MASK, + IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB + |IOMUXC_GPR13_SATA_PHY_7_SATA2M + |IOMUXC_GPR13_SATA_SPEED_3G + |(3<<IOMUXC_GPR13_SATA_PHY_6_SHIFT) + |IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED + |IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16 + |IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB + |IOMUXC_GPR13_SATA_PHY_2_TX_1P104V + |IOMUXC_GPR13_SATA_PHY_1_SLOW); + + return 0; +} +#endif + int board_early_init_f(void) { - setup_iomux_uart(); + setup_iomux_uart(); + setup_buttons(); - return 0; + return 0; } int board_init(void) @@ -283,6 +337,10 @@ int board_init(void) setup_spi(); #endif +#ifdef CONFIG_CMD_SATA + setup_sata(); +#endif + return 0; } @@ -292,3 +350,94 @@ int checkboard(void) return 0; } + +struct button_key { + char const *name; + unsigned gpnum; + char ident; +}; + +static struct button_key const buttons[] = { + {"back", GPIO_NUMBER(2, 2), 'B'}, + {"home", GPIO_NUMBER(2, 4), 'H'}, + {"menu", GPIO_NUMBER(2, 1), 'M'}, + {"search", GPIO_NUMBER(2, 3), 'S'}, + {"volup", GPIO_NUMBER(7, 13), 'V'}, + {"voldown", GPIO_NUMBER(4, 5), 'v'}, +}; + +/* + * generate a null-terminated string containing the buttons pressed + * returns number of keys pressed + */ +static int read_keys(char *buf) +{ + int i, numpressed = 0; + for (i = 0; i < ARRAY_SIZE(buttons); i++) { + if (!gpio_get_value(buttons[i].gpnum)) + buf[numpressed++] = buttons[i].ident; + } + buf[numpressed] = '\0'; + return numpressed; +} + +static int do_kbd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + char envvalue[ARRAY_SIZE(buttons)+1]; + int numpressed = read_keys(envvalue); + setenv("keybd", envvalue); + return numpressed == 0; +} + +U_BOOT_CMD( + kbd, 1, 1, do_kbd, + "Tests for keypresses, sets 'keybd' environment variable", + "Returns 0 (true) to shell if key is pressed." +); + +#ifdef CONFIG_PREBOOT +static char const kbd_magic_prefix[] = "key_magic"; +static char const kbd_command_prefix[] = "key_cmd"; + +static void preboot_keys(void) +{ + int numpressed; + char keypress[ARRAY_SIZE(buttons)+1]; + numpressed = read_keys(keypress); + if (numpressed) { + char *kbd_magic_keys = getenv("magic_keys"); + char *suffix; + /* + * loop over all magic keys + */ + for (suffix = kbd_magic_keys; *suffix; ++suffix) { + char *keys; + char magic[sizeof(kbd_magic_prefix) + 1]; + sprintf(magic, "%s%c", kbd_magic_prefix, *suffix); + keys = getenv(magic); + if (keys) { + if (!strcmp(keys, keypress)) + break; + } + } + if (*suffix) { + char cmd_name[sizeof(kbd_command_prefix) + 1]; + char *cmd; + sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix); + cmd = getenv(cmd_name); + if (cmd) { + setenv("preboot", cmd); + return; + } + } + } +} +#endif + +int misc_init_r(void) +{ +#ifdef CONFIG_PREBOOT + preboot_keys(); +#endif + return 0; +} diff --git a/board/htkw/mcx/mcx.c b/board/htkw/mcx/mcx.c index e593b43d48..8f75af19d4 100644 --- a/board/htkw/mcx/mcx.c +++ b/board/htkw/mcx/mcx.c @@ -69,17 +69,6 @@ int board_init(void) } /* - * Routine: misc_init_r - * Description: late init. - */ -int misc_init_r(void) -{ - dieid_num_r(); - - return 0; -} - -/* * Routine: set_muxconf_regs * Description: Setting up the configuration Mux registers specific to the * hardware. Many pins need to be moved from protect to primary @@ -93,7 +82,7 @@ void set_muxconf_regs(void) #if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { - return omap_mmc_init(0); + return omap_mmc_init(0, 0, 0); } #endif diff --git a/board/isee/igep0020/igep0020.c b/board/isee/igep0020/igep0020.c index 6a3777eb8c..971e31b5f3 100644 --- a/board/isee/igep0020/igep0020.c +++ b/board/isee/igep0020/igep0020.c @@ -52,8 +52,6 @@ static const u32 gpmc_lan_config[] = { int board_init(void) { gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ - /* board id for Linux */ - gd->bd->bi_arch_number = MACH_TYPE_IGEP0020; /* boot param addr */ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); @@ -96,7 +94,7 @@ static void setup_net_chip(void) #ifdef CONFIG_GENERIC_MMC int board_mmc_init(bd_t *bis) { - omap_mmc_init(0); + omap_mmc_init(0, 0, 0); return 0; } #endif diff --git a/board/isee/igep0030/igep0030.c b/board/isee/igep0030/igep0030.c index 6a927350b4..653c1b5abb 100644 --- a/board/isee/igep0030/igep0030.c +++ b/board/isee/igep0030/igep0030.c @@ -39,8 +39,6 @@ DECLARE_GLOBAL_DATA_PTR; int board_init(void) { gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ - /* board id for Linux */ - gd->bd->bi_arch_number = MACH_TYPE_IGEP0030; /* boot param addr */ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); @@ -50,7 +48,7 @@ int board_init(void) #ifdef CONFIG_GENERIC_MMC int board_mmc_init(bd_t *bis) { - omap_mmc_init(0); + omap_mmc_init(0, 0, 0); return 0; } #endif diff --git a/board/logicpd/am3517evm/am3517evm.c b/board/logicpd/am3517evm/am3517evm.c index 0a105bf281..d316f33cd1 100644 --- a/board/logicpd/am3517evm/am3517evm.c +++ b/board/logicpd/am3517evm/am3517evm.c @@ -79,7 +79,7 @@ void set_muxconf_regs(void) #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { - omap_mmc_init(0); + omap_mmc_init(0, 0, 0); return 0; } #endif diff --git a/board/logicpd/omap3som/omap3logic.c b/board/logicpd/omap3som/omap3logic.c index bc7ec68f14..12bcfcb877 100644 --- a/board/logicpd/omap3som/omap3logic.c +++ b/board/logicpd/omap3som/omap3logic.c @@ -140,21 +140,10 @@ int board_init(void) #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { - return omap_mmc_init(0); + return omap_mmc_init(0, 0, 0); } #endif -/* - * Routine: misc_init_r - * Description: display die ID register - */ -int misc_init_r(void) -{ - dieid_num_r(); - - return 0; -} - #ifdef CONFIG_SMC911X /* GPMC CS1 settings for Logic SOM LV/Torpedo LAN92xx Ethernet chip */ static const u32 gpmc_lan92xx_config[] = { diff --git a/board/logicpd/zoom1/zoom1.c b/board/logicpd/zoom1/zoom1.c index dec0b2611f..90b6b0fde5 100644 --- a/board/logicpd/zoom1/zoom1.c +++ b/board/logicpd/zoom1/zoom1.c @@ -92,7 +92,7 @@ void set_muxconf_regs(void) #ifdef CONFIG_GENERIC_MMC int board_mmc_init(bd_t *bis) { - omap_mmc_init(0); + omap_mmc_init(0, 0, 0); return 0; } #endif diff --git a/board/logicpd/zoom2/zoom2.c b/board/logicpd/zoom2/zoom2.c index be3083d9c3..8e18019801 100644 --- a/board/logicpd/zoom2/zoom2.c +++ b/board/logicpd/zoom2/zoom2.c @@ -183,7 +183,7 @@ void set_muxconf_regs (void) #ifdef CONFIG_GENERIC_MMC int board_mmc_init(bd_t *bis) { - omap_mmc_init(0); + omap_mmc_init(0, 0, 0); return 0; } #endif diff --git a/board/matrix_vision/mvblx/mvblx.c b/board/matrix_vision/mvblx/mvblx.c index 74b5b19be2..f68f312215 100644 --- a/board/matrix_vision/mvblx/mvblx.c +++ b/board/matrix_vision/mvblx/mvblx.c @@ -106,8 +106,8 @@ void set_muxconf_regs(void) #ifdef CONFIG_GENERIC_MMC int board_mmc_init(bd_t *bis) { - omap_mmc_init(0); - omap_mmc_init(1); + omap_mmc_init(0, 0, 0); + omap_mmc_init(1, 0, 0); return 0; } #endif diff --git a/board/nvidia/common/Makefile b/board/nvidia/common/Makefile index 3e748fdd20..a93d4583e7 100644 --- a/board/nvidia/common/Makefile +++ b/board/nvidia/common/Makefile @@ -27,6 +27,7 @@ LIB = $(obj)lib$(VENDOR).o COBJS-y += board.o COBJS-$(CONFIG_SPI_UART_SWITCH) += uart-spi-switch.o +COBJS-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o COBJS := $(COBJS-y) SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c index 85dd359ec9..2e22133591 100644 --- a/board/nvidia/common/board.c +++ b/board/nvidia/common/board.c @@ -23,6 +23,7 @@ #include <common.h> #include <ns16550.h> +#include <linux/compiler.h> #include <asm/io.h> #include <asm/arch/tegra2.h> #include <asm/arch/sys_proto.h> @@ -30,12 +31,17 @@ #include <asm/arch/board.h> #include <asm/arch/clk_rst.h> #include <asm/arch/clock.h> +#include <asm/arch/emc.h> #include <asm/arch/pinmux.h> +#include <asm/arch/pmc.h> +#include <asm/arch/pmu.h> #include <asm/arch/uart.h> +#include <asm/arch/warmboot.h> #include <spi.h> #include <asm/arch/usb.h> #include <i2c.h> #include "board.h" +#include "emc.h" DECLARE_GLOBAL_DATA_PTR; @@ -59,11 +65,28 @@ void __pin_mux_usb(void) void pin_mux_usb(void) __attribute__((weak, alias("__pin_mux_usb"))); /* + * Routine: power_det_init + * Description: turn off power detects + */ +static void power_det_init(void) +{ +#if defined(CONFIG_TEGRA2) + struct pmc_ctlr *const pmc = (struct pmc_ctlr *)TEGRA2_PMC_BASE; + + /* turn off power detects */ + writel(0, &pmc->pmc_pwr_det_latch); + writel(0, &pmc->pmc_pwr_det); +#endif +} + +/* * Routine: board_init * Description: Early hardware init. */ int board_init(void) { + __maybe_unused int err; + /* Do clocks and UART first so that printf() works */ clock_init(); clock_verify(); @@ -76,18 +99,35 @@ int board_init(void) #endif /* boot param addr */ gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100); + + power_det_init(); + #ifdef CONFIG_TEGRA_I2C #ifndef CONFIG_SYS_I2C_INIT_BOARD #error "You must define CONFIG_SYS_I2C_INIT_BOARD to use i2c on Nvidia boards" #endif i2c_init_board(); -#endif +# ifdef CONFIG_TEGRA_PMU + if (pmu_set_nominal()) + debug("Failed to select nominal voltages\n"); +# ifdef CONFIG_TEGRA_CLOCK_SCALING + err = board_emc_init(); + if (err) + debug("Memory controller init failed: %d\n", err); +# endif +# endif /* CONFIG_TEGRA_PMU */ +#endif /* CONFIG_TEGRA_I2C */ #ifdef CONFIG_USB_EHCI_TEGRA pin_mux_usb(); board_usb_init(gd->fdt_blob); #endif +#ifdef CONFIG_TEGRA2_LP0 + /* prepare the WB code to LP0 location */ + warmboot_prepare_code(TEGRA_LP0_ADDR, TEGRA_LP0_SIZE); +#endif + return 0; } diff --git a/board/nvidia/common/emc.c b/board/nvidia/common/emc.c new file mode 100644 index 0000000000..8e4290ceed --- /dev/null +++ b/board/nvidia/common/emc.c @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/ap20.h> +#include <asm/arch/clk_rst.h> +#include <asm/arch/clock.h> +#include <asm/arch/emc.h> +#include <asm/arch/pmu.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/tegra2.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* These rates are hard-coded for now, until fdt provides them */ +#define EMC_SDRAM_RATE_T20 (333000 * 2 * 1000) +#define EMC_SDRAM_RATE_T25 (380000 * 2 * 1000) + +int board_emc_init(void) +{ + unsigned rate; + + switch (tegra_get_chip_type()) { + default: + case TEGRA_SOC_T20: + rate = EMC_SDRAM_RATE_T20; + break; + case TEGRA_SOC_T25: + rate = EMC_SDRAM_RATE_T25; + break; + } + return tegra_set_emc(gd->fdt_blob, rate); +} diff --git a/board/nvidia/common/emc.h b/board/nvidia/common/emc.h new file mode 100644 index 0000000000..ec1b115f45 --- /dev/null +++ b/board/nvidia/common/emc.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * (C) Copyright 2010,2011 NVIDIA Corporation <www.nvidia.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _NVIDIA_EMC_H_ +#define _NVIDIA_EMC_H_ + +int board_emc_init(void); + +#endif diff --git a/board/nvidia/dts/tegra2-seaboard.dts b/board/nvidia/dts/tegra2-seaboard.dts index 6ba3ec48f1..335253953b 100644 --- a/board/nvidia/dts/tegra2-seaboard.dts +++ b/board/nvidia/dts/tegra2-seaboard.dts @@ -89,4 +89,68 @@ i2c@7000c500 { clock-frequency = <100000>; }; + + emc@7000f400 { + emc-table@190000 { + reg = < 190000 >; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = < 190000 >; + nvidia,emc-registers = < 0x0000000c 0x00000026 + 0x00000009 0x00000003 0x00000004 0x00000004 + 0x00000002 0x0000000c 0x00000003 0x00000003 + 0x00000002 0x00000001 0x00000004 0x00000005 + 0x00000004 0x00000009 0x0000000d 0x0000059f + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000003 0x00000001 0x0000000b 0x000000c8 + 0x00000003 0x00000007 0x00000004 0x0000000f + 0x00000002 0x00000000 0x00000000 0x00000002 + 0x00000000 0x00000000 0x00000083 0xa06204ae + 0x007dc010 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 >; + }; + emc-table@380000 { + reg = < 380000 >; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = < 380000 >; + nvidia,emc-registers = < 0x00000017 0x0000004b + 0x00000012 0x00000006 0x00000004 0x00000005 + 0x00000003 0x0000000c 0x00000006 0x00000006 + 0x00000003 0x00000001 0x00000004 0x00000005 + 0x00000004 0x00000009 0x0000000d 0x00000b5f + 0x00000000 0x00000003 0x00000003 0x00000006 + 0x00000006 0x00000001 0x00000011 0x000000c8 + 0x00000003 0x0000000e 0x00000007 0x0000000f + 0x00000002 0x00000000 0x00000000 0x00000002 + 0x00000000 0x00000000 0x00000083 0xe044048b + 0x007d8010 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 >; + }; + }; + + kbc@7000e200 { + linux,keymap = <0x00020011 0x0003001f 0x0004001e 0x0005002c + 0x000701d0 0x0107007d 0x02060064 0x02070038 0x03000006 + 0x03010005 0x03020013 0x03030012 0x03040021 0x03050020 + 0x0306002d 0x04000008 0x04010007 0x04020014 0x04030023 + 0x04040022 0x0405002f 0x0406002e 0x04070039 0x0500000a + 0x05010009 0x05020016 0x05030015 0x05040024 0x05050031 + 0x05060030 0x0507002b 0x0600000c 0x0601000b 0x06020018 + 0x06030017 0x06040026 0x06050025 0x06060033 0x06070032 + 0x0701000d 0x0702001b 0x0703001c 0x0707008b 0x08040036 + 0x0805002a 0x09050061 0x0907001d 0x0b00001a 0x0b010019 + 0x0b020028 0x0b030027 0x0b040035 0x0b050034 0x0c000044 + 0x0c010043 0x0c02000e 0x0c030004 0x0c040003 0x0c050067 + 0x0c0600d2 0x0c070077 0x0d00006e 0x0d01006f 0x0d030068 + 0x0d04006d 0x0d05006a 0x0d06006c 0x0d070069 0x0e000057 + 0x0e010058 0x0e020042 0x0e030010 0x0e04003e 0x0e05003d + 0x0e060002 0x0e070041 0x0f000001 0x0f010029 0x0f02003f + 0x0f03000f 0x0f04003b 0x0f05003c 0x0f06003a 0x0f070040 + 0x14000047 0x15000049 0x15010048 0x1502004b 0x1504004f + 0x16010062 0x1602004d 0x1603004c 0x16040051 0x16050050 + 0x16070052 0x1b010037 0x1b03004a 0x1b04004e 0x1b050053 + 0x1c050073 0x1d030066 0x1d04006b 0x1d0500e0 0x1d060072 + 0x1d0700e1 0x1e000045 0x1e010046 0x1e020071 + 0x1f04008a>; + linux,fn-keymap = <0x05040002>; + }; }; diff --git a/board/overo/overo.c b/board/overo/overo.c index 7b4064cdb1..f973870830 100644 --- a/board/overo/overo.c +++ b/board/overo/overo.c @@ -403,7 +403,7 @@ int board_eth_init(bd_t *bis) #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { - omap_mmc_init(0); + omap_mmc_init(0, 0, 0); return 0; } #endif diff --git a/board/pandora/pandora.c b/board/pandora/pandora.c index 58a676d455..3a62e9d633 100644 --- a/board/pandora/pandora.c +++ b/board/pandora/pandora.c @@ -32,6 +32,7 @@ #include <common.h> #include <twl4030.h> #include <asm/io.h> +#include <asm/gpio.h> #include <asm/arch/mmc_host_def.h> #include <asm/arch/mux.h> #include <asm/arch/gpio.h> @@ -45,6 +46,10 @@ DECLARE_GLOBAL_DATA_PTR; #define TWL4030_BB_CFG_BBSEL_3200MV (3 << 2) #define TWL4030_BB_CFG_BBISEL_500UA 2 +#define CONTROL_WKUP_CTRL 0x48002a5c +#define GPIO_IO_PWRDNZ (1 << 6) +#define PBIASLITEVMODE1 (1 << 8) + /* * Routine: board_init * Description: Early hardware init. @@ -60,29 +65,52 @@ int board_init(void) return 0; } +static void set_output_gpio(unsigned int gpio, int value) +{ + int ret; + + ret = gpio_request(gpio, ""); + if (ret != 0) { + printf("could not request GPIO %u\n", gpio); + return; + } + ret = gpio_direction_output(gpio, value); + if (ret != 0) + printf("could not set GPIO %u to %d\n", gpio, value); +} + /* * Routine: misc_init_r * Description: Configure board specific parts */ int misc_init_r(void) { - struct gpio *gpio1_base = (struct gpio *)OMAP34XX_GPIO1_BASE; - struct gpio *gpio4_base = (struct gpio *)OMAP34XX_GPIO4_BASE; - struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE; - struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE; + t2_t *t2_base = (t2_t *)T2_BASE; + u32 pbias_lite; twl4030_led_init(TWL4030_LED_LEDEN_LEDBON); - /* Configure GPIOs to output */ - writel(~(GPIO14 | GPIO15 | GPIO16 | GPIO23), &gpio1_base->oe); - writel(~GPIO22, &gpio4_base->oe); /* 118 */ - writel(~(GPIO0 | GPIO1 | GPIO28 | GPIO29 | GPIO30 | GPIO31), - &gpio5_base->oe); /* 128, 129, 156-159 */ - writel(~GPIO4, &gpio6_base->oe); /* 164 */ + /* set up dual-voltage GPIOs to 1.8V */ + pbias_lite = readl(&t2_base->pbias_lite); + pbias_lite &= ~PBIASLITEVMODE1; + pbias_lite |= PBIASLITEPWRDNZ1; + writel(pbias_lite, &t2_base->pbias_lite); + if (get_cpu_family() == CPU_OMAP36XX) + writel(readl(CONTROL_WKUP_CTRL) | GPIO_IO_PWRDNZ, + CONTROL_WKUP_CTRL); + + /* make sure audio and BT chips are in powerdown state */ + set_output_gpio(14, 0); + set_output_gpio(15, 0); + set_output_gpio(118, 0); + + /* enable USB supply */ + set_output_gpio(164, 1); - /* Set GPIOs */ - writel(GPIO28, &gpio5_base->setdataout); - writel(GPIO4, &gpio6_base->setdataout); + /* wifi needs a short pulse to enter powersave state */ + set_output_gpio(23, 1); + udelay(5000); + gpio_direction_output(23, 0); /* Enable battery backup capacitor (3.2V, 0.5mA charge current) */ twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, @@ -103,12 +131,15 @@ int misc_init_r(void) void set_muxconf_regs(void) { MUX_PANDORA(); + if (get_cpu_family() == CPU_OMAP36XX) { + MUX_PANDORA_3730(); + } } #ifdef CONFIG_GENERIC_MMC int board_mmc_init(bd_t *bis) { - omap_mmc_init(0); + omap_mmc_init(0, 0, 0); return 0; } #endif diff --git a/board/pandora/pandora.h b/board/pandora/pandora.h index f0ad16b0a4..fea8bf259a 100644 --- a/board/pandora/pandora.h +++ b/board/pandora/pandora.h @@ -399,4 +399,10 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\ MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /*sdrc_cke1*/ +#define MUX_PANDORA_3730() \ + MUX_VAL(CP(GPIO126), (IEN | PTD | DIS | M4)) /*GPIO_126 - MMC1_WP*/\ + MUX_VAL(CP(GPIO127), (IEN | PTD | DIS | M4)) /*GPIO_127 - MMC2_WP*/\ + MUX_VAL(CP(GPIO128), (IDIS | PTD | DIS | M4)) /*GPIO_128 - LED_MMC1*/\ + MUX_VAL(CP(GPIO129), (IDIS | PTD | DIS | M4)) /*GPIO_129 - LED_MMC2*/ + #endif diff --git a/board/raidsonic/ib62x0/Makefile b/board/raidsonic/ib62x0/Makefile new file mode 100644 index 0000000000..d450f8d0ab --- /dev/null +++ b/board/raidsonic/ib62x0/Makefile @@ -0,0 +1,43 @@ +# +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar <prafulla@marvell.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := ib62x0.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/raidsonic/ib62x0/ib62x0.c b/board/raidsonic/ib62x0/ib62x0.c new file mode 100644 index 0000000000..65f2c2ea6a --- /dev/null +++ b/board/raidsonic/ib62x0/ib62x0.c @@ -0,0 +1,79 @@ +/* + * Copyright (C) 2011-2012 + * Gerald Kerma <dreagle@doukki.net> + * Luka Perkov <uboot@lukaperkov.net> + * Simon Baatz <gmbnomis@gmail.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <common.h> +#include <miiphy.h> +#include <asm/arch/cpu.h> +#include <asm/arch/kirkwood.h> +#include <asm/arch/mpp.h> +#include "ib62x0.h" + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + /* + * default gpio configuration + * There are maximum 64 gpios controlled through 2 sets of registers + * the below configuration configures mainly initial LED status + */ + kw_config_gpio(IB62x0_OE_VAL_LOW, + IB62x0_OE_VAL_HIGH, + IB62x0_OE_LOW, IB62x0_OE_HIGH); + + /* Multi-Purpose Pins Functionality configuration */ + u32 kwmpp_config[] = { + MPP0_NF_IO2, + MPP1_NF_IO3, + MPP2_NF_IO4, + MPP3_NF_IO5, + MPP4_NF_IO6, + MPP5_NF_IO7, + MPP6_SYSRST_OUTn, + MPP8_TW_SDA, + MPP9_TW_SCK, + MPP10_UART0_TXD, + MPP11_UART0_RXD, + MPP18_NF_IO0, + MPP19_NF_IO1, + MPP20_SATA1_ACTn, + MPP21_SATA0_ACTn, + MPP22_GPIO, /* Power LED red */ + MPP24_GPIO, /* Power off device */ + MPP25_GPIO, /* Power LED green */ + MPP27_GPIO, /* USB transfer LED */ + MPP28_GPIO, /* Reset button */ + MPP29_GPIO, /* USB Copy button */ + 0 + }; + kirkwood_mpp_conf(kwmpp_config); + return 0; +} + +int board_init(void) +{ + /* adress of boot parameters */ + gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + + return 0; +} diff --git a/board/raidsonic/ib62x0/ib62x0.h b/board/raidsonic/ib62x0/ib62x0.h new file mode 100644 index 0000000000..0c30690697 --- /dev/null +++ b/board/raidsonic/ib62x0/ib62x0.h @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2011-2012 + * Gerald Kerma <dreagle@doukki.net> + * Simon Baatz <gmbnomis@gmail.com> + * Luka Perkov <uboot@lukaperkov.net> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef __IB62x0_H +#define __IB62x0_H + +#define IB62x0_OE_LOW (~(1 << 22 | 1 << 24 | 1 << 25 | 1 << 27)) +#define IB62x0_OE_HIGH (~(0)) +#define IB62x0_OE_VAL_LOW 0 +#define IB62x0_OE_VAL_HIGH 0 + +/* PHY related */ +#define MV88E1116_LED_FCTRL_REG 10 +#define MV88E1116_CPRSP_CR3_REG 21 +#define MV88E1116_MAC_CTRL_REG 21 +#define MV88E1116_PGADR_REG 22 +#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) +#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) + +#endif /* __IB62x0_H */ diff --git a/board/raidsonic/ib62x0/kwbimage.cfg b/board/raidsonic/ib62x0/kwbimage.cfg new file mode 100644 index 0000000000..bd594ebd5d --- /dev/null +++ b/board/raidsonic/ib62x0/kwbimage.cfg @@ -0,0 +1,169 @@ +# +# Copyright (C) 2011-2012 +# Gerald Kerma <dreagle@doukki.net> +# Simon Baatz <gmbnomis@gmail.com> +# Luka Perkov <uboot@lukaperkov.net> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# +# Refer docs/README.kwimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations +BOOT_FROM nand # change from nand to uart if building UART image +NAND_ECC_MODE default +NAND_PAGE_SIZE 0x0800 + +# SOC registers configuration using bootrom header extension +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed + +# Configure RGMII-0 interface pad voltage to 1.8V +DATA 0xffd100e0 0x1b1b1b9b + +#Dram initalization for SINGLE x16 CL=5 @ 400MHz +DATA 0xffd01400 0x43000c30 # DDR Configuration register +# bit13-0: 0xc30, (3120 DDR2 clks refresh rate) +# bit23-14: 0x0, +# bit24: 0x1, enable exit self refresh mode on DDR access +# bit25: 0x1, required +# bit29-26: 0x0, +# bit31-30: 0x1, + +DATA 0xffd01404 0x37543000 # DDR Controller Control Low +# bit4: 0x0, addr/cmd in smame cycle +# bit5: 0x0, clk is driven during self refresh, we don't care for APX +# bit6: 0x0, use recommended falling edge of clk for addr/cmd +# bit14: 0x0, input buffer always powered up +# bit18: 0x1, cpu lock transaction enabled +# bit23-20: 0x5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 +# bit27-24: 0x7, CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM +# bit30-28: 0x3, required +# bit31: 0x0, no additional STARTBURST delay + +DATA 0xffd01408 0x22125451 # DDR Timing (Low) (active cycles value +1) +# bit3-0: TRAS lsbs +# bit7-4: TRCD +# bit11-8: TRP +# bit15-12: TWR +# bit19-16: TWTR +# bit20: TRAS msb +# bit23-21: 0x0 +# bit27-24: TRRD +# bit31-28: TRTP + +DATA 0xffd0140c 0x00000a33 # DDR Timing (High) +# bit6-0: TRFC +# bit8-7: TR2R +# bit10-9: TR2W +# bit12-11: TW2W +# bit31-13: 0x0, required + +DATA 0xffd01410 0x0000000c # DDR Address Control +# bit1-0: 00, Cs0width (x8) +# bit3-2: 11, Cs0size (1Gb) +# bit5-4: 00, Cs1width (x8) +# bit7-6: 11, Cs1size (1Gb) +# bit9-8: 00, Cs2width (nonexistent +# bit11-10: 00, Cs2size (nonexistent +# bit13-12: 00, Cs3width (nonexistent +# bit15-14: 00, Cs3size (nonexistent +# bit16: 0, Cs0AddrSel +# bit17: 0, Cs1AddrSel +# bit18: 0, Cs2AddrSel +# bit19: 0, Cs3AddrSel +# bit31-20: 0x0, required + +DATA 0xffd01414 0x00000000 # DDR Open Pages Control +# bit0: 0, OpenPage enabled +# bit31-1: 0x0, required + +DATA 0xffd01418 0x00000000 # DDR Operation +# bit3-0: 0x0, DDR cmd +# bit31-4: 0x0, required + +DATA 0xffd0141c 0x00000c52 # DDR Mode +# bit2-0: 0x2, BurstLen=2 required +# bit3: 0x0, BurstType=0 required +# bit6-4: 0x4, CL=5 +# bit7: 0x0, TestMode=0 normal +# bit8: 0x0, DLL reset=0 normal +# bit11-9: 0x6, auto-precharge write recovery ???????????? +# bit12: 0x0, PD must be zero +# bit31-13: 0x0, required + +DATA 0xffd01420 0x00000040 # DDR Extended Mode +# bit0: 0, DDR DLL enabled +# bit1: 0, DDR drive strenght normal +# bit2: 1, DDR ODT control lsd (disabled) +# bit5-3: 0x0, required +# bit6: 0, DDR ODT control msb, (disabled) +# bit9-7: 0x0, required +# bit10: 0, differential DQS enabled +# bit11: 0, required +# bit12: 0, DDR output buffer enabled +# bit31-13: 0x0, required + +DATA 0xffd01424 0x0000f17f # DDR Controller Control High +# bit2-0: 0x7, required +# bit3: 0x1, MBUS Burst Chop disabled +# bit6-4: 0x7, required +# bit7: 0x0, +# bit8: 0x1, add writepath sample stage, must be 1 for DDR freq >= 300MHz +# bit9: 0x0, no half clock cycle addition to dataout +# bit10: 0x0, 1/4 clock cycle skew enabled for addr/ctl signals +# bit11: 0x0, 1/4 clock cycle skew disabled for write mesh +# bit15-12: 0xf, required +# bit31-16: 0, required + +DATA 0xffd01428 0x00085520 # DDR2 ODT Read Timing (default values) +DATA 0xffd0147c 0x00008552 # DDR2 ODT Write Timing (default values) + +DATA 0xffd01500 0x00000000 # CS[0]n Base address to 0x0 +DATA 0xffd01504 0x0ffffff1 # CS[0]n Size +# bit0: 0x1, Window enabled +# bit1: 0x0, Write Protect disabled +# bit3-2: 0x0, CS0 hit selected +# bit23-4: 0xfffff, required +# bit31-24: 0x0f, Size (i.e. 256MB) + +DATA 0xffd01508 0x10000000 # CS[1]n Base address to 256Mb +DATA 0xffd0150c 0x00000000 # CS[1]n Size, window disabled + +DATA 0xffd01514 0x00000000 # CS[2]n Size, window disabled +DATA 0xffd0151c 0x00000000 # CS[3]n Size, window disabled + +DATA 0xffd01494 0x00030000 # DDR ODT Control (Low) +# bit3-0: ODT0Rd, MODT[0] asserted during read from DRAM CS1 +# bit7-4: ODT0Rd, MODT[0] asserted during read from DRAM CS0 +# bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1 +# bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 + +DATA 0xffd01498 0x00000000 # DDR ODT Control (High) +# bit1-0: 0x0, ODT0 controlled by ODT Control (low) register above +# bit3-2: 0x1, ODT1 active NEVER! +# bit31-4: 0x0, required + +DATA 0xffd0149c 0x0000e803 # CPU ODT Control +DATA 0xffd01480 0x00000001 # DDR Initialization Control +# bit0: 0x1, enable DDR init upon this register write + +DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register +DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register + +# End of Header extension +DATA 0x0 0x0 diff --git a/board/samsung/smdk5250/tzpc_init.c b/board/samsung/smdk5250/tzpc_init.c index c2ccef3381..c833541fd0 100644 --- a/board/samsung/smdk5250/tzpc_init.c +++ b/board/samsung/smdk5250/tzpc_init.c @@ -28,11 +28,11 @@ /* Setting TZPC[TrustZone Protection Controller] */ void tzpc_init(void) { - struct exynos5_tzpc *tzpc; + struct exynos_tzpc *tzpc; unsigned int addr; for (addr = TZPC0_BASE; addr <= TZPC9_BASE; addr += TZPC_BASE_OFFSET) { - tzpc = (struct exynos5_tzpc *)addr; + tzpc = (struct exynos_tzpc *)addr; if (addr == TZPC0_BASE) writel(R0SIZE, &tzpc->r0size); diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c index aa4291df4a..3085de1a14 100644 --- a/board/samsung/trats/trats.c +++ b/board/samsung/trats/trats.c @@ -2,6 +2,7 @@ * Copyright (C) 2011 Samsung Electronics * Heungjun Kim <riverful.kim@samsung.com> * Kyungmin Park <kyungmin.park@samsung.com> + * Donghwa Lee <dh09.lee@samsung.com> * * See file CREDITS for list of people who contributed to this * project. @@ -23,16 +24,19 @@ */ #include <common.h> +#include <lcd.h> #include <asm/io.h> #include <asm/arch/cpu.h> #include <asm/arch/gpio.h> #include <asm/arch/mmc.h> #include <asm/arch/clock.h> +#include <asm/arch/clk.h> +#include <asm/arch/mipi_dsim.h> #include <asm/arch/watchdog.h> #include <asm/arch/power.h> #include <pmic.h> #include <usb/s3c_udc.h> -#include <max8998_pmic.h> +#include <max8997_pmic.h> #include "setup.h" @@ -216,26 +220,19 @@ static int s5pc210_phy_control(int on) return -1; if (on) { - ret |= pmic_set_output(p, - MAX8998_REG_BUCK_ACTIVE_DISCHARGE3, - MAX8998_SAFEOUT1, LDO_ON); - ret |= pmic_set_output(p, MAX8998_REG_ONOFF1, - MAX8998_LDO3, LDO_ON); - ret |= pmic_set_output(p, MAX8998_REG_ONOFF2, - MAX8998_LDO8, LDO_ON); - + ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL, + ENSAFEOUT1, LDO_ON); + ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, EN_LDO); + ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, EN_LDO); } else { - ret |= pmic_set_output(p, MAX8998_REG_ONOFF2, - MAX8998_LDO8, LDO_OFF); - ret |= pmic_set_output(p, MAX8998_REG_ONOFF1, - MAX8998_LDO3, LDO_OFF); - ret |= pmic_set_output(p, - MAX8998_REG_BUCK_ACTIVE_DISCHARGE3, - MAX8998_SAFEOUT1, LDO_OFF); + ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, DIS_LDO); + ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, DIS_LDO); + ret |= pmic_set_output(p, MAX8997_REG_SAFEOUTCTRL, + ENSAFEOUT1, LDO_OFF); } if (ret) { - puts("MAX8998 LDO setting error!\n"); + puts("MAX8997 LDO setting error!\n"); return -1; } @@ -364,3 +361,145 @@ int board_early_init_f(void) return 0; } + +static void lcd_reset(void) +{ + struct exynos4_gpio_part2 *gpio2 = + (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); + + s5p_gpio_direction_output(&gpio2->y4, 5, 1); + udelay(10000); + s5p_gpio_direction_output(&gpio2->y4, 5, 0); + udelay(10000); + s5p_gpio_direction_output(&gpio2->y4, 5, 1); +} + +static int lcd_power(void) +{ + int ret = 0; + struct pmic *p = get_pmic(); + + if (pmic_probe(p)) + return 0; + + /* LDO15 voltage: 2.2v */ + ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, 0x1c | EN_LDO); + /* LDO13 voltage: 3.0v */ + ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, 0x2c | EN_LDO); + + if (ret) { + puts("MAX8997 LDO setting error!\n"); + return -1; + } + + return 0; +} + +static struct mipi_dsim_config dsim_config = { + .e_interface = DSIM_VIDEO, + .e_virtual_ch = DSIM_VIRTUAL_CH_0, + .e_pixel_format = DSIM_24BPP_888, + .e_burst_mode = DSIM_BURST_SYNC_EVENT, + .e_no_data_lane = DSIM_DATA_LANE_4, + .e_byte_clk = DSIM_PLL_OUT_DIV8, + .hfp = 1, + + .p = 3, + .m = 120, + .s = 1, + + /* D-PHY PLL stable time spec :min = 200usec ~ max 400usec */ + .pll_stable_time = 500, + + /* escape clk : 10MHz */ + .esc_clk = 20 * 1000000, + + /* stop state holding counter after bta change count 0 ~ 0xfff */ + .stop_holding_cnt = 0x7ff, + /* bta timeout 0 ~ 0xff */ + .bta_timeout = 0xff, + /* lp rx timeout 0 ~ 0xffff */ + .rx_timeout = 0xffff, +}; + +static struct exynos_platform_mipi_dsim s6e8ax0_platform_data = { + .lcd_panel_info = NULL, + .dsim_config = &dsim_config, +}; + +static struct mipi_dsim_lcd_device mipi_lcd_device = { + .name = "s6e8ax0", + .id = -1, + .bus_id = 0, + .platform_data = (void *)&s6e8ax0_platform_data, +}; + +static int mipi_power(void) +{ + int ret = 0; + struct pmic *p = get_pmic(); + + if (pmic_probe(p)) + return 0; + + /* LDO3 voltage: 1.1v */ + ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, 0x6 | EN_LDO); + /* LDO4 voltage: 1.8v */ + ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, 0x14 | EN_LDO); + + if (ret) { + puts("MAX8997 LDO setting error!\n"); + return -1; + } + + return 0; +} + +void init_panel_info(vidinfo_t *vid) +{ + vid->vl_freq = 60; + vid->vl_col = 720; + vid->vl_row = 1280; + vid->vl_width = 720; + vid->vl_height = 1280; + vid->vl_clkp = CONFIG_SYS_HIGH; + vid->vl_hsp = CONFIG_SYS_LOW; + vid->vl_vsp = CONFIG_SYS_LOW; + vid->vl_dp = CONFIG_SYS_LOW; + + vid->vl_bpix = 5; + vid->dual_lcd_enabled = 0; + + /* s6e8ax0 Panel */ + vid->vl_hspw = 5; + vid->vl_hbpd = 10; + vid->vl_hfpd = 10; + + vid->vl_vspw = 2; + vid->vl_vbpd = 1; + vid->vl_vfpd = 13; + vid->vl_cmd_allow_len = 0xf; + + vid->win_id = 3; + vid->cfg_gpio = NULL; + vid->backlight_on = NULL; + vid->lcd_power_on = NULL; /* lcd_power_on in mipi dsi driver */ + vid->reset_lcd = lcd_reset; + + vid->init_delay = 0; + vid->power_on_delay = 0; + vid->reset_delay = 0; + vid->interface_mode = FIMD_RGB_INTERFACE; + vid->mipi_enabled = 1; + + strcpy(s6e8ax0_platform_data.lcd_panel_name, mipi_lcd_device.name); + s6e8ax0_platform_data.lcd_power = lcd_power; + s6e8ax0_platform_data.mipi_power = mipi_power; + s6e8ax0_platform_data.phy_enable = set_mipi_phy_ctrl; + s6e8ax0_platform_data.lcd_panel_info = (void *)vid; + exynos_mipi_dsi_register_lcd_device(&mipi_lcd_device); + s6e8ax0_init(); + exynos_set_dsim_platform_data(&s6e8ax0_platform_data); + + setenv("lcdinfo", "lcd=s6e8ax0"); +} diff --git a/board/samsung/universal_c210/universal.c b/board/samsung/universal_c210/universal.c index d0ff8341f6..90fff5cf5e 100644 --- a/board/samsung/universal_c210/universal.c +++ b/board/samsung/universal_c210/universal.c @@ -58,13 +58,13 @@ int board_init(void) gd->bd->bi_arch_number = MACH_TYPE_UNIVERSAL_C210; gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; - check_hw_revision(); - printf("HW Revision:\t0x%x\n", board_rev); - #if defined(CONFIG_PMIC) pmic_init(); #endif + check_hw_revision(); + printf("HW Revision:\t0x%x\n", board_rev); + return 0; } @@ -109,10 +109,27 @@ static unsigned short get_adc_value(int channel) return ret; } +static int adc_power_control(int on) +{ + int ret; + struct pmic *p = get_pmic(); + + if (pmic_probe(p)) + return -1; + + ret = pmic_set_output(p, + MAX8998_REG_ONOFF1, + MAX8998_LDO4, !!on); + + return ret; +} + static unsigned int get_hw_revision(void) { int hwrev, mode0, mode1; + adc_power_control(1); + mode0 = get_adc_value(1); /* HWREV_MODE0 */ mode1 = get_adc_value(2); /* HWREV_MODE1 */ @@ -135,6 +152,8 @@ static unsigned int get_hw_revision(void) debug("mode0: %d, mode1: %d, hwrev 0x%x\n", mode0, mode1, hwrev); + adc_power_control(0); + return hwrev; } diff --git a/board/technexion/twister/twister.c b/board/technexion/twister/twister.c index b92758692d..c2b10ac1ea 100644 --- a/board/technexion/twister/twister.c +++ b/board/technexion/twister/twister.c @@ -133,7 +133,7 @@ int board_eth_init(bd_t *bis) !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { - return omap_mmc_init(0); + return omap_mmc_init(0, 0, 0); } #endif diff --git a/board/teejet/mt_ventoux/mt_ventoux.c b/board/teejet/mt_ventoux/mt_ventoux.c index c5eb42c362..9fbaedd792 100644 --- a/board/teejet/mt_ventoux/mt_ventoux.c +++ b/board/teejet/mt_ventoux/mt_ventoux.c @@ -196,13 +196,6 @@ int board_init(void) return 0; } -int misc_init_r(void) -{ - dieid_num_r(); - - return 0; -} - /* * Routine: set_muxconf_regs * Description: Setting up the configuration Mux registers specific to the @@ -228,6 +221,6 @@ int board_eth_init(bd_t *bis) !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { - return omap_mmc_init(0); + return omap_mmc_init(0, 0, 0); } #endif diff --git a/board/ti/am3517crane/am3517crane.c b/board/ti/am3517crane/am3517crane.c index 436645a83f..888398deac 100644 --- a/board/ti/am3517crane/am3517crane.c +++ b/board/ti/am3517crane/am3517crane.c @@ -78,7 +78,7 @@ void set_muxconf_regs(void) #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { - omap_mmc_init(0); + omap_mmc_init(0, 0, 0); return 0; } #endif diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c index e26b387934..9edd3c5c4f 100644 --- a/board/ti/beagle/beagle.c +++ b/board/ti/beagle/beagle.c @@ -477,7 +477,7 @@ void set_muxconf_regs(void) #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { - omap_mmc_init(0); + omap_mmc_init(0, 0, 0); return 0; } #endif diff --git a/board/ti/evm/evm.c b/board/ti/evm/evm.c index 8497aee6de..61fc7b5531 100644 --- a/board/ti/evm/evm.c +++ b/board/ti/evm/evm.c @@ -278,7 +278,7 @@ int board_eth_init(bd_t *bis) #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { - omap_mmc_init(0); + omap_mmc_init(0, 0, 0); return 0; } #endif diff --git a/board/ti/omap5912osk/omap5912osk.c b/board/ti/omap5912osk/omap5912osk.c index 6f0e763f01..fac683a7e6 100644 --- a/board/ti/omap5912osk/omap5912osk.c +++ b/board/ti/omap5912osk/omap5912osk.c @@ -81,13 +81,6 @@ int board_init (void) return 0; } - -int misc_init_r (void) -{ - /* currently empty */ - return (0); -} - /****************************** Routine: Description: diff --git a/board/ti/omap5_evm/evm.c b/board/ti/omap5_evm/evm.c index ea0cb13b43..c8dfdf8142 100644 --- a/board/ti/omap5_evm/evm.c +++ b/board/ti/omap5_evm/evm.c @@ -23,7 +23,7 @@ * MA 02111-1307 USA */ #include <common.h> -#include <twl6030.h> +#include <twl6035.h> #include <asm/arch/sys_proto.h> #include <asm/arch/mmc_host_def.h> @@ -63,8 +63,8 @@ int board_eth_init(bd_t *bis) */ int misc_init_r(void) { -#ifdef CONFIG_TWL6030_POWER - twl6030_init_battery_charging(); +#ifdef CONFIG_TWL6035_POWER + twl6035_init_settings(); #endif return 0; } @@ -94,8 +94,8 @@ void set_muxconf_regs_non_essential(void) #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) int board_mmc_init(bd_t *bis) { - omap_mmc_init(0); - omap_mmc_init(1); + omap_mmc_init(0, 0, 0); + omap_mmc_init(1, 0, 0); return 0; } #endif diff --git a/board/ti/omap5_evm/mux_data.h b/board/ti/omap5_evm/mux_data.h index 18f4729257..296eb682e1 100644 --- a/board/ti/omap5_evm/mux_data.h +++ b/board/ti/omap5_evm/mux_data.h @@ -2,8 +2,7 @@ * (C) Copyright 2010 * Texas Instruments Incorporated, <www.ti.com> * - * Balaji Krishnamoorthy <balajitk@ti.com> - * Aneesh V <aneesh@ti.com> + * Sricharan R <r.sricharan@ti.com> * * See file CREDITS for list of people who contributed to this * project. @@ -30,246 +29,276 @@ const struct pad_conf_entry core_padconf_array_essential[] = { -{GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */ -{GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */ -{GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */ -{GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */ -{GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */ -{GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */ -{GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */ -{GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */ -{GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)}, /* sdmmc2_clk */ -{GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_cmd */ -{SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc1_clk */ -{SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */ -{SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */ -{SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */ -{SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */ -{SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */ -{SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat4 */ -{SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat5 */ -{SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat6 */ -{SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat7 */ -{UART3_CTS_RCTX, (PTU | IEN | M0)}, /* uart3_tx */ -{UART3_RTS_SD, (M0)}, /* uart3_rts_sd */ -{UART3_RX_IRRX, (IEN | M0)}, /* uart3_rx */ -{UART3_TX_IRTX, (M0)} /* uart3_tx */ + {EMMC_CLK, (PTU | IEN | M0)}, /* EMMC_CLK */ + {EMMC_CMD, (PTU | IEN | M0)}, /* EMMC_CMD */ + {EMMC_DATA0, (PTU | IEN | M0)}, /* EMMC_DATA0 */ + {EMMC_DATA1, (PTU | IEN | M0)}, /* EMMC_DATA1 */ + {EMMC_DATA2, (PTU | IEN | M0)}, /* EMMC_DATA2 */ + {EMMC_DATA3, (PTU | IEN | M0)}, /* EMMC_DATA3 */ + {EMMC_DATA4, (PTU | IEN | M0)}, /* EMMC_DATA4 */ + {EMMC_DATA5, (PTU | IEN | M0)}, /* EMMC_DATA5 */ + {EMMC_DATA6, (PTU | IEN | M0)}, /* EMMC_DATA6 */ + {EMMC_DATA7, (PTU | IEN | M0)}, /* EMMC_DATA7 */ + {SDCARD_CLK, (PTU | IEN | M0)}, /* SDCARD_CLK */ + {SDCARD_CMD, (PTU | IEN | M0)}, /* SDCARD_CMD */ + {SDCARD_DATA0, (PTU | IEN | M0)}, /* SDCARD_DATA0*/ + {SDCARD_DATA1, (PTU | IEN | M0)}, /* SDCARD_DATA1*/ + {SDCARD_DATA2, (PTU | IEN | M0)}, /* SDCARD_DATA2*/ + {SDCARD_DATA3, (PTU | IEN | M0)}, /* SDCARD_DATA3*/ + {UART3_RX_IRRX, (PTU | IEN | M0)}, /* UART3_RX_IRRX */ + {UART3_TX_IRTX, (M0)}, /* UART3_TX_IRTX */ }; const struct pad_conf_entry wkup_padconf_array_essential[] = { -{PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */ -{PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */ -{PAD1_SYS_32K, (IEN | M0)} /* sys_32k */ + {SR_PMIC_SCL, (PTU | IEN | M0)}, /* SR_PMIC_SCL */ + {SR_PMIC_SDA, (PTU | IEN | M0)}, /* SR_PMIC_SDA */ + {SYS_32K, (IEN | M0)}, /* SYS_32K */ }; const struct pad_conf_entry core_padconf_array_non_essential[] = { - {GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* gpio_32 */ - {GPMC_AD9, (PTU | IEN | M3)}, /* gpio_33 */ - {GPMC_AD10, (PTU | IEN | M3)}, /* gpio_34 */ - {GPMC_AD11, (PTU | IEN | M3)}, /* gpio_35 */ - {GPMC_AD12, (PTU | IEN | M3)}, /* gpio_36 */ - {GPMC_AD13, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_37 */ - {GPMC_AD14, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_38 */ - {GPMC_AD15, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_39 */ - {GPMC_A16, (M3)}, /* gpio_40 */ - {GPMC_A17, (PTD | M3)}, /* gpio_41 */ - {GPMC_A18, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row6 */ - {GPMC_A19, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row7 */ - {GPMC_A20, (IEN | M3)}, /* gpio_44 */ - {GPMC_A21, (M3)}, /* gpio_45 */ - {GPMC_A22, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col6 */ - {GPMC_A23, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col7 */ - {GPMC_A24, (PTD | M3)}, /* gpio_48 */ - {GPMC_A25, (PTD | M3)}, /* gpio_49 */ - {GPMC_NCS0, (M3)}, /* gpio_50 */ - {GPMC_NCS1, (IEN | M3)}, /* gpio_51 */ - {GPMC_NCS2, (IEN | M3)}, /* gpio_52 */ - {GPMC_NCS3, (IEN | M3)}, /* gpio_53 */ - {GPMC_NWP, (M3)}, /* gpio_54 */ - {GPMC_CLK, (PTD | M3)}, /* gpio_55 */ - {GPMC_NADV_ALE, (M3)}, /* gpio_56 */ - {GPMC_NBE0_CLE, (M3)}, /* gpio_59 */ - {GPMC_NBE1, (PTD | M3)}, /* gpio_60 */ - {GPMC_WAIT0, (PTU | IEN | M3)}, /* gpio_61 */ - {GPMC_WAIT1, (IEN | M3)}, /* gpio_62 */ - {C2C_DATA11, (PTD | M3)}, /* gpio_100 */ - {C2C_DATA12, (M1)}, /* dsi1_te0 */ - {C2C_DATA13, (PTD | M3)}, /* gpio_102 */ - {C2C_DATA14, (M1)}, /* dsi2_te0 */ - {C2C_DATA15, (PTD | M3)}, /* gpio_104 */ - {HDMI_HPD, (M0)}, /* hdmi_hpd */ - {HDMI_CEC, (M0)}, /* hdmi_cec */ - {HDMI_DDC_SCL, (PTU | M0)}, /* hdmi_ddc_scl */ - {HDMI_DDC_SDA, (PTU | IEN | M0)}, /* hdmi_ddc_sda */ - {CSI21_DX0, (IEN | M0)}, /* csi21_dx0 */ - {CSI21_DY0, (IEN | M0)}, /* csi21_dy0 */ - {CSI21_DX1, (IEN | M0)}, /* csi21_dx1 */ - {CSI21_DY1, (IEN | M0)}, /* csi21_dy1 */ - {CSI21_DX2, (IEN | M0)}, /* csi21_dx2 */ - {CSI21_DY2, (IEN | M0)}, /* csi21_dy2 */ - {CSI21_DX3, (PTD | M7)}, /* csi21_dx3 */ - {CSI21_DY3, (PTD | M7)}, /* csi21_dy3 */ - {CSI21_DX4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)}, /* csi21_dx4 */ - {CSI21_DY4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)}, /* csi21_dy4 */ - {CSI22_DX0, (IEN | M0)}, /* csi22_dx0 */ - {CSI22_DY0, (IEN | M0)}, /* csi22_dy0 */ - {CSI22_DX1, (IEN | M0)}, /* csi22_dx1 */ - {CSI22_DY1, (IEN | M0)}, /* csi22_dy1 */ - {CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_shutter */ - {CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_strobe */ - {CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_83 */ - {USBB1_ULPITLL_CLK, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_cawake */ - {USBB1_ULPITLL_STP, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_cadata */ - {USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_caflag */ - {USBB1_ULPITLL_NXT, (OFF_EN | M1)}, /* hsi1_acready */ - {USBB1_ULPITLL_DAT0, (OFF_EN | M1)}, /* hsi1_acwake */ - {USBB1_ULPITLL_DAT1, (OFF_EN | M1)}, /* hsi1_acdata */ - {USBB1_ULPITLL_DAT2, (OFF_EN | M1)}, /* hsi1_acflag */ - {USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_caready */ - {USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat4 */ - {USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat5 */ - {USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat6 */ - {USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat7 */ - {USBB1_HSIC_DATA, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_data */ - {USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_strobe */ - {USBC1_ICUSB_DP, (IEN | M0)}, /* usbc1_icusb_dp */ - {USBC1_ICUSB_DM, (IEN | M0)}, /* usbc1_icusb_dm */ - {ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_clkx */ - {ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dr */ - {ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dx */ - {ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_fsx */ - {ABE_MCBSP1_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp1_clkx */ - {ABE_MCBSP1_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp1_dr */ - {ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp1_dx */ - {ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp1_fsx */ - {ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_ul_data */ - {ABE_PDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_dl_data */ - {ABE_PDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_frame */ - {ABE_PDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_lb_clk */ - {ABE_CLKS, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_clks */ - {ABE_DMIC_CLK1, (M0)}, /* abe_dmic_clk1 */ - {ABE_DMIC_DIN1, (IEN | M0)}, /* abe_dmic_din1 */ - {ABE_DMIC_DIN2, (IEN | M0)}, /* abe_dmic_din2 */ - {ABE_DMIC_DIN3, (IEN | M0)}, /* abe_dmic_din3 */ - {UART2_CTS, (PTU | IEN | M0)}, /* uart2_cts */ - {UART2_RTS, (M0)}, /* uart2_rts */ - {UART2_RX, (PTU | IEN | M0)}, /* uart2_rx */ - {UART2_TX, (M0)}, /* uart2_tx */ - {HDQ_SIO, (M3)}, /* gpio_127 */ - {MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_clk */ - {MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_somi */ - {MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_simo */ - {MCSPI1_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_cs0 */ - {MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* mcspi1_cs1 */ - {MCSPI1_CS2, (PTU | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_139 */ - {MCSPI1_CS3, (PTU | IEN | M3)}, /* gpio_140 */ - {SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc5_clk */ - {SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_cmd */ - {SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat0 */ - {SDMMC5_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat1 */ - {SDMMC5_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat2 */ - {SDMMC5_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat3 */ - {MCSPI4_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_clk */ - {MCSPI4_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_simo */ - {MCSPI4_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_somi */ - {MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_cs0 */ - {UART4_RX, (IEN | M0)}, /* uart4_rx */ - {UART4_TX, (M0)}, /* uart4_tx */ - {USBB2_ULPITLL_CLK, (PTD | IEN | M3)}, /* gpio_157 */ - {USBB2_ULPITLL_STP, (IEN | M5)}, /* dispc2_data23 */ - {USBB2_ULPITLL_DIR, (IEN | M5)}, /* dispc2_data22 */ - {USBB2_ULPITLL_NXT, (IEN | M5)}, /* dispc2_data21 */ - {USBB2_ULPITLL_DAT0, (IEN | M5)}, /* dispc2_data20 */ - {USBB2_ULPITLL_DAT1, (IEN | M5)}, /* dispc2_data19 */ - {USBB2_ULPITLL_DAT2, (IEN | M5)}, /* dispc2_data18 */ - {USBB2_ULPITLL_DAT3, (IEN | M5)}, /* dispc2_data15 */ - {USBB2_ULPITLL_DAT4, (IEN | M5)}, /* dispc2_data14 */ - {USBB2_ULPITLL_DAT5, (IEN | M5)}, /* dispc2_data13 */ - {USBB2_ULPITLL_DAT6, (IEN | M5)}, /* dispc2_data12 */ - {USBB2_ULPITLL_DAT7, (IEN | M5)}, /* dispc2_data11 */ - {USBB2_HSIC_DATA, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_169 */ - {USBB2_HSIC_STROBE, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_170 */ - {UNIPRO_TX0, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col0 */ - {UNIPRO_TY0, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col1 */ - {UNIPRO_TX1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col2 */ - {UNIPRO_TY1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col3 */ - {UNIPRO_TX2, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col4 */ - {UNIPRO_TY2, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col5 */ - {UNIPRO_RX0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row0 */ - {UNIPRO_RY0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row1 */ - {UNIPRO_RX1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row2 */ - {UNIPRO_RY1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row3 */ - {UNIPRO_RX2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row4 */ - {UNIPRO_RY2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row5 */ - {USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* usba0_otg_ce */ - {USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dp */ - {USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dm */ - {FREF_CLK1_OUT, (M0)}, /* fref_clk1_out */ - {FREF_CLK2_OUT, (M0)}, /* fref_clk2_out */ - {SYS_NIRQ1, (PTU | IEN | M0)}, /* sys_nirq1 */ - {SYS_NIRQ2, (M7)}, /* sys_nirq2 */ - {SYS_BOOT0, (PTU | IEN | M3)}, /* gpio_184 */ - {SYS_BOOT1, (M3)}, /* gpio_185 */ - {SYS_BOOT2, (PTD | IEN | M3)}, /* gpio_186 */ - {SYS_BOOT3, (PTD | IEN | M3)}, /* gpio_187 */ - {SYS_BOOT4, (M3)}, /* gpio_188 */ - {SYS_BOOT5, (PTD | IEN | M3)}, /* gpio_189 */ - {DPM_EMU0, (IEN | M0)}, /* dpm_emu0 */ - {DPM_EMU1, (IEN | M0)}, /* dpm_emu1 */ - {DPM_EMU2, (IEN | M0)}, /* dpm_emu2 */ - {DPM_EMU3, (IEN | M5)}, /* dispc2_data10 */ - {DPM_EMU4, (IEN | M5)}, /* dispc2_data9 */ - {DPM_EMU5, (IEN | M5)}, /* dispc2_data16 */ - {DPM_EMU6, (IEN | M5)}, /* dispc2_data17 */ - {DPM_EMU7, (IEN | M5)}, /* dispc2_hsync */ - {DPM_EMU8, (IEN | M5)}, /* dispc2_pclk */ - {DPM_EMU9, (IEN | M5)}, /* dispc2_vsync */ - {DPM_EMU10, (IEN | M5)}, /* dispc2_de */ - {DPM_EMU11, (IEN | M5)}, /* dispc2_data8 */ - {DPM_EMU12, (IEN | M5)}, /* dispc2_data7 */ - {DPM_EMU13, (IEN | M5)}, /* dispc2_data6 */ - {DPM_EMU14, (IEN | M5)}, /* dispc2_data5 */ - {DPM_EMU15, (IEN | M5)}, /* dispc2_data4 */ - {DPM_EMU16, (M3)}, /* gpio_27 */ - {DPM_EMU17, (IEN | M5)}, /* dispc2_data2 */ - {DPM_EMU18, (IEN | M5)}, /* dispc2_data1 */ - {DPM_EMU19, (IEN | M5)}, /* dispc2_data0 */ - {I2C1_SCL, (PTU | IEN | M0)}, /* i2c1_scl */ - {I2C1_SDA, (PTU | IEN | M0)}, /* i2c1_sda */ - {I2C2_SCL, (PTU | IEN | M0)}, /* i2c2_scl */ - {I2C2_SDA, (PTU | IEN | M0)}, /* i2c2_sda */ - {I2C3_SCL, (PTU | IEN | M0)}, /* i2c3_scl */ - {I2C3_SDA, (PTU | IEN | M0)}, /* i2c3_sda */ - {I2C4_SCL, (PTU | IEN | M0)}, /* i2c4_scl */ - {I2C4_SDA, (PTU | IEN | M0)} /* i2c4_sda */ + + {C2C_DATAIN0, (IEN | M0)}, /* C2C_DATAIN0 */ + {C2C_DATAIN1, (IEN | M0)}, /* C2C_DATAIN1 */ + {C2C_DATAIN2, (IEN | M0)}, /* C2C_DATAIN2 */ + {C2C_DATAIN3, (IEN | M0)}, /* C2C_DATAIN3 */ + {C2C_DATAIN4, (IEN | M0)}, /* C2C_DATAIN4 */ + {C2C_DATAIN5, (IEN | M0)}, /* C2C_DATAIN5 */ + {C2C_DATAIN6, (IEN | M0)}, /* C2C_DATAIN6 */ + {C2C_DATAIN7, (IEN | M0)}, /* C2C_DATAIN7 */ + {C2C_CLKIN1, (IEN | M0)}, /* C2C_CLKIN1 */ + {C2C_CLKIN0, (IEN | M0)}, /* C2C_CLKIN0 */ + {C2C_CLKOUT0, (M0)}, /* C2C_CLKOUT0 */ + {C2C_CLKOUT1, (M0)}, /* C2C_CLKOUT1 */ + {C2C_DATAOUT0, (M0)}, /* C2C_DATAOUT0 */ + {C2C_DATAOUT1, (M0)}, /* C2C_DATAOUT1 */ + {C2C_DATAOUT2, (M0)}, /* C2C_DATAOUT2 */ + {C2C_DATAOUT3, (M0)}, /* C2C_DATAOUT3 */ + {C2C_DATAOUT4, (M0)}, /* C2C_DATAOUT4 */ + {C2C_DATAOUT5, (M0)}, /* C2C_DATAOUT5 */ + {C2C_DATAOUT6, (M0)}, /* C2C_DATAOUT6 */ + {C2C_DATAOUT7, (M0)}, /* C2C_DATAOUT7 */ + {C2C_DATA8, (IEN | M0)}, /* C2C_DATA8 */ + {C2C_DATA9, (IEN | M0)}, /* C2C_DATA9 */ + {C2C_DATA10, (IEN | M0)}, /* C2C_DATA10 */ + {C2C_DATA11, (IEN | M0)}, /* C2C_DATA11 */ + {C2C_DATA12, (IEN | M0)}, /* C2C_DATA12 */ + {C2C_DATA13, (IEN | M0)}, /* C2C_DATA13 */ + {C2C_DATA14, (IEN | M0)}, /* C2C_DATA14 */ + {C2C_DATA15, (IEN | M0)}, /* C2C_DATA15 */ + {LLIB_WAKEREQOUT, (PTU | IEN | M6)}, /* GPIO2_32 */ + {LLIA_WAKEREQOUT, (M1)}, /* C2C_WAKEREQOUT */ + {HSI1_ACREADY, (PTD | M6)}, /* GPIO3_64 */ + {HSI1_CAREADY, (PTD | M6)}, /* GPIO3_65 */ + {HSI1_ACWAKE, (PTD | IEN | M6)}, /* GPIO3_66 */ + {HSI1_CAWAKE, (PTU | IEN | M6)}, /* GPIO3_67 */ + {HSI1_ACFLAG, (PTD | IEN | M6)}, /* GPIO3_68 */ + {HSI1_ACDATA, (PTD | M6)}, /* GPIO3_69 */ + {HSI1_CAFLAG, (M6)}, /* GPIO3_70 */ + {HSI1_CADATA, (M6)}, /* GPIO3_71 */ + {UART1_TX, (M0)}, /* UART1_TX */ + {UART1_CTS, (PTU | IEN | M0)}, /* UART1_CTS */ + {UART1_RX, (PTU | IEN | M0)}, /* UART1_RX */ + {UART1_RTS, (M0)}, /* UART1_RTS */ + {HSI2_CAREADY, (IEN | M0)}, /* HSI2_CAREADY */ + {HSI2_ACREADY, (OFF_EN | M0)}, /* HSI2_ACREADY */ + {HSI2_CAWAKE, (IEN | PTD | M0)}, /* HSI2_CAWAKE */ + {HSI2_ACWAKE, (M0)}, /* HSI2_ACWAKE */ + {HSI2_CAFLAG, (IEN | PTD | M0)}, /* HSI2_CAFLAG */ + {HSI2_CADATA, (IEN | PTD | M0)}, /* HSI2_CADATA */ + {HSI2_ACFLAG, (M0)}, /* HSI2_ACFLAG */ + {HSI2_ACDATA, (M0)}, /* HSI2_ACDATA */ + {UART2_RTS, (IEN | M1)}, /* MCSPI3_SOMI */ + {UART2_CTS, (IEN | M1)}, /* MCSPI3_CS0 */ + {UART2_RX, (IEN | M1)}, /* MCSPI3_SIMO */ + {UART2_TX, (IEN | M1)}, /* MCSPI3_CLK */ + {USBB1_HSIC_STROBE, (PTU | IEN | M0)}, /* USBB1_HSIC_STROBE */ + {USBB1_HSIC_DATA, (PTU | IEN | M0)}, /* USBB1_HSIC_DATA */ + {USBB2_HSIC_STROBE, (PTU | IEN | M0)}, /* USBB2_HSIC_STROBE */ + {USBB2_HSIC_DATA, (PTU | IEN | M0)}, /* USBB2_HSIC_DATA */ + {TIMER10_PWM_EVT, (IEN | M0)}, /* TIMER10_PWM_EVT */ + {DSIPORTA_TE0, (IEN | M0)}, /* DSIPORTA_TE0 */ + {DSIPORTA_LANE0X, (IEN | M0)}, /* DSIPORTA_LANE0X */ + {DSIPORTA_LANE0Y, (IEN | M0)}, /* DSIPORTA_LANE0Y */ + {DSIPORTA_LANE1X, (IEN | M0)}, /* DSIPORTA_LANE1X */ + {DSIPORTA_LANE1Y, (IEN | M0)}, /* DSIPORTA_LANE1Y */ + {DSIPORTA_LANE2X, (IEN | M0)}, /* DSIPORTA_LANE2X */ + {DSIPORTA_LANE2Y, (IEN | M0)}, /* DSIPORTA_LANE2Y */ + {DSIPORTA_LANE3X, (IEN | M0)}, /* DSIPORTA_LANE3X */ + {DSIPORTA_LANE3Y, (IEN | M0)}, /* DSIPORTA_LANE3Y */ + {DSIPORTA_LANE4X, (IEN | M0)}, /* DSIPORTA_LANE4X */ + {DSIPORTA_LANE4Y, (IEN | M0)}, /* DSIPORTA_LANE4Y */ + {TIMER9_PWM_EVT, (IEN | M0)}, /* TIMER9_PWM_EVT */ + {DSIPORTC_TE0, (IEN | M0)}, /* DSIPORTC_TE0 */ + {DSIPORTC_LANE0X, (IEN | M0)}, /* DSIPORTC_LANE0X */ + {DSIPORTC_LANE0Y, (IEN | M0)}, /* DSIPORTC_LANE0Y */ + {DSIPORTC_LANE1X, (IEN | M0)}, /* DSIPORTC_LANE1X */ + {DSIPORTC_LANE1Y, (IEN | M0)}, /* DSIPORTC_LANE1Y */ + {DSIPORTC_LANE2X, (IEN | M0)}, /* DSIPORTC_LANE2X */ + {DSIPORTC_LANE2Y, (IEN | M0)}, /* DSIPORTC_LANE2Y */ + {DSIPORTC_LANE3X, (IEN | M0)}, /* DSIPORTC_LANE3X */ + {DSIPORTC_LANE3Y, (IEN | M0)}, /* DSIPORTC_LANE3Y */ + {DSIPORTC_LANE4X, (IEN | M0)}, /* DSIPORTC_LANE4X */ + {DSIPORTC_LANE4Y, (IEN | M0)}, /* DSIPORTC_LANE4Y */ + {RFBI_HSYNC0, (M4)}, /* KBD_COL5 */ + {RFBI_TE_VSYNC0, (PTD | M6)}, /* GPIO6_161 */ + {RFBI_RE, (M4)}, /* KBD_COL4 */ + {RFBI_A0, (PTD | IEN | M6)}, /* GPIO6_165 */ + {RFBI_DATA8, (M4)}, /* KBD_COL3 */ + {RFBI_DATA9, (PTD | M6)}, /* GPIO6_175 */ + {RFBI_DATA10, (PTD | M6)}, /* GPIO6_176 */ + {RFBI_DATA11, (PTD | M6)}, /* GPIO6_177 */ + {RFBI_DATA12, (PTD | M6)}, /* GPIO6_178 */ + {RFBI_DATA13, (PTU | IEN | M6)}, /* GPIO6_179 */ + {RFBI_DATA14, (M4)}, /* KBD_COL7 */ + {RFBI_DATA15, (M4)}, /* KBD_COL6 */ + {GPIO6_182, (M6)}, /* GPIO6_182 */ + {GPIO6_183, (PTD | M6)}, /* GPIO6_183 */ + {GPIO6_184, (M4)}, /* KBD_COL2 */ + {GPIO6_185, (PTD | IEN | M6)}, /* GPIO6_185 */ + {GPIO6_186, (PTD | M6)}, /* GPIO6_186 */ + {GPIO6_187, (PTU | IEN | M4)}, /* KBD_ROW2 */ + {RFBI_DATA0, (PTD | M6)}, /* GPIO6_166 */ + {RFBI_DATA1, (PTD | M6)}, /* GPIO6_167 */ + {RFBI_DATA2, (PTD | M6)}, /* GPIO6_168 */ + {RFBI_DATA3, (PTD | IEN | M6)}, /* GPIO6_169 */ + {RFBI_DATA4, (IEN | M6)}, /* GPIO6_170 */ + {RFBI_DATA5, (IEN | M6)}, /* GPIO6_171 */ + {RFBI_DATA6, (PTD | M6)}, /* GPIO6_172 */ + {RFBI_DATA7, (PTD | M6)}, /* GPIO6_173 */ + {RFBI_CS0, (PTD | IEN | M6)}, /* GPIO6_163 */ + {RFBI_WE, (PTD | M6)}, /* GPIO6_162 */ + {MCSPI2_CS0, (M0)}, /* MCSPI2_CS0 */ + {MCSPI2_CLK, (IEN | M0)}, /* MCSPI2_CLK */ + {MCSPI2_SIMO, (IEN | M0)}, /* MCSPI2_SIMO*/ + {MCSPI2_SOMI, (PTU | IEN | M0)}, /* MCSPI2_SOMI*/ + {I2C4_SCL, (IEN | M0)}, /* I2C4_SCL */ + {I2C4_SDA, (IEN | M0)}, /* I2C4_SDA */ + {HDMI_CEC, (IEN | M0)}, /* HDMI_CEC */ + {HDMI_HPD, (PTD | IEN | M0)}, /* HDMI_HPD */ + {HDMI_DDC_SCL, (IEN | M0)}, /* HDMI_DDC_SCL */ + {HDMI_DDC_SDA, (IEN | M0)}, /* HDMI_DDC_SDA */ + {CSIPORTA_LANE0X, (IEN | M0)}, /* CSIPORTA_LANE0X */ + {CSIPORTA_LANE0Y, (IEN | M0)}, /* CSIPORTA_LANE0Y */ + {CSIPORTA_LANE1Y, (IEN | M0)}, /* CSIPORTA_LANE1Y */ + {CSIPORTA_LANE1X, (IEN | M0)}, /* CSIPORTA_LANE1X */ + {CSIPORTA_LANE2Y, (IEN | M0)}, /* CSIPORTA_LANE2Y */ + {CSIPORTA_LANE2X, (IEN | M0)}, /* CSIPORTA_LANE2X */ + {CSIPORTA_LANE3X, (IEN | M0)}, /* CSIPORTA_LANE3X */ + {CSIPORTA_LANE3Y, (IEN | M0)}, /* CSIPORTA_LANE3Y */ + {CSIPORTA_LANE4X, (IEN | M0)}, /* CSIPORTA_LANE4X */ + {CSIPORTA_LANE4Y, (IEN | M0)}, /* CSIPORTA_LANE4Y */ + {CSIPORTB_LANE0X, (IEN | M0)}, /* CSIPORTB_LANE0X */ + {CSIPORTB_LANE0Y, (IEN | M0)}, /* CSIPORTB_LANE0Y */ + {CSIPORTB_LANE1Y, (IEN | M0)}, /* CSIPORTB_LANE1Y */ + {CSIPORTB_LANE1X, (IEN | M0)}, /* CSIPORTB_LANE1X */ + {CSIPORTB_LANE2Y, (IEN | M0)}, /* CSIPORTB_LANE2Y */ + {CSIPORTB_LANE2X, (IEN | M0)}, /* CSIPORTB_LANE2X */ + {CSIPORTC_LANE0Y, (IEN | M0)}, /* CSIPORTC_LANE0Y */ + {CSIPORTC_LANE0X, (IEN | M0)}, /* CSIPORTC_LANE0X */ + {CSIPORTC_LANE1Y, (IEN | M0)}, /* CSIPORTC_LANE1Y */ + {CSIPORTC_LANE1X, (IEN | M0)}, /* CSIPORTC_LANE1X */ + {CAM_SHUTTER, (M0)}, /* CAM_SHUTTER */ + {CAM_STROBE, (M0)}, /* CAM_STROBE */ + {CAM_GLOBALRESET, (IEN | M0)}, /* CAM_GLOBALRESET */ + {TIMER11_PWM_EVT, (PTD | M6)}, /* GPIO8_227 */ + {TIMER5_PWM_EVT, (PTD | M6)}, /* GPIO8_228 */ + {TIMER6_PWM_EVT, (PTD | M6)}, /* GPIO8_229 */ + {TIMER8_PWM_EVT, (PTU | M6)}, /* GPIO8_230 */ + {I2C3_SCL, (IEN | M0)}, /* I2C3_SCL */ + {I2C3_SDA, (IEN | M0)}, /* I2C3_SDA */ + {GPIO8_233, (IEN | M2)}, /* TIMER8_PWM_EVT */ + {ABE_CLKS, (IEN | M0)}, /* ABE_CLKS */ + {ABEDMIC_DIN1, (IEN | M0)}, /* ABEDMIC_DIN1 */ + {ABEDMIC_DIN2, (IEN | M0)}, /* ABEDMIC_DIN2 */ + {ABEDMIC_DIN3, (IEN | M0)}, /* ABEDMIC_DIN3 */ + {ABEDMIC_CLK1, (M0)}, /* ABEDMIC_CLK1 */ + {ABEDMIC_CLK2, (IEN | M1)}, /* ABEMCBSP1_FSX */ + {ABEDMIC_CLK3, (M1)}, /* ABEMCBSP1_DX */ + {ABESLIMBUS1_CLOCK, (IEN | M1)}, /* ABEMCBSP1_CLKX */ + {ABESLIMBUS1_DATA, (IEN | M1)}, /* ABEMCBSP1_DR */ + {ABEMCBSP2_DR, (IEN | M0)}, /* ABEMCBSP2_DR */ + {ABEMCBSP2_DX, (M0)}, /* ABEMCBSP2_DX */ + {ABEMCBSP2_FSX, (IEN | M0)}, /* ABEMCBSP2_FSX */ + {ABEMCBSP2_CLKX, (IEN | M0)}, /* ABEMCBSP2_CLKX */ + {ABEMCPDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* ABEMCPDM_UL_DATA */ + {ABEMCPDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* ABEMCPDM_DL_DATA */ + {ABEMCPDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* ABEMCPDM_FRAME */ + {ABEMCPDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* ABEMCPDM_LB_CLK */ + {WLSDIO_CLK, (PTU | IEN | M0)}, /* WLSDIO_CLK */ + {WLSDIO_CMD, (PTU | IEN | M0)}, /* WLSDIO_CMD */ + {WLSDIO_DATA0, (PTU | IEN | M0)}, /* WLSDIO_DATA0*/ + {WLSDIO_DATA1, (PTU | IEN | M0)}, /* WLSDIO_DATA1*/ + {WLSDIO_DATA2, (PTU | IEN | M0)}, /* WLSDIO_DATA2*/ + {WLSDIO_DATA3, (PTU | IEN | M0)}, /* WLSDIO_DATA3*/ + {UART5_RX, (PTU | IEN | M0)}, /* UART5_RX */ + {UART5_TX, (M0)}, /* UART5_TX */ + {UART5_CTS, (PTU | IEN | M0)}, /* UART5_CTS */ + {UART5_RTS, (M0)}, /* UART5_RTS */ + {I2C2_SCL, (IEN | M0)}, /* I2C2_SCL */ + {I2C2_SDA, (IEN | M0)}, /* I2C2_SDA */ + {MCSPI1_CLK, (M6)}, /* GPIO5_140 */ + {MCSPI1_SOMI, (IEN | M6)}, /* GPIO5_141 */ + {MCSPI1_SIMO, (PTD | M6)}, /* GPIO5_142 */ + {MCSPI1_CS0, (PTD | M6)}, /* GPIO5_143 */ + {MCSPI1_CS1, (PTD | IEN | M6)}, /* GPIO5_144 */ + {I2C5_SCL, (IEN | M0)}, /* I2C5_SCL */ + {I2C5_SDA, (IEN | M0)}, /* I2C5_SDA */ + {PERSLIMBUS2_CLOCK, (PTD | M6)}, /* GPIO5_145 */ + {PERSLIMBUS2_DATA, (PTD | IEN | M6)}, /* GPIO5_146 */ + {UART6_TX, (PTU | IEN | M6)}, /* GPIO5_149 */ + {UART6_RX, (PTU | IEN | M6)}, /* GPIO5_150 */ + {UART6_CTS, (PTU | IEN | M6)}, /* GPIO5_151 */ + {UART6_RTS, (PTU | M0)}, /* UART6_RTS */ + {UART3_CTS_RCTX, (PTU | IEN | M6)}, /* GPIO5_153 */ + {UART3_RTS_IRSD, (PTU | IEN | M1)}, /* HDQ_SIO */ + {USBB3_HSIC_STROBE, (PTU | IEN | M0)}, /* USBB3_HSIC_STROBE*/ + {USBB3_HSIC_DATA, (PTU | IEN | M0)}, /* USBB3_HSIC_DATA */ + {USBD0_HS_DP, (IEN | M0)}, /* USBD0_HS_DP */ + {USBD0_HS_DM, (IEN | M0)}, /* USBD0_HS_DM */ + {USBD0_SS_RX, (IEN | M0)}, /* USBD0_SS_RX */ + {I2C1_PMIC_SCL, (PTU | IEN | M0)}, /* I2C1_PMIC_SCL */ + {I2C1_PMIC_SDA, (PTU | IEN | M0)}, /* I2C1_PMIC_SDA */ + }; const struct pad_conf_entry wkup_padconf_array_non_essential[] = { - {PAD0_SIM_IO, (IEN | M0)}, /* sim_io */ - {PAD1_SIM_CLK, (M0)}, /* sim_clk */ - {PAD0_SIM_RESET, (M0)}, /* sim_reset */ - {PAD1_SIM_CD, (PTU | IEN | M0)}, /* sim_cd */ - {PAD0_SIM_PWRCTRL, (M0)}, /* sim_pwrctrl */ - {PAD1_FREF_XTAL_IN, (M0)}, /* # */ - {PAD0_FREF_SLICER_IN, (M0)}, /* fref_slicer_in */ - {PAD1_FREF_CLK_IOREQ, (M0)}, /* fref_clk_ioreq */ - {PAD0_FREF_CLK0_OUT, (M2)}, /* sys_drm_msecure */ - {PAD1_FREF_CLK3_REQ, (PTU | IEN | M0)}, /* # */ - {PAD0_FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */ - {PAD1_FREF_CLK4_REQ, (PTU | IEN | M0)}, /* # */ - {PAD0_FREF_CLK4_OUT, (M0)}, /* # */ - {PAD0_SYS_NRESPWRON, (M0)}, /* sys_nrespwron */ - {PAD1_SYS_NRESWARM, (M0)}, /* sys_nreswarm */ - {PAD0_SYS_PWR_REQ, (PTU | M0)}, /* sys_pwr_req */ - {PAD1_SYS_PWRON_RESET, (M3)}, /* gpio_wk29 */ - {PAD0_SYS_BOOT6, (IEN | M3)}, /* gpio_wk9 */ - {PAD1_SYS_BOOT7, (IEN | M3)}, /* gpio_wk10 */ - {PAD1_FREF_CLK3_REQ, (M3)}, /* gpio_wk30 */ - {PAD1_FREF_CLK4_REQ, (M3)}, /* gpio_wk7 */ - {PAD0_FREF_CLK4_OUT, (M3)}, /* gpio_wk8 */ + +/* + * This pad keeps C2C Module always enabled. + * Putting this in safe mode do not cause the issue. + * C2C driver could enable this mux setting if needed. + */ + {LLIA_WAKEREQIN, (M7)}, /* SAFE MODE */ + {LLIB_WAKEREQIN, (M7)}, /* SAFE MODE */ + {DRM_EMU0, (PTU | IEN | M0)}, /* DRM_EMU0 */ + {DRM_EMU1, (PTU | IEN | M0)}, /* DRM_EMU1 */ + {JTAG_NTRST, (IEN | M0)}, /* JTAG_NTRST */ + {JTAG_TCK, (IEN | M0)}, /* JTAG_TCK */ + {JTAG_RTCK, (M0)}, /* JTAG_RTCK */ + {JTAG_TMSC, (IEN | M0)}, /* JTAG_TMSC */ + {JTAG_TDI, (IEN | M0)}, /* JTAG_TDI */ + {JTAG_TDO, (M0)}, /* JTAG_TDO */ + {FREF_CLK_IOREQ, (IEN | M0)}, /* FREF_CLK_IOREQ */ + {FREF_CLK0_OUT, (M0)}, /* FREF_CLK0_OUT */ + {FREF_CLK1_OUT, (M0)}, /* FREF_CLK1_OUT */ + {FREF_CLK2_OUT, (M0)}, /* FREF_CLK2_OUT */ + {FREF_CLK2_REQ, (PTU | IEN | M6)}, /* GPIO1_WK9 */ + {FREF_CLK1_REQ, (PTD | IEN | M6)}, /* GPIO1_WK8 */ + {SYS_NRESPWRON, (IEN | M0)}, /* SYS_NRESPWRON */ + {SYS_NRESWARM, (PTU | IEN | M0)}, /* SYS_NRESWARM */ + {SYS_PWR_REQ, (M0)}, /* SYS_PWR_REQ */ + {SYS_NIRQ1, (PTU | IEN | M0)}, /* SYS_NIRQ1 */ + {SYS_NIRQ2, (PTU | IEN | M0)}, /* SYS_NIRQ2 */ + {SYS_BOOT0, (IEN | M0)}, /* SYS_BOOT0 */ + {SYS_BOOT1, (IEN | M0)}, /* SYS_BOOT1 */ + {SYS_BOOT2, (IEN | M0)}, /* SYS_BOOT2 */ + {SYS_BOOT3, (IEN | M0)}, /* SYS_BOOT3 */ + {SYS_BOOT4, (IEN | M0)}, /* SYS_BOOT4 */ + {SYS_BOOT5, (IEN | M0)}, /* SYS_BOOT5 */ + }; #endif /* _EVM4430_MUX_DATA_H */ diff --git a/board/ti/omap730p2/omap730p2.c b/board/ti/omap730p2/omap730p2.c index 954ced5efe..36204b2c88 100644 --- a/board/ti/omap730p2/omap730p2.c +++ b/board/ti/omap730p2/omap730p2.c @@ -129,12 +129,6 @@ int board_init (void) return 0; } -int misc_init_r (void) -{ - /* currently empty */ - return (0); -} - /****************************** Routine: Description: diff --git a/board/ti/panda/panda.c b/board/ti/panda/panda.c index ca4b8b35eb..ee82771b08 100644 --- a/board/ti/panda/panda.c +++ b/board/ti/panda/panda.c @@ -179,7 +179,7 @@ void set_muxconf_regs_non_essential(void) #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) int board_mmc_init(bd_t *bis) { - omap_mmc_init(0); + omap_mmc_init(0, 0, 0); return 0; } #endif diff --git a/board/ti/panda/panda_mux_data.h b/board/ti/panda/panda_mux_data.h index 5b66a14242..dc8b3886c2 100644 --- a/board/ti/panda/panda_mux_data.h +++ b/board/ti/panda/panda_mux_data.h @@ -76,7 +76,7 @@ const struct pad_conf_entry wkup_padconf_array_essential[] = { const struct pad_conf_entry wkup_padconf_array_essential_4460[] = { -{PAD1_FREF_CLK4_REQ, (PTU | M7)}, /* gpio_wk7 for TPS: safe mode + pull up */ +{PAD1_FREF_CLK4_REQ, (M3)}, /* gpio_wk7 for TPS: Mode 3 */ }; @@ -168,10 +168,10 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = { {ABE_DMIC_DIN1, (IEN | M0)}, /* abe_dmic_din1 */ {ABE_DMIC_DIN2, (PTU | IEN | M3)}, /* gpio_121 */ {ABE_DMIC_DIN3, (IEN | M0)}, /* abe_dmic_din3 */ - {UART2_CTS, (PTU | IEN | M0)}, /* uart2_cts */ - {UART2_RTS, (M0)}, /* uart2_rts */ - {UART2_RX, (PTU | IEN | M0)}, /* uart2_rx */ - {UART2_TX, (M0)}, /* uart2_tx */ + {UART2_CTS, (PTU | IEN | M7)}, /* uart2_cts */ + {UART2_RTS, (M7)}, /* uart2_rts */ + {UART2_RX, (PTU | IEN | M7)}, /* uart2_rx */ + {UART2_TX, (M7)}, /* uart2_tx */ {HDQ_SIO, (M3)}, /* gpio_127 */ {MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_clk */ {MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_somi */ diff --git a/board/ti/sdp3430/sdp.c b/board/ti/sdp3430/sdp.c index d73f501819..9a1c012145 100644 --- a/board/ti/sdp3430/sdp.c +++ b/board/ti/sdp3430/sdp.c @@ -209,7 +209,7 @@ void set_muxconf_regs(void) #ifdef CONFIG_GENERIC_MMC int board_mmc_init(bd_t *bis) { - omap_mmc_init(0); + omap_mmc_init(0, 0, 0); return 0; } #endif diff --git a/board/ti/sdp4430/sdp.c b/board/ti/sdp4430/sdp.c index 9ae9e2c602..982c771a73 100644 --- a/board/ti/sdp4430/sdp.c +++ b/board/ti/sdp4430/sdp.c @@ -108,8 +108,8 @@ void set_muxconf_regs_non_essential(void) #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) int board_mmc_init(bd_t *bis) { - omap_mmc_init(0); - omap_mmc_init(1); + omap_mmc_init(0, 0, 0); + omap_mmc_init(1, 0, 0); return 0; } #endif diff --git a/board/ti/sdp4430/sdp4430_mux_data.h b/board/ti/sdp4430/sdp4430_mux_data.h index 0a20968978..6140b999ef 100644 --- a/board/ti/sdp4430/sdp4430_mux_data.h +++ b/board/ti/sdp4430/sdp4430_mux_data.h @@ -67,7 +67,7 @@ const struct pad_conf_entry wkup_padconf_array_essential[] = { const struct pad_conf_entry wkup_padconf_array_essential_4460[] = { -{PAD1_FREF_CLK4_REQ, (PTU | M7)}, /* gpio_wk7 for TPS: safe mode + pull up */ +{PAD1_FREF_CLK4_REQ, (M3)}, /* gpio_wk7 for TPS: Mode 3 */ }; diff --git a/board/timll/devkit3250/Makefile b/board/timll/devkit3250/Makefile new file mode 100644 index 0000000000..ea7827c80d --- /dev/null +++ b/board/timll/devkit3250/Makefile @@ -0,0 +1,44 @@ +# +# Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com> +# Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301, USA. +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := devkit3250.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/timll/devkit3250/devkit3250.c b/board/timll/devkit3250/devkit3250.c new file mode 100644 index 0000000000..6b0ec80fcd --- /dev/null +++ b/board/timll/devkit3250/devkit3250.c @@ -0,0 +1,65 @@ +/* + * Embest/Timll DevKit3250 board support + * + * Copyright (C) 2011 Vladimir Zapolskiy <vz@mleia.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#include <common.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/cpu.h> +#include <asm/arch/emc.h> + +DECLARE_GLOBAL_DATA_PTR; + +static struct emc_regs *emc = (struct emc_regs *)EMC_BASE; + +int board_early_init_f(void) +{ + lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART); + + return 0; +} + +int board_init(void) +{ + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + +#ifdef CONFIG_SYS_FLASH_CFI + /* Use 16-bit memory interface for NOR Flash */ + emc->stat[0].config = EMC_STAT_CONFIG_PB | EMC_STAT_CONFIG_16BIT; + + /* Change the NOR timings to optimum value to get maximum bandwidth */ + emc->stat[0].waitwen = EMC_STAT_WAITWEN(1); + emc->stat[0].waitoen = EMC_STAT_WAITOEN(1); + emc->stat[0].waitrd = EMC_STAT_WAITRD(12); + emc->stat[0].waitpage = EMC_STAT_WAITPAGE(12); + emc->stat[0].waitwr = EMC_STAT_WAITWR(5); + emc->stat[0].waitturn = EMC_STAT_WAITTURN(2); +#endif + + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + + return 0; +} diff --git a/board/timll/devkit8000/devkit8000.c b/board/timll/devkit8000/devkit8000.c index d75e86b32e..35f5e15fc2 100644 --- a/board/timll/devkit8000/devkit8000.c +++ b/board/timll/devkit8000/devkit8000.c @@ -136,7 +136,7 @@ void set_muxconf_regs(void) #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { - omap_mmc_init(0); + omap_mmc_init(0, 0, 0); return 0; } #endif |
