Merge branch 'u-boot/master' into 'u-boot-arm/master'

82 files changed, 263 insertions, 5999 deletions

diff --git a/board/Marvell/include/pci.h b/board/Marvell/include/pci.h
index 167248db1e..572e0d345d 100644
--- a/board/Marvell/include/pci.h
+++ b/board/Marvell/include/pci.h
@@ -7,8 +7,8 @@
 
 /* includes */
 
-#include"core.h"
-#include"memory.h"
+#include "core.h"
+#include "memory.h"
 
 /* According to PCI REV 2.1 MAX agents allowed on the bus are -21- */
 #define PCI_MAX_DEVICES 22
diff --git a/board/abilis/tb100/Makefile b/board/abilis/tb100/Makefile
new file mode 100644
index 0000000000..4f273b322b
--- /dev/null
+++ b/board/abilis/tb100/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2014 Pierrick Hascoet, Abilis Systems
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	+= tb100.o
diff --git a/board/abilis/tb100/tb100.c b/board/abilis/tb100/tb100.c
new file mode 100644
index 0000000000..ff3632f6c0
--- /dev/null
+++ b/board/abilis/tb100/tb100.c
@@ -0,0 +1,23 @@
+/*
+ * (C) Copyright 2014 Pierrick Hascoet, Abilis Systems
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+
+void reset_cpu(ulong addr)
+{
+#define CRM_SWRESET	0xff101044
+	writel(0x1, (void *)CRM_SWRESET);
+}
+
+int board_eth_init(bd_t *bis)
+{
+	if (designware_initialize(ETH0_BASE_ADDRESS, 0) >= 0)
+		return 1;
+
+	return 0;
+}
diff --git a/board/adder/Makefile b/board/adder/Makefile
deleted file mode 100644
index 8dc505a5fe..0000000000
--- a/board/adder/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# Copyright (C) 2004 Arabella Software Ltd.
-# Yuli Barcohen <yuli@arabellasw.com>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= adder.o
diff --git a/board/adder/adder.c b/board/adder/adder.c
deleted file mode 100644
index 2ee7096b83..0000000000
--- a/board/adder/adder.c
+++ /dev/null
@@ -1,108 +0,0 @@
-/*
- * Copyright (C) 2004-2005 Arabella Software Ltd.
- * Yuli Barcohen <yuli@arabellasw.com>
- *
- * Support for Analogue&Micro Adder boards family.
- * Tested on AdderII and Adder87x.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-#if defined(CONFIG_OF_LIBFDT)
-	#include <libfdt.h>
-#endif
-
-/*
- * SDRAM is single Samsung K4S643232F-T70   chip (8MB)
- *       or single Micron  MT48LC4M32B2TG-7 chip (16MB).
- * Minimal CPU frequency is 40MHz.
- */
-static uint sdram_table[] = {
-	/* Single read	(offset 0x00 in UPM RAM) */
-	0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xe0bbbc00,
-	0x10f77c44, 0xf3fffc07, 0xfffffc04, 0xfffffc04,
-
-	/* Burst read	(offset 0x08 in UPM RAM) */
-	0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xf0affc00,
-	0xf0affc00, 0xf0affc00, 0xf0affc00, 0x10a77c44,
-	0xf7bffc47, 0xfffffc35, 0xfffffc34, 0xfffffc35,
-	0xfffffc35, 0x1ff77c35, 0xfffffc34, 0x1fb57c35,
-
-	/* Single write (offset 0x18 in UPM RAM) */
-	0x1f27fc24, 0xe0aebc04, 0x00b93c00, 0x13f77c47,
-	0xfffdfc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
-
-	/* Burst write	(offset 0x20 in UPM RAM) */
-	0x1f07fc24, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
-	0xf0affc00, 0xe0abbc00, 0x1fb77c47, 0xfffffc04,
-	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
-	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
-
-	/* Refresh	(offset 0x30 in UPM RAM) */
-	0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
-	0xfffffc84, 0xfffffc07, 0xfffffc04, 0xfffffc04,
-	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
-
-	/* Exception	(offset 0x3C in UPM RAM) */
-	0xfffffc27, 0xfffffc04, 0xfffffc04, 0xfffffc04
-};
-
-phys_size_t initdram (int board_type)
-{
-	long int msize;
-	volatile immap_t     *immap  = (volatile immap_t *)CONFIG_SYS_IMMR;
-	volatile memctl8xx_t *memctl = &immap->im_memctl;
-
-	upmconfig(UPMA, sdram_table, sizeof(sdram_table) / sizeof(uint));
-
-	/* Configure SDRAM refresh */
-	memctl->memc_mptpr = MPTPR_PTP_DIV32; /* BRGCLK/32 */
-
-	memctl->memc_mamr = (94 << 24) | CONFIG_SYS_MAMR; /* No refresh */
-	udelay(200);
-
-	/* Run precharge from location 0x15 */
-	memctl->memc_mar = 0x0;
-	memctl->memc_mcr = 0x80002115;
-	udelay(200);
-
-	/* Run 8 refresh cycles */
-	memctl->memc_mcr = 0x80002830;
-	udelay(200);
-
-	/* Run MRS pattern from location 0x16 */
-	memctl->memc_mar = 0x88;
-	memctl->memc_mcr = 0x80002116;
-	udelay(200);
-
-	memctl->memc_mamr |=  MAMR_PTAE; /* Enable refresh */
-	memctl->memc_or1   = ~(CONFIG_SYS_SDRAM_MAX_SIZE - 1) | OR_CSNT_SAM;
-	memctl->memc_br1   =  CONFIG_SYS_SDRAM_BASE | BR_PS_32 | BR_MS_UPMA | BR_V;
-
-	msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_MAX_SIZE);
-	memctl->memc_or1  |= ~(msize - 1);
-
-	return msize;
-}
-
-int checkboard( void )
-{
-	puts("Board: Adder");
-#if defined(CONFIG_MPC885_FAMILY)
-	puts("87x\n");
-#elif defined(CONFIG_MPC866_FAMILY)
-	puts("II\n");
-#endif
-
-	return 0;
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup(blob, bd);
-
-}
-#endif
diff --git a/board/adder/u-boot.lds b/board/adder/u-boot.lds
deleted file mode 100644
index 38567d1c6e..0000000000
--- a/board/adder/u-boot.lds
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * (C) Copyright 2001-2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Modified by Yuli Barcohen <yuli@arabellasw.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-SECTIONS
-{
-  /* Read-only sections, merged into text segment: */
-  . = + SIZEOF_HEADERS;
-  .text          :
-  {
-    arch/powerpc/cpu/mpc8xx/start.o	(.text*)
-    arch/powerpc/cpu/mpc8xx/traps.o	(.text*)
-    *(.text*)
-    . = ALIGN(16);
-    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
-  }
-
-  /* Read-write section, merged into data segment: */
-  . = (. + 0x0FFF) & 0xFFFFF000;
-  _erotext = .;
-  PROVIDE (erotext = .);
-  .reloc   :
-  {
-    _GOT2_TABLE_ = .;
-    KEEP(*(.got2))
-    KEEP(*(.got))
-    PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
-    _FIXUP_TABLE_ = .;
-    KEEP(*(.fixup))
-  }
-  __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
-  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
-
-  .data    :
-  {
-    *(.data*)
-    *(.sdata*)
-  }
-  _edata  =  .;
-  PROVIDE (edata = .);
-
-  . = .;
-
-  . = ALIGN(4);
-  .u_boot_list : {
-	KEEP(*(SORT(.u_boot_list*)));
-  }
-
-
-  . = .;
-  __start___ex_table = .;
-  __ex_table : { *(__ex_table) }
-  __stop___ex_table = .;
-
-  . = ALIGN(4096);
-  __init_begin = .;
-  .text.init : { *(.text.init) }
-  .data.init : { *(.data.init) }
-  . = ALIGN(4096);
-  __init_end = .;
-
-  __bss_start = .;
-  .bss (NOLOAD)       :
-  {
-   *(.bss*)
-   *(.sbss*)
-   *(COMMON)
-   . = ALIGN(4);
-  }
-  __bss_end = . ;
-  PROVIDE (end = .);
-}
-ENTRY(_start)
diff --git a/board/ait/cam_enc_4xx/cam_enc_4xx.c b/board/ait/cam_enc_4xx/cam_enc_4xx.c
index 7e1b16ac46..9aa1d7aece 100644
--- a/board/ait/cam_enc_4xx/cam_enc_4xx.c
+++ b/board/ait/cam_enc_4xx/cam_enc_4xx.c
@@ -8,8 +8,8 @@
  */
 
 #include <common.h>
+#include <cli.h>
 #include <errno.h>
-#include <hush.h>
 #include <linux/mtd/nand.h>
 #include <nand.h>
 #include <miiphy.h>
@@ -777,7 +777,7 @@ static void ait_menu_read_env(char *name)
 
 	sprintf(output, "%s old: %s value: ", name, getenv(name));
 	memset(cbuf, 0, CONFIG_SYS_CBSIZE);
-	readret = readline_into_buffer(output, cbuf, 0);
+	readret = cli_readline_into_buffer(output, cbuf, 0);
 
 	if (readret >= 0) {
 		ret = setenv(name, cbuf);
diff --git a/board/altera/common/sevenseg.c b/board/altera/common/sevenseg.c
deleted file mode 100644
index 1f22c8524a..0000000000
--- a/board/altera/common/sevenseg.c
+++ /dev/null
@@ -1,204 +0,0 @@
-/*
- * (C) Copyright 2003, Li-Pro.Net <www.li-pro.net>
- * Stephan Linz <linz@li-pro.net>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * common/sevenseg.c
- *
- * NIOS PIO based seven segment led support functions
- */
-
-#include <common.h>
-#include <nios-io.h>
-
-#ifdef	CONFIG_SEVENSEG
-
-#define SEVENDEG_MASK_DP	((SEVENSEG_DIGIT_DP << 8) | SEVENSEG_DIGIT_DP)
-
-#ifdef	SEVENSEG_WRONLY	/* emulate read access */
-#if (SEVENSEG_ACTIVE == 0)
-static unsigned int sevenseg_portval = ~0;
-#else
-static unsigned int sevenseg_portval = 0;
-#endif
-#endif
-
-static int sevenseg_init_done = 0;
-
-static inline void __sevenseg_set_masked (unsigned int mask, int value)
-{
-	nios_pio_t *piop __attribute__((unused)) = (nios_pio_t*)SEVENSEG_BASE;
-
-#ifdef	SEVENSEG_WRONLY	/* emulate read access */
-
-#if (SEVENSEG_ACTIVE == 0)
-	if (value)
-		sevenseg_portval &= ~mask;
-	else
-		sevenseg_portval |= mask;
-#else
-	if (value)
-		sevenseg_portval |= mask;
-	else
-		sevenseg_portval &= ~mask;
-#endif
-
-	piop->data = sevenseg_portval;
-
-#else	/* !SEVENSEG_WRONLY */
-
-#if (SEVENSEG_ACTIVE == 0)
-	if (value)
-		piop->data &= ~mask;
-	else
-		piop->data |= mask;
-#else
-	if (value)
-		piop->data |= mask;
-	else
-		piop->data &= ~mask;
-#endif
-
-#endif	/* SEVENSEG_WRONLY */
-}
-
-static inline void __sevenseg_toggle_masked (unsigned int mask)
-{
-	nios_pio_t *piop = (nios_pio_t*)SEVENSEG_BASE;
-
-#ifdef	SEVENSEG_WRONLY	/* emulate read access */
-
-	sevenseg_portval ^= mask;
-	piop->data = sevenseg_portval;
-
-#else	/* !SEVENSEG_WRONLY */
-
-	piop->data ^= mask;
-
-#endif	/* SEVENSEG_WRONLY */
-}
-
-static inline void __sevenseg_set (unsigned int value)
-{
-	nios_pio_t *piop __attribute__((unused)) = (nios_pio_t*)SEVENSEG_BASE;
-
-#ifdef	SEVENSEG_WRONLY	/* emulate read access */
-
-#if (SEVENSEG_ACTIVE == 0)
-	sevenseg_portval = (sevenseg_portval &   SEVENDEG_MASK_DP)
-			 | ((~value)         & (~SEVENDEG_MASK_DP));
-#else
-	sevenseg_portval = (sevenseg_portval & SEVENDEG_MASK_DP)
-			 | (value);
-#endif
-
-	piop->data = sevenseg_portval;
-
-#else	/* !SEVENSEG_WRONLY */
-
-#if (SEVENSEG_ACTIVE == 0)
-	piop->data = (piop->data &   SEVENDEG_MASK_DP)
-		   | ((~value)   & (~SEVENDEG_MASK_DP));
-#else
-	piop->data = (piop->data & SEVENDEG_MASK_DP)
-		   | (value);
-#endif
-
-#endif	/* SEVENSEG_WRONLY */
-}
-
-static inline void __sevenseg_init (void)
-{
-	nios_pio_t *piop __attribute__((unused)) = (nios_pio_t*)SEVENSEG_BASE;
-
-	__sevenseg_set(0);
-
-#ifndef	SEVENSEG_WRONLY	/* setup direction */
-
-	piop->direction |= mask;
-
-#endif	/* SEVENSEG_WRONLY */
-}
-
-
-void sevenseg_set(int value)
-{
-	unsigned char	digits[] = {
-		SEVENSEG_DIGITS_0,
-		SEVENSEG_DIGITS_1,
-		SEVENSEG_DIGITS_2,
-		SEVENSEG_DIGITS_3,
-		SEVENSEG_DIGITS_4,
-		SEVENSEG_DIGITS_5,
-		SEVENSEG_DIGITS_6,
-		SEVENSEG_DIGITS_7,
-		SEVENSEG_DIGITS_8,
-		SEVENSEG_DIGITS_9,
-		SEVENSEG_DIGITS_A,
-		SEVENSEG_DIGITS_B,
-		SEVENSEG_DIGITS_C,
-		SEVENSEG_DIGITS_D,
-		SEVENSEG_DIGITS_E,
-		SEVENSEG_DIGITS_F
-	};
-
-	if (!sevenseg_init_done) {
-		__sevenseg_init();
-		sevenseg_init_done++;
-	}
-
-	switch (value & SEVENSEG_MASK_CTRL) {
-
-		case SEVENSEG_RAW:
-			__sevenseg_set( (
-				(digits[((value & SEVENSEG_MASK_VAL) >>  4)] << 8) |
-				digits[((value & SEVENSEG_MASK_VAL) & 0xf)] ) );
-			return;
-			break;	/* paranoia */
-
-		case SEVENSEG_OFF:
-			__sevenseg_set(0);
-			__sevenseg_set_masked(SEVENDEG_MASK_DP, 0);
-			return;
-			break;	/* paranoia */
-
-		case SEVENSEG_SET_DPL:
-			__sevenseg_set_masked(SEVENSEG_DIGIT_DP, 1);
-			return;
-			break;	/* paranoia */
-
-		case SEVENSEG_SET_DPH:
-			__sevenseg_set_masked((SEVENSEG_DIGIT_DP << 8), 1);
-			return;
-			break;	/* paranoia */
-
-		case SEVENSEG_RES_DPL:
-			__sevenseg_set_masked(SEVENSEG_DIGIT_DP, 0);
-			return;
-			break;	/* paranoia */
-
-		case SEVENSEG_RES_DPH:
-			__sevenseg_set_masked((SEVENSEG_DIGIT_DP << 8), 0);
-			return;
-			break;	/* paranoia */
-
-		case SEVENSEG_TOG_DPL:
-			__sevenseg_toggle_masked(SEVENSEG_DIGIT_DP);
-			return;
-			break;	/* paranoia */
-
-		case SEVENSEG_TOG_DPH:
-			__sevenseg_toggle_masked((SEVENSEG_DIGIT_DP << 8));
-			return;
-			break;	/* paranoia */
-
-		case SEVENSEG_LO:
-		case SEVENSEG_HI:
-		case SEVENSEG_STR:
-		default:
-			break;
-	}
-}
-
-#endif	/* CONFIG_SEVENSEG */
diff --git a/board/altera/common/sevenseg.h b/board/altera/common/sevenseg.h
deleted file mode 100644
index 34348329ec..0000000000
--- a/board/altera/common/sevenseg.h
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- * (C) Copyright 2003, Li-Pro.Net <www.li-pro.net>
- * Stephan Linz <linz@li-pro.net>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * common/sevenseg.h
- *
- * NIOS PIO based seven segment led support functions
- */
-
-#ifndef __DK1S10_SEVENSEG_H__
-#define __DK1S10_SEVENSEG_H__
-
-#ifdef	CONFIG_SEVENSEG
-
-/*
- *  15                    8 7      0
- * |-----------------------|--------|
- * |   controll value      |  value |
- * ----------------------------------
- */
-#define	SEVENSEG_RAW		(int)(0)	/* write out byte value (hex) */
-#define	SEVENSEG_OFF		(int)( 1 << 8)	/* display switch off */
-#define	SEVENSEG_SET_DPL	(int)( 2 << 8)	/* set dp low  nibble */
-#define	SEVENSEG_SET_DPH	(int)( 3 << 8)	/* set dp high nibble */
-#define	SEVENSEG_RES_DPL	(int)( 4 << 8)	/* reset dp low  nibble */
-#define	SEVENSEG_RES_DPH	(int)( 5 << 8)	/* reset dp high nibble */
-#define	SEVENSEG_TOG_DPL	(int)( 6 << 8)	/* toggle dp low  nibble */
-#define	SEVENSEG_TOG_DPH	(int)( 7 << 8)	/* toggle dp high nibble */
-#define	SEVENSEG_LO		(int)( 8 << 8)	/* write out low nibble only */
-#define	SEVENSEG_HI		(int)( 9 << 8)	/* write out high nibble only */
-#define	SEVENSEG_STR		(int)(10 << 8)	/* write out a string */
-
-#define	SEVENSEG_MASK_VAL	(0xff)		/* only used by SEVENSEG_RAW */
-#define	SEVENSEG_MASK_CTRL	(~SEVENSEG_MASK_VAL)
-
-#ifdef	SEVENSEG_DIGIT_HI_LO_EQUAL
-
-#define	SEVENSEG_DIGITS_0	(	SEVENSEG_DIGIT_A	\
-				|	SEVENSEG_DIGIT_B	\
-				|	SEVENSEG_DIGIT_C	\
-				|	SEVENSEG_DIGIT_D	\
-				|	SEVENSEG_DIGIT_E	\
-				|	SEVENSEG_DIGIT_F	)
-#define	SEVENSEG_DIGITS_1	(	SEVENSEG_DIGIT_B	\
-				|	SEVENSEG_DIGIT_C	)
-#define	SEVENSEG_DIGITS_2	(	SEVENSEG_DIGIT_A	\
-				|	SEVENSEG_DIGIT_B	\
-				|	SEVENSEG_DIGIT_D	\
-				|	SEVENSEG_DIGIT_E	\
-				|	SEVENSEG_DIGIT_G	)
-#define	SEVENSEG_DIGITS_3	(	SEVENSEG_DIGIT_A	\
-				|	SEVENSEG_DIGIT_B	\
-				|	SEVENSEG_DIGIT_C	\
-				|	SEVENSEG_DIGIT_D	\
-				|	SEVENSEG_DIGIT_G	)
-#define	SEVENSEG_DIGITS_4	(	SEVENSEG_DIGIT_B	\
-				|	SEVENSEG_DIGIT_C	\
-				|	SEVENSEG_DIGIT_F	\
-				|	SEVENSEG_DIGIT_G	)
-#define	SEVENSEG_DIGITS_5	(	SEVENSEG_DIGIT_A	\
-				|	SEVENSEG_DIGIT_C	\
-				|	SEVENSEG_DIGIT_D	\
-				|	SEVENSEG_DIGIT_F	\
-				|	SEVENSEG_DIGIT_G	)
-#define	SEVENSEG_DIGITS_6	(	SEVENSEG_DIGIT_A	\
-				|	SEVENSEG_DIGIT_C	\
-				|	SEVENSEG_DIGIT_D	\
-				|	SEVENSEG_DIGIT_E	\
-				|	SEVENSEG_DIGIT_F	\
-				|	SEVENSEG_DIGIT_G	)
-#define	SEVENSEG_DIGITS_7	(	SEVENSEG_DIGIT_A	\
-				|	SEVENSEG_DIGIT_B	\
-				|	SEVENSEG_DIGIT_C	)
-#define	SEVENSEG_DIGITS_8	(	SEVENSEG_DIGIT_A	\
-				|	SEVENSEG_DIGIT_B	\
-				|	SEVENSEG_DIGIT_C	\
-				|	SEVENSEG_DIGIT_D	\
-				|	SEVENSEG_DIGIT_E	\
-				|	SEVENSEG_DIGIT_F	\
-				|	SEVENSEG_DIGIT_G	)
-#define	SEVENSEG_DIGITS_9	(	SEVENSEG_DIGIT_A	\
-				|	SEVENSEG_DIGIT_B	\
-				|	SEVENSEG_DIGIT_C	\
-				|	SEVENSEG_DIGIT_D	\
-				|	SEVENSEG_DIGIT_F	\
-				|	SEVENSEG_DIGIT_G	)
-#define	SEVENSEG_DIGITS_A	(	SEVENSEG_DIGIT_A	\
-				|	SEVENSEG_DIGIT_B	\
-				|	SEVENSEG_DIGIT_C	\
-				|	SEVENSEG_DIGIT_E	\
-				|	SEVENSEG_DIGIT_F	\
-				|	SEVENSEG_DIGIT_G	)
-#define	SEVENSEG_DIGITS_B	(	SEVENSEG_DIGIT_C	\
-				|	SEVENSEG_DIGIT_D	\
-				|	SEVENSEG_DIGIT_E	\
-				|	SEVENSEG_DIGIT_F	\
-				|	SEVENSEG_DIGIT_G	)
-#define	SEVENSEG_DIGITS_C	(	SEVENSEG_DIGIT_D	\
-				|	SEVENSEG_DIGIT_E	\
-				|	SEVENSEG_DIGIT_G	)
-#define	SEVENSEG_DIGITS_D	(	SEVENSEG_DIGIT_B	\
-				|	SEVENSEG_DIGIT_C	\
-				|	SEVENSEG_DIGIT_D	\
-				|	SEVENSEG_DIGIT_E	\
-				|	SEVENSEG_DIGIT_G	)
-#define	SEVENSEG_DIGITS_E	(	SEVENSEG_DIGIT_A	\
-				|	SEVENSEG_DIGIT_D	\
-				|	SEVENSEG_DIGIT_E	\
-				|	SEVENSEG_DIGIT_F	\
-				|	SEVENSEG_DIGIT_G	)
-#define	SEVENSEG_DIGITS_F	(	SEVENSEG_DIGIT_A	\
-				|	SEVENSEG_DIGIT_E	\
-				|	SEVENSEG_DIGIT_F	\
-				|	SEVENSEG_DIGIT_G	)
-
-#else	/* !SEVENSEG_DIGIT_HI_LO_EQUAL */
-#error SEVENSEG: different pin asssignments not supported
-#endif
-
-void sevenseg_set(int value);
-
-#endif	/* CONFIG_SEVENSEG */
-
-#endif	/* __DK1S10_SEVENSEG_H__ */
diff --git a/board/altera/nios2-generic/Makefile b/board/altera/nios2-generic/Makefile
index 84690fe04d..aa362b3609 100644
--- a/board/altera/nios2-generic/Makefile
+++ b/board/altera/nios2-generic/Makefile
@@ -9,5 +9,4 @@
 obj-y	:= nios2-generic.o
 obj-$(CONFIG_CMD_IDE) += ../common/cfide.o
 obj-$(CONFIG_EPLED) += ../common/epled.o
-obj-$(CONFIG_SEVENSEG) += ../common/sevenseg.o
 obj-y	+= text_base.o
diff --git a/board/amcc/yucca/cmd_yucca.c b/board/amcc/yucca/cmd_yucca.c
index dc78b73731..c1724bf034 100644
--- a/board/amcc/yucca/cmd_yucca.c
+++ b/board/amcc/yucca/cmd_yucca.c
@@ -8,6 +8,7 @@
  */
 
 #include <common.h>
+#include <cli.h>
 #include <command.h>
 #include "yucca.h"
 #include <i2c.h>
@@ -51,7 +52,7 @@ static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag, int flag,
 
 	do {
 		printf("enter sys clock frequency 33 or 66 MHz or quit to abort\n");
-		nbytes = readline (" ? ");
+		nbytes = cli_readline(" ? ");
 
 		if (strcmp(console_buffer, "quit") == 0)
 			return 0;
@@ -74,7 +75,7 @@ static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag, int flag,
 			printf("enter cpu clock frequency 400, 500, 533 MHz or quit to abort\n");
 #endif
 		}
-		nbytes = readline (" ? ");
+		nbytes = cli_readline(" ? ");
 
 		if (strcmp(console_buffer, "quit") == 0)
 			return 0;
@@ -118,7 +119,7 @@ static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag, int flag,
 				printf("enter plb clock frequency 133, 166 MHz or quit to abort\n");
 
 #endif
-			nbytes = readline (" ? ");
+			nbytes = cli_readline(" ? ");
 
 			if (strcmp(console_buffer, "quit") == 0)
 				return 0;
@@ -142,7 +143,7 @@ static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag, int flag,
 
 	do {
 		printf("enter Pci-X clock frequency 33, 66, 100 or 133 MHz or quit to abort\n");
-		nbytes = readline (" ? ");
+		nbytes = cli_readline(" ? ");
 
 		if (strcmp(console_buffer, "quit") == 0)
 			return 0;
@@ -163,13 +164,13 @@ static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag, int flag,
 	printf("Pci-X clk = %s MHz\n", pcixClock);
 
 	do {
-		printf("\npress [y] to write I2C bootstrap \n");
-		printf("or [n] to abort.  \n");
-		printf("Don't forget to set board switches \n");
-		printf("according to your choice before re-starting \n");
-		printf("(refer to 440spe_uboot_kit_um_1_01.pdf) \n");
+		printf("\npress [y] to write I2C bootstrap\n");
+		printf("or [n] to abort.\n");
+		printf("Don't forget to set board switches\n");
+		printf("according to your choice before re-starting\n");
+		printf("(refer to 440spe_uboot_kit_um_1_01.pdf)\n");
 
-		nbytes = readline (" ? ");
+		nbytes = cli_readline(" ? ");
 		if (strcmp(console_buffer, "n") == 0)
 			return 0;
 
diff --git a/board/astro/mcf5373l/fpga.c b/board/astro/mcf5373l/fpga.c
index 1d044d96a5..d1110dfd6e 100644
--- a/board/astro/mcf5373l/fpga.c
+++ b/board/astro/mcf5373l/fpga.c
@@ -100,7 +100,7 @@ int altera_done_fn(int cookie)
  * writing the complete buffer in one function is much faster,
  * then calling it for every bit
  */
-int altera_write_fn(void *buf, size_t len, int flush, int cookie)
+int altera_write_fn(const void *buf, size_t len, int flush, int cookie)
 {
 	size_t bytecount = 0;
 	gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
diff --git a/board/astro/mcf5373l/mcf5373l.c b/board/astro/mcf5373l/mcf5373l.c
index daba32c9dc..7ec7cb378f 100644
--- a/board/astro/mcf5373l/mcf5373l.c
+++ b/board/astro/mcf5373l/mcf5373l.c
@@ -79,7 +79,7 @@ phys_size_t initdram(int board_type)
 	 * (Do not rely on the SDCS register(s) being set to 0x00000000
 	 * during reset as stated in the data sheet.)
 	 */
-	return get_ram_size((unsigned long *)CONFIG_SYS_SDRAM_BASE,
+	return get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
 				0x80000000 - CONFIG_SYS_SDRAM_BASE);
 }
 
diff --git a/board/atmel/at91sam9261ek/at91sam9261ek.c b/board/atmel/at91sam9261ek/at91sam9261ek.c
index 3e8f062f89..a301d72e8c 100644
--- a/board/atmel/at91sam9261ek/at91sam9261ek.c
+++ b/board/atmel/at91sam9261ek/at91sam9261ek.c
@@ -133,20 +133,20 @@ static void at91sam9261ek_dm9000_hw_init(void)
 
 #ifdef CONFIG_LCD
 vidinfo_t panel_info = {
-	vl_col:		240,
-	vl_row:		320,
-	vl_clk:		4965000,
-	vl_sync:	ATMEL_LCDC_INVLINE_INVERTED |
-			ATMEL_LCDC_INVFRAME_INVERTED,
-	vl_bpix:	3,
-	vl_tft:		1,
-	vl_hsync_len:	5,
-	vl_left_margin:	1,
-	vl_right_margin:33,
-	vl_vsync_len:	1,
-	vl_upper_margin:1,
-	vl_lower_margin:0,
-	mmio:		ATMEL_BASE_LCDC,
+	.vl_col =		240,
+	.vl_row =		320,
+	.vl_clk =		4965000,
+	.vl_sync =		ATMEL_LCDC_INVLINE_INVERTED |
+				ATMEL_LCDC_INVFRAME_INVERTED,
+	.vl_bpix =		3,
+	.vl_tft =		1,
+	.vl_hsync_len =		5,
+	.vl_left_margin =	1,
+	.vl_right_margin =	33,
+	.vl_vsync_len =		1,
+	.vl_upper_margin =	1,
+	.vl_lower_margin =	0,
+	.mmio =			ATMEL_BASE_LCDC,
 };
 
 void lcd_enable(void)
diff --git a/board/atmel/at91sam9263ek/at91sam9263ek.c b/board/atmel/at91sam9263ek/at91sam9263ek.c
index db29879801..927adb0d38 100644
--- a/board/atmel/at91sam9263ek/at91sam9263ek.c
+++ b/board/atmel/at91sam9263ek/at91sam9263ek.c
@@ -111,20 +111,20 @@ static void at91sam9263ek_macb_hw_init(void)
 
 #ifdef CONFIG_LCD
 vidinfo_t panel_info = {
-	vl_col:		240,
-	vl_row:		320,
-	vl_clk:		4965000,
-	vl_sync:	ATMEL_LCDC_INVLINE_INVERTED |
-			ATMEL_LCDC_INVFRAME_INVERTED,
-	vl_bpix:	3,
-	vl_tft:		1,
-	vl_hsync_len:	5,
-	vl_left_margin:	1,
-	vl_right_margin:33,
-	vl_vsync_len:	1,
-	vl_upper_margin:1,
-	vl_lower_margin:0,
-	mmio:		ATMEL_BASE_LCDC,
+	.vl_col =		240,
+	.vl_row =		320,
+	.vl_clk =		4965000,
+	.vl_sync =		ATMEL_LCDC_INVLINE_INVERTED |
+				ATMEL_LCDC_INVFRAME_INVERTED,
+	.vl_bpix =		3,
+	.vl_tft =		1,
+	.vl_hsync_len =		5,
+	.vl_left_margin =	1,
+	.vl_right_margin =	33,
+	.vl_vsync_len =		1,
+	.vl_upper_margin =	1,
+	.vl_lower_margin =	0,
+	.mmio =			ATMEL_BASE_LCDC,
 };
 
 void lcd_enable(void)
diff --git a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
index 57881164c5..b807ef9a42 100644
--- a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
+++ b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
@@ -121,20 +121,20 @@ static void at91sam9m10g45ek_macb_hw_init(void)
 #ifdef CONFIG_LCD
 
 vidinfo_t panel_info = {
-	vl_col:		480,
-	vl_row:		272,
-	vl_clk:		9000000,
-	vl_sync:	ATMEL_LCDC_INVLINE_NORMAL |
-			ATMEL_LCDC_INVFRAME_NORMAL,
-	vl_bpix:	3,
-	vl_tft:		1,
-	vl_hsync_len:	45,
-	vl_left_margin:	1,
-	vl_right_margin:1,
-	vl_vsync_len:	1,
-	vl_upper_margin:40,
-	vl_lower_margin:1,
-	mmio :		 ATMEL_BASE_LCDC,
+	.vl_col =		480,
+	.vl_row =		272,
+	.vl_clk =		9000000,
+	.vl_sync =		ATMEL_LCDC_INVLINE_NORMAL |
+				ATMEL_LCDC_INVFRAME_NORMAL,
+	.vl_bpix =		3,
+	.vl_tft =		1,
+	.vl_hsync_len =		45,
+	.vl_left_margin =	1,
+	.vl_right_margin =	1,
+	.vl_vsync_len =		1,
+	.vl_upper_margin =	40,
+	.vl_lower_margin =	1,
+	.mmio =			ATMEL_BASE_LCDC,
 };
 
 
diff --git a/board/atmel/at91sam9rlek/at91sam9rlek.c b/board/atmel/at91sam9rlek/at91sam9rlek.c
index c700a9076b..56ca1d4f7e 100644
--- a/board/atmel/at91sam9rlek/at91sam9rlek.c
+++ b/board/atmel/at91sam9rlek/at91sam9rlek.c
@@ -78,20 +78,20 @@ static void at91sam9rlek_nand_hw_init(void)
 
 #ifdef CONFIG_LCD
 vidinfo_t panel_info = {
-	vl_col:		240,
-	vl_row:		320,
-	vl_clk:		4965000,
-	vl_sync:	ATMEL_LCDC_INVLINE_INVERTED |
-			ATMEL_LCDC_INVFRAME_INVERTED,
-	vl_bpix:	3,
-	vl_tft:		1,
-	vl_hsync_len:	5,
-	vl_left_margin:	1,
-	vl_right_margin:33,
-	vl_vsync_len:	1,
-	vl_upper_margin:1,
-	vl_lower_margin:0,
-	mmio:		ATMEL_BASE_LCDC,
+	.vl_col =		240,
+	.vl_row =		320,
+	.vl_clk =		4965000,
+	.vl_sync =		ATMEL_LCDC_INVLINE_INVERTED |
+				ATMEL_LCDC_INVFRAME_INVERTED,
+	.vl_bpix =		3,
+	.vl_tft =		1,
+	.vl_hsync_len =		5,
+	.vl_left_margin =	1,
+	.vl_right_margin =	33,
+	.vl_vsync_len =		1,
+	.vl_upper_margin =	1,
+	.vl_lower_margin =	0,
+	.mmio =			ATMEL_BASE_LCDC,
 };
 
 void lcd_enable(void)
diff --git a/board/compulab/cm_t335/u-boot.lds b/board/compulab/cm_t335/u-boot.lds
index c8ab716cea..627583668a 100644
--- a/board/compulab/cm_t335/u-boot.lds
+++ b/board/compulab/cm_t335/u-boot.lds
@@ -62,6 +62,8 @@ SECTIONS
 		*(.__rel_dyn_end)
 	}
 
+	.hash : { *(.hash*) }
+
 	.end :
 	{
 		*(.__end)
@@ -99,8 +101,6 @@ SECTIONS
 	}
 
 	.dynsym _image_binary_end : { *(.dynsym) }
-	.hash : { *(.hash) }
-	.got.plt : { *(.got.plt) }
 	.dynbss : { *(.dynbss) }
 	.dynstr : { *(.dynstr*) }
 	.dynamic : { *(.dynamic*) }
diff --git a/board/cray/L1/Makefile b/board/cray/L1/Makefile
index 55402981fd..716a5a316b 100644
--- a/board/cray/L1/Makefile
+++ b/board/cray/L1/Makefile
@@ -15,13 +15,9 @@ quiet_cmd_awk = AWK     $@
 $(obj)/bootscript.c: $(obj)/bootscript.image $(src)/x2c.awk
 	$(call cmd,awk)
 
-quiet_cmd_mkimage = MKIMAGE $@
-cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \
-        $(if $(KBUILD_VERBOSE:1=), >/dev/null)
-
 MKIMAGEFLAGS_bootscript.image := -A ppc -O linux -T script -C none \
 						-a 0 -e 0 -n bootscript
 $(obj)/bootscript.image: $(src)/bootscript.hush
 	$(call cmd,mkimage)
 
-clean-files := bootscript.c bootscript.image
\ No newline at end of file
+clean-files := bootscript.c bootscript.image
diff --git a/board/eltec/elppc/misc.c b/board/eltec/elppc/misc.c
index d80eaba2d0..2acf80047f 100644
--- a/board/eltec/elppc/misc.c
+++ b/board/eltec/elppc/misc.c
@@ -7,6 +7,7 @@
 
 /* includes */
 #include <common.h>
+#include <cli.h>
 #include <linux/ctype.h>
 #include <pci.h>
 #include <net.h>
@@ -113,7 +114,7 @@ int misc_init_r (void)
 		printf ("Press key:\n  <c> to copy current revision info to nvram.\n");
 		printf ("  <r> to reenter revision info.\n");
 		printf ("=> ");
-		if (0 != readline (NULL)) {
+		if (0 != cli_readline(NULL)) {
 			switch ((char) toupper (console_buffer[0])) {
 			case 'C':
 				copyNv = 1;
@@ -130,7 +131,7 @@ int misc_init_r (void)
 		memcpy (buf, &eerev.revision[0][0], 14);	/* save all revision info */
 		printf ("Enter revision number (0-9): %c  ",
 			eerev.revision[0][0]);
-		if (0 != readline (NULL)) {
+		if (0 != cli_readline(NULL)) {
 			eerev.revision[0][0] =
 				(char) toupper (console_buffer[0]);
 			memcpy (&eerev.revision[1][0], buf, 12);	/* shift rest of rev info */
@@ -138,14 +139,14 @@ int misc_init_r (void)
 
 		printf ("Enter revision character (A-Z): %c  ",
 			eerev.revision[0][1]);
-		if (1 == readline (NULL)) {
+		if (1 == cli_readline(NULL)) {
 			eerev.revision[0][1] =
 				(char) toupper (console_buffer[0]);
 		}
 
 		printf ("Enter board name (V-XXXX-XXXX): %s  ",
 			(char *) &eerev.board);
-		if (11 == readline (NULL)) {
+		if (11 == cli_readline(NULL)) {
 			for (i = 0; i < 11; i++)
 				eerev.board[i] =
 					(char) toupper (console_buffer[i]);
@@ -153,14 +154,14 @@ int misc_init_r (void)
 		}
 
 		printf ("Enter serial number: %s ", (char *) &eerev.serial);
-		if (6 == readline (NULL)) {
+		if (6 == cli_readline(NULL)) {
 			for (i = 0; i < 6; i++)
 				eerev.serial[i] = console_buffer[i];
 			eerev.serial[6] = '\0';
 		}
 
 		printf ("Enter ether node ID with leading zero (HEX): %02x%02x%02x%02x%02x%02x  ", eerev.etheraddr[0], eerev.etheraddr[1], eerev.etheraddr[2], eerev.etheraddr[3], eerev.etheraddr[4], eerev.etheraddr[5]);
-		if (12 == readline (NULL)) {
+		if (12 == cli_readline(NULL)) {
 			for (i = 0; i < 12; i += 2)
 				eerev.etheraddr[i >> 1] =
 					(char) (16 *
@@ -175,7 +176,7 @@ int misc_init_r (void)
 		l = strlen ((char *) &eerev.text);
 		printf ("Add to text section (max 64 chr): %s ",
 			(char *) &eerev.text);
-		if (0 != readline (NULL)) {
+		if (0 != cli_readline(NULL)) {
 			for (i = l; i < 63; i++)
 				eerev.text[i] = console_buffer[i - l];
 			eerev.text[63] = '\0';
diff --git a/board/eltec/mhpc/mhpc.c b/board/eltec/mhpc/mhpc.c
index f3f564ffe4..5781b2a54f 100644
--- a/board/eltec/mhpc/mhpc.c
+++ b/board/eltec/mhpc/mhpc.c
@@ -14,6 +14,7 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <common.h>
+#include <cli.h>
 #include <linux/ctype.h>
 #include <commproc.h>
 #include "mpc8xx.h"
@@ -146,21 +147,21 @@ int misc_init_r (void)
 	if (strncmp ((char *) &mhpcRevInfo.board[2], "MHPC", 4) != 0) {
 		printf ("Enter revision number (0-9): %c  ",
 			mhpcRevInfo.revision[0]);
-		if (0 != readline (NULL)) {
+		if (0 != cli_readline(NULL)) {
 			mhpcRevInfo.revision[0] =
 				(char) toupper (console_buffer[0]);
 		}
 
 		printf ("Enter revision character (A-Z): %c  ",
 			mhpcRevInfo.revision[1]);
-		if (1 == readline (NULL)) {
+		if (1 == cli_readline(NULL)) {
 			mhpcRevInfo.revision[1] =
 				(char) toupper (console_buffer[0]);
 		}
 
 		printf ("Enter board name (V-XXXX-XXXX): %s  ",
 			(char *) &mhpcRevInfo.board);
-		if (11 == readline (NULL)) {
+		if (11 == cli_readline(NULL)) {
 			for (i = 0; i < 11; i++) {
 				mhpcRevInfo.board[i] =
 					(char) toupper (console_buffer[i]);
@@ -177,7 +178,7 @@ int misc_init_r (void)
 		do {
 			printf ("\nEnter sensor number (0-255): %d  ",
 				(int) mhpcRevInfo.sensor);
-			if (0 != readline (NULL)) {
+			if (0 != cli_readline(NULL)) {
 				mhpcRevInfo.sensor =
 					(unsigned char)
 					simple_strtoul (console_buffer, NULL,
@@ -187,7 +188,7 @@ int misc_init_r (void)
 
 		printf ("Enter serial number: %s ",
 			(char *) &mhpcRevInfo.serial);
-		if (6 == readline (NULL)) {
+		if (6 == cli_readline(NULL)) {
 			for (i = 0; i < 6; i++) {
 				mhpcRevInfo.serial[i] = console_buffer[i];
 			}
@@ -195,7 +196,7 @@ int misc_init_r (void)
 		}
 
 		printf ("Enter ether node ID with leading zero (HEX): %02x%02x%02x%02x%02x%02x  ", mhpcRevInfo.etheraddr[0], mhpcRevInfo.etheraddr[1], mhpcRevInfo.etheraddr[2], mhpcRevInfo.etheraddr[3], mhpcRevInfo.etheraddr[4], mhpcRevInfo.etheraddr[5]);
-		if (12 == readline (NULL)) {
+		if (12 == cli_readline(NULL)) {
 			for (i = 0; i < 12; i += 2) {
 				mhpcRevInfo.etheraddr[i >> 1] =
 					(char) (16 *
diff --git a/board/ep8248/Makefile b/board/ep8248/Makefile
deleted file mode 100644
index bfaf1c89d8..0000000000
--- a/board/ep8248/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= ep8248.o
diff --git a/board/ep8248/ep8248.c b/board/ep8248/ep8248.c
deleted file mode 100644
index 736c1806d1..0000000000
--- a/board/ep8248/ep8248.c
+++ /dev/null
@@ -1,254 +0,0 @@
-/*
- * Copyright (C) 2004 Arabella Software Ltd.
- * Yuli Barcohen <yuli@arabellasw.com>
- *
- * Support for Embedded Planet EP8248 boards.
- * Tested on EP8248E.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc8260.h>
-#include <ioports.h>
-
-/*
- * I/O Port configuration table
- *
- * if conf is 1, then that port pin will be configured at boot time
- * according to the five values podr/pdir/ppar/psor/pdat for that entry
- */
-
-#define CONFIG_SYS_FCC1 (CONFIG_ETHER_ON_FCC1 == 1)
-#define CONFIG_SYS_FCC2 (CONFIG_ETHER_ON_FCC2 == 1)
-
-const iop_conf_t iop_conf_tab[4][32] = {
-
-    /* Port A */
-    {	/*	      conf      ppar psor pdir podr pdat */
-	/* PA31 */ { CONFIG_SYS_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII COL    */
-	/* PA30 */ { CONFIG_SYS_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII CRS    */
-	/* PA29 */ { CONFIG_SYS_FCC1,   1,   1,   1,   0,   0 }, /* FCC1 MII TX_ER  */
-	/* PA28 */ { CONFIG_SYS_FCC1,   1,   1,   1,   0,   0 }, /* FCC1 MII TX_EN  */
-	/* PA27 */ { CONFIG_SYS_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII RX_DV  */
-	/* PA26 */ { CONFIG_SYS_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII RX_ER  */
-	/* PA25 */ { 0,          0,   0,   0,   0,   0 }, /* PA25            */
-	/* PA24 */ { 0,          0,   0,   0,   0,   0 }, /* PA24            */
-	/* PA23 */ { 0,          0,   0,   0,   0,   0 }, /* PA23            */
-	/* PA22 */ { 0,          0,   0,   0,   0,   0 }, /* PA22            */
-	/* PA21 */ { CONFIG_SYS_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[3] */
-	/* PA20 */ { CONFIG_SYS_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[2] */
-	/* PA19 */ { CONFIG_SYS_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[1] */
-	/* PA18 */ { CONFIG_SYS_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[0] */
-	/* PA17 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[0] */
-	/* PA16 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[1] */
-	/* PA15 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[2] */
-	/* PA14 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[3] */
-	/* PA13 */ { 0,          0,   0,   0,   0,   0 }, /* PA13            */
-	/* PA12 */ { 0,          0,   0,   0,   0,   0 }, /* PA12            */
-	/* PA11 */ { 0,          0,   0,   0,   0,   0 }, /* PA11            */
-	/* PA10 */ { 0,          0,   0,   0,   0,   0 }, /* PA10            */
-	/* PA9  */ { 0,          1,   0,   1,   0,   0 }, /* SMC2 TxD        */
-	/* PA8  */ { 0,          1,   0,   0,   0,   0 }, /* SMC2 RxD        */
-	/* PA7  */ { 0,          0,   0,   0,   0,   0 }, /* PA7             */
-	/* PA6  */ { 0,          0,   0,   0,   0,   0 }, /* PA6             */
-	/* PA5  */ { 0,          0,   0,   0,   0,   0 }, /* PA5             */
-	/* PA4  */ { 0,          0,   0,   0,   0,   0 }, /* PA4             */
-	/* PA3  */ { 0,          0,   0,   0,   0,   0 }, /* PA3             */
-	/* PA2  */ { 0,          0,   0,   0,   0,   0 }, /* PA2             */
-	/* PA1  */ { 0,          0,   0,   0,   0,   0 }, /* PA1             */
-	/* PA0  */ { 0,          0,   0,   0,   0,   0 }  /* PA0             */
-    },
-
-    /* Port B */
-    {   /*	      conf      ppar psor pdir podr pdat */
-	/* PB31 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TX_ER  */
-	/* PB30 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RX_DV  */
-	/* PB29 */ { CONFIG_SYS_FCC2,   1,   1,   1,   0,   0 }, /* FCC2 MII TX_EN  */
-	/* PB28 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RX_ER  */
-	/* PB27 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII COL    */
-	/* PB26 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII CRS    */
-	/* PB25 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[3] */
-	/* PB24 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[2] */
-	/* PB23 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[1] */
-	/* PB22 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[0] */
-	/* PB21 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[0] */
-	/* PB20 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[1] */
-	/* PB19 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[2] */
-	/* PB18 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[3] */
-	/* PB17 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
-	/* PB16 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
-	/* PB15 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
-	/* PB14 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
-	/* PB13 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
-	/* PB12 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
-	/* PB11 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
-	/* PB10 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
-	/* PB9  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
-	/* PB8  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
-	/* PB7  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
-	/* PB6  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
-	/* PB5  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
-	/* PB4  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
-	/* PB3  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
-	/* PB2  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
-	/* PB1  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
-	/* PB0  */ { 0,          0,   0,   0,   0,   0 }  /* non-existent    */
-    },
-
-    /* Port C */
-    {   /*	      conf      ppar psor pdir podr pdat */
-	/* PC31 */ { 0,          0,   0,   0,   0,   0 }, /* PC31            */
-	/* PC30 */ { 0,          0,   0,   0,   0,   0 }, /* PC30            */
-	/* PC29 */ { 0,          0,   0,   0,   0,   0 }, /* PC29            */
-	/* PC28 */ { 0,          0,   0,   0,   0,   0 }, /* PC28            */
-	/* PC27 */ { 0,          0,   0,   0,   0,   0 }, /* PC27            */
-	/* PC26 */ { 0,          0,   0,   0,   0,   0 }, /* PC26            */
-	/* PC25 */ { 0,          0,   0,   0,   0,   0 }, /* PC25            */
-	/* PC24 */ { 0,          0,   0,   0,   0,   0 }, /* PC24            */
-	/* PC23 */ { 0,          0,   0,   0,   0,   0 }, /* PC23            */
-	/* PC22 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 RxClk (CLK10) */
-	/* PC21 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 TxClk (CLK11) */
-	/* PC20 */ { 0,          0,   0,   0,   0,   0 }, /* PC20            */
-	/* PC19 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 RxClk (CLK13) */
-	/* PC18 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 TxClk (CLK14) */
-	/* PC17 */ { 0,          0,   0,   0,   0,   0 }, /* PC17            */
-	/* PC16 */ { 0,          0,   0,   0,   0,   0 }, /* PC16            */
-	/* PC15 */ { 0,          0,   0,   0,   0,   0 }, /* PC15            */
-	/* PC14 */ { 0,          0,   0,   0,   0,   0 }, /* PC14            */
-	/* PC13 */ { 0,          0,   0,   0,   0,   0 }, /* PC13            */
-	/* PC12 */ { 0,          0,   0,   0,   0,   0 }, /* PC12            */
-	/* PC11 */ { 0,          0,   0,   0,   0,   0 }, /* PC11            */
-	/* PC10 */ { 0,          0,   0,   0,   0,   0 }, /* PC10            */
-	/* PC9  */ { 1,          0,   0,   1,   0,   1 }, /* MDIO            */
-	/* PC8  */ { 1,          0,   0,   1,   0,   1 }, /* MDC             */
-	/* PC7  */ { 0,          0,   0,   0,   0,   0 }, /* PC7             */
-	/* PC6  */ { 0,          0,   0,   0,   0,   0 }, /* PC6             */
-	/* PC5  */ { 1,          1,   0,   1,   0,   0 }, /* SMC1 TxD        */
-	/* PC4  */ { 1,          1,   0,   0,   0,   0 }, /* SMC1 RxD        */
-	/* PC3  */ { 0,          0,   0,   0,   0,   0 }, /* PC3             */
-	/* PC2  */ { 0,          0,   0,   0,   0,   0 }, /* PC2             */
-	/* PC1  */ { 0,          0,   0,   0,   0,   0 }, /* PC1             */
-	/* PC0  */ { 0,          0,   0,   0,   0,   0 }, /* PC0             */
-    },
-
-    /* Port D */
-    {   /*	      conf      ppar psor pdir podr pdat */
-	/* PD31 */ { 1,          1,   0,   0,   0,   0 }, /* SCC1 RxD        */
-	/* PD30 */ { 1,          1,   1,   1,   0,   0 }, /* SCC1 TxD        */
-	/* PD29 */ { 0,          0,   0,   0,   0,   0 }, /* PD29            */
-	/* PD28 */ { 0,          0,   0,   0,   0,   0 }, /* PD28            */
-	/* PD27 */ { 0,          0,   0,   0,   0,   0 }, /* PD27            */
-	/* PD26 */ { 0,          0,   0,   0,   0,   0 }, /* PD26            */
-	/* PD25 */ { 0,          0,   0,   0,   0,   0 }, /* PD25            */
-	/* PD24 */ { 0,          0,   0,   0,   0,   0 }, /* PD24            */
-	/* PD23 */ { 0,          0,   0,   0,   0,   0 }, /* PD23            */
-	/* PD22 */ { 0,          0,   0,   0,   0,   0 }, /* PD22            */
-	/* PD21 */ { 0,          0,   0,   0,   0,   0 }, /* PD21            */
-	/* PD20 */ { 0,          0,   0,   0,   0,   0 }, /* PD20            */
-	/* PD19 */ { 0,          0,   0,   0,   0,   0 }, /* PD19            */
-	/* PD18 */ { 0,          0,   0,   0,   0,   0 }, /* PD18            */
-	/* PD17 */ { 0,          0,   0,   0,   0,   0 }, /* PD17            */
-	/* PD16 */ { 0,          0,   0,   0,   0,   0 }, /* PD16            */
-	/* PD15 */ { 1,          1,   1,   0,   1,   0 }, /* I2C SDA         */
-	/* PD14 */ { 1,          1,   1,   0,   1,   0 }, /* I2C SCL         */
-	/* PD13 */ { 0,          0,   0,   0,   0,   0 }, /* PD13            */
-	/* PD12 */ { 0,          0,   0,   0,   0,   0 }, /* PD12            */
-	/* PD11 */ { 0,          0,   0,   0,   0,   0 }, /* PD11            */
-	/* PD10 */ { 0,          0,   0,   0,   0,   0 }, /* PD10            */
-	/* PD9  */ { 0,          0,   0,   0,   0,   0 }, /* PD9             */
-	/* PD8  */ { 0,          0,   0,   0,   0,   0 }, /* PD8             */
-	/* PD7  */ { 0,          0,   0,   0,   0,   0 }, /* PD7             */
-	/* PD6  */ { 0,          0,   0,   0,   0,   0 }, /* PD6             */
-	/* PD5  */ { 0,          0,   0,   0,   0,   0 }, /* PD5             */
-	/* PD4  */ { 0,          0,   0,   0,   0,   0 }, /* PD4             */
-	/* PD3  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
-	/* PD2  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
-	/* PD1  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
-	/* PD0  */ { 0,          0,   0,   0,   0,   0 }  /* non-existent    */
-    }
-};
-
-int board_early_init_f (void)
-{
-	vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR;
-
-	bcsr[4] |= 0x30; /* Turn the LEDs off */
-
-#if defined(CONFIG_CONS_ON_SMC) || defined(CONFIG_KGDB_ON_SMC)
-	bcsr[6] |= 0x10;
-#endif
-#if defined(CONFIG_CONS_ON_SCC) || defined(CONFIG_KGDB_ON_SCC)
-	bcsr[7] |= 0x10;
-#endif
-
-#if CONFIG_SYS_FCC1
-	bcsr[8] |= 0xC0;
-#endif /* CONFIG_SYS_FCC1 */
-#if CONFIG_SYS_FCC2
-	bcsr[8] |= 0x30;
-#endif /* CONFIG_SYS_FCC2 */
-
-	return 0;
-}
-
-phys_size_t initdram(int board_type)
-{
-	vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR;
-	long int msize = 16L << (bcsr[2] & 3);
-
-#ifndef CONFIG_SYS_RAMBOOT
-	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
-	volatile memctl8260_t *memctl = &immap->im_memctl;
-	vu_char *ramaddr = (vu_char *)CONFIG_SYS_SDRAM_BASE;
-	uchar c = 0xFF;
-	uint psdmr = CONFIG_SYS_PSDMR;
-	int i;
-
-	immap->im_siu_conf.sc_ppc_acr  = 0x02;
-	immap->im_siu_conf.sc_ppc_alrh = 0x30126745;
-	immap->im_siu_conf.sc_tescr1   = 0x00004000;
-
-	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
-
-	/* Initialise 60x bus SDRAM */
-	memctl->memc_psrt = CONFIG_SYS_PSRT;
-	memctl->memc_or1  = CONFIG_SYS_SDRAM_OR;
-	memctl->memc_br1  = CONFIG_SYS_SDRAM_BR;
-	memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; /* Precharge all banks */
-	*ramaddr = c;
-	memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */
-	for (i = 0; i < 8; i++)
-		*ramaddr = c;
-	memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;  /* Mode Register write */
-	*ramaddr = c;
-	memctl->memc_psdmr = psdmr | PSDMR_RFEN;    /* Refresh enable */
-	*ramaddr = c;
-#endif /* !CONFIG_SYS_RAMBOOT */
-
-	/* Return total 60x bus SDRAM size */
-	return msize * 1024 * 1024;
-}
-
-int checkboard(void)
-{
-	vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR;
-
-	puts("Board: ");
-	switch (bcsr[0]) {
-	case 0x0C:
-		printf("EP8248E 1.0 CPLD revision %d\n", bcsr[1]);
-		break;
-	default:
-		printf("unknown: ID=%02X\n", bcsr[0]);
-	}
-
-	return 0;
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
-void ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup( blob, bd);
-}
-#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
diff --git a/board/etin/debris/Makefile b/board/etin/debris/Makefile
deleted file mode 100644
index 2e74823ea6..0000000000
--- a/board/etin/debris/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y =  debris.o flash.o phantom.o
diff --git a/board/etin/debris/debris.c b/board/etin/debris/debris.c
deleted file mode 100644
index 0308fef6cf..0000000000
--- a/board/etin/debris/debris.c
+++ /dev/null
@@ -1,174 +0,0 @@
-/*
- * (C) Copyright 2000
- * Sangmoon Kim, Etin Systems. dogoil@etinsys.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc824x.h>
-#include <net.h>
-#include <pci.h>
-#include <i2c.h>
-#include <netdev.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard (void)
-{
-	/*TODO: Check processor type */
-
-	puts (	"Board: Debris "
-#ifdef CONFIG_MPC8240
-		"8240"
-#endif
-#ifdef CONFIG_MPC8245
-		"8245"
-#endif
-		" ##Test not implemented yet##\n");
-	return 0;
-}
-
-#if 0	/* NOT USED */
-int checkflash (void)
-{
-	/* TODO: XXX XXX XXX */
-	printf ("## Test not implemented yet ##\n");
-
-	return (0);
-}
-#endif
-
-phys_size_t initdram (int board_type)
-{
-	int m, row, col, bank, i;
-	unsigned long start, end;
-	uint32_t mccr1;
-	uint32_t mear1 = 0, emear1 = 0, msar1 = 0, emsar1 = 0;
-	uint32_t mear2 = 0, emear2 = 0, msar2 = 0, emsar2 = 0;
-	uint8_t mber = 0;
-
-	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-
-	if (i2c_reg_read (0x50, 2) != 0x04) return 0;	/* Memory type */
-	m = i2c_reg_read (0x50, 5);	/* # of physical banks */
-	row = i2c_reg_read (0x50, 3);	/* # of rows */
-	col = i2c_reg_read (0x50, 4);	/* # of columns */
-	bank = i2c_reg_read (0x50, 17);	/* # of logical banks */
-
-	CONFIG_READ_WORD(MCCR1, mccr1);
-	mccr1 &= 0xffff0000;
-
-	start = CONFIG_SYS_SDRAM_BASE;
-	end = start + (1 << (col + row + 3) ) * bank - 1;
-
-	for (i = 0; i < m; i++) {
-		mccr1 |= ((row == 13)? 2 : (bank == 4)? 0 : 3) << i * 2;
-		if (i < 4) {
-			msar1  |= ((start >> 20) & 0xff) << i * 8;
-			emsar1 |= ((start >> 28) & 0xff) << i * 8;
-			mear1  |= ((end >> 20) & 0xff) << i * 8;
-			emear1 |= ((end >> 28) & 0xff) << i * 8;
-		} else {
-			msar2  |= ((start >> 20) & 0xff) << (i-4) * 8;
-			emsar2 |= ((start >> 28) & 0xff) << (i-4) * 8;
-			mear2  |= ((end >> 20) & 0xff) << (i-4) * 8;
-			emear2 |= ((end >> 28) & 0xff) << (i-4) * 8;
-		}
-		mber |= 1 << i;
-		start += (1 << (col + row + 3) ) * bank;
-		end += (1 << (col + row + 3) ) * bank;
-	}
-	for (; i < 8; i++) {
-		if (i < 4) {
-			msar1  |= 0xff << i * 8;
-			emsar1 |= 0x30 << i * 8;
-			mear1  |= 0xff << i * 8;
-			emear1 |= 0x30 << i * 8;
-		} else {
-			msar2  |= 0xff << (i-4) * 8;
-			emsar2 |= 0x30 << (i-4) * 8;
-			mear2  |= 0xff << (i-4) * 8;
-			emear2 |= 0x30 << (i-4) * 8;
-		}
-	}
-
-	CONFIG_WRITE_WORD(MCCR1, mccr1);
-	CONFIG_WRITE_WORD(MSAR1, msar1);
-	CONFIG_WRITE_WORD(EMSAR1, emsar1);
-	CONFIG_WRITE_WORD(MEAR1, mear1);
-	CONFIG_WRITE_WORD(EMEAR1, emear1);
-	CONFIG_WRITE_WORD(MSAR2, msar2);
-	CONFIG_WRITE_WORD(EMSAR2, emsar2);
-	CONFIG_WRITE_WORD(MEAR2, mear2);
-	CONFIG_WRITE_WORD(EMEAR2, emear2);
-	CONFIG_WRITE_BYTE(MBER, mber);
-
-	return (1 << (col + row + 3) ) * bank * m;
-}
-
-/*
- * Initialize PCI Devices, report devices found.
- */
-#ifndef CONFIG_PCI_PNP
-static struct pci_config_table pci_debris_config_table[] = {
-	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
-	  pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
-				       PCI_ENET0_MEMADDR,
-				       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
-	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x10, PCI_ANY_ID,
-	  pci_cfgfunc_config_device, { PCI_ENET1_IOADDR,
-				       PCI_ENET1_MEMADDR,
-				       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
-	{ }
-};
-#endif
-
-struct pci_controller hose = {
-#ifndef CONFIG_PCI_PNP
-	config_table: pci_debris_config_table,
-#endif
-};
-
-void pci_init_board(void)
-{
-	pci_mpc824x_init(&hose);
-}
-
-void *nvram_read(void *dest, const long src, size_t count)
-{
-	volatile uchar *d = (volatile uchar*) dest;
-	volatile uchar *s = (volatile uchar*) src;
-	while(count--) {
-		*d++ = *s++;
-		asm volatile("sync");
-	}
-	return dest;
-}
-
-void nvram_write(long dest, const void *src, size_t count)
-{
-	volatile uchar *d = (volatile uchar*)dest;
-	volatile uchar *s = (volatile uchar*)src;
-	while(count--) {
-		*d++ = *s++;
-		asm volatile("sync");
-	}
-}
-
-int misc_init_r(void)
-{
-	uchar ethaddr[6];
-
-	if (eth_getenv_enetaddr("ethaddr", ethaddr))
-		/* Write ethernet addr in NVRAM for VxWorks */
-		nvram_write(CONFIG_ENV_ADDR + CONFIG_SYS_NVRAM_VXWORKS_OFFS,
-				ethaddr, 6);
-
-	return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
-	return pci_eth_init(bis);
-}
diff --git a/board/etin/debris/flash.c b/board/etin/debris/flash.c
deleted file mode 100644
index 26579588dd..0000000000
--- a/board/etin/debris/flash.c
+++ /dev/null
@@ -1,705 +0,0 @@
-/*
- * board/eva/flash.c
- *
- * (C) Copyright 2002
- * Sangmoon Kim, Etin Systems, dogoil@etinsys.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/pci_io.h>
-#include <mpc824x.h>
-#include <asm/mmu.h>
-
-int (*do_flash_erase)(flash_info_t*, uint32_t, uint32_t);
-int (*write_dword)(flash_info_t*, ulong, uint64_t);
-
-typedef uint64_t cfi_word;
-
-#define cfi_read(flash, addr) *((volatile cfi_word*)(flash->start[0] + addr))
-
-#define cfi_write(flash, val, addr) \
-	move64((cfi_word*)&val, \
-			(cfi_word*)(flash->start[0] + addr))
-
-#define CMD(x) ((((cfi_word)x)<<48)|(((cfi_word)x)<<32)|(((cfi_word)x)<<16)|(((cfi_word)x)))
-
-static void write32(unsigned long addr, uint32_t value)
-{
-	*(volatile uint32_t*)(addr) = value;
-	asm volatile("sync");
-}
-
-static uint32_t read32(unsigned long addr)
-{
-	uint32_t value;
-	value = *(volatile uint32_t*)addr;
-	asm volatile("sync");
-	return value;
-}
-
-static cfi_word cfi_cmd(flash_info_t *flash, uint8_t cmd, uint32_t addr)
-{
-	uint32_t base = flash->start[0];
-	uint32_t val=(cmd << 16) | cmd;
-	addr <<= 3;
-	write32(base + addr, val);
-	return addr;
-}
-
-static uint16_t cfi_read_query(flash_info_t *flash, uint32_t addr)
-{
-	uint32_t base = flash->start[0];
-	addr <<= 3;
-	return (uint16_t)read32(base + addr);
-}
-
-flash_info_t    flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-static void move64(uint64_t *src, uint64_t *dest)
-{
-	asm volatile("lfd  0, 0(3)\n\t" /* fpr0   =  *scr       */
-	 "stfd 0, 0(4)"         /* *dest  =  fpr0       */
-	 : : : "fr0" );         /* Clobbers fr0         */
-	return;
-}
-
-static int cfi_write_dword(flash_info_t *flash, ulong dest, cfi_word data)
-{
-	unsigned long start;
-	cfi_word status = 0;
-
-	status = cfi_read(flash, dest);
-	data &= status;
-
-	cfi_cmd(flash, 0x40, 0);
-	cfi_write(flash, data, dest);
-
-	udelay(10);
-	start = get_timer (0);
-	for(;;) {
-		status = cfi_read(flash, dest);
-		status &= CMD(0x80);
-		if(status == CMD(0x80))
-			break;
-		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
-			cfi_cmd(flash, 0xff, 0);
-			return 1;
-		}
-		udelay(1);
-	}
-	cfi_cmd(flash, 0xff, 0);
-
-	return 0;
-}
-
-static int jedec_write_dword (flash_info_t *flash, ulong dest, cfi_word data)
-{
-	ulong start;
-	cfi_word status = 0;
-
-	status = cfi_read(flash, dest);
-	if(status != CMD(0xffff)) return 2;
-
-	cfi_cmd(flash, 0xaa, 0x555);
-	cfi_cmd(flash, 0x55, 0x2aa);
-	cfi_cmd(flash, 0xa0, 0x555);
-
-	cfi_write(flash, data, dest);
-
-	udelay(10);
-	start = get_timer (0);
-	status = ~data;
-	while(status != data) {
-		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT)
-			return 1;
-		status = cfi_read(flash, dest);
-		udelay(1);
-	}
-	return 0;
-}
-
-static __inline__ unsigned long get_msr(void)
-{
-	unsigned long msr;
-	__asm__ __volatile__ ("mfmsr %0" : "=r" (msr) :);
-	return msr;
-}
-
-static __inline__ void set_msr(unsigned long msr)
-{
-	__asm__ __volatile__ ("mtmsr %0" : : "r" (msr));
-}
-
-int write_buff (flash_info_t *flash, uchar *src, ulong addr, ulong cnt)
-{
-	ulong wp;
-	int i, s, l, rc;
-	cfi_word data;
-	uint8_t *t = (uint8_t*)&data;
-	unsigned long base = flash->start[0];
-	uint32_t msr;
-
-	if (flash->flash_id == FLASH_UNKNOWN)
-		return 4;
-
-	if (cnt == 0)
-		return 0;
-
-	addr -= base;
-
-	msr = get_msr();
-	set_msr(msr|MSR_FP);
-
-	wp = (addr & ~7);   /* get lower word aligned address */
-
-	if((addr-wp) != 0) {
-		data = cfi_read(flash, wp);
-		s = addr & 7;
-		l = ( cnt < (8-s) ) ? cnt : (8-s);
-		for(i = 0; i < l; i++)
-			t[s+i] = *src++;
-		if ((rc = write_dword(flash, wp, data)) != 0)
-			goto DONE;
-		wp += 8;
-		cnt -= l;
-	}
-
-	while (cnt >= 8) {
-		for (i = 0; i < 8; i++)
-			t[i] = *src++;
-		if ((rc = write_dword(flash, wp, data)) != 0)
-			goto DONE;
-		wp  += 8;
-		cnt -= 8;
-	}
-
-	if (cnt == 0) {
-		rc = 0;
-		goto DONE;
-	}
-
-	data = cfi_read(flash, wp);
-	for(i = 0; i < cnt; i++)
-		t[i] = *src++;
-	rc = write_dword(flash, wp, data);
-DONE:
-	set_msr(msr);
-	return rc;
-}
-
-static int cfi_erase_oneblock(flash_info_t *flash, uint32_t sect)
-{
-	int sa;
-	int flag;
-	ulong start, last, now;
-	cfi_word status;
-
-	flag = disable_interrupts();
-
-	sa = (flash->start[sect] - flash->start[0]);
-	write32(flash->start[sect], 0x00200020);
-	write32(flash->start[sect], 0x00d000d0);
-
-	if (flag)
-		enable_interrupts();
-
-	udelay(1000);
-	start = get_timer (0);
-	last  = start;
-
-	for (;;) {
-		status = cfi_read(flash, sa);
-		status &= CMD(0x80);
-		if (status == CMD(0x80))
-			break;
-		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
-			cfi_cmd(flash, 0xff, 0);
-			printf ("Timeout\n");
-			return ERR_TIMOUT;
-		}
-
-		if ((now - last) > 1000) {
-			serial_putc ('.');
-			last = now;
-		}
-		udelay(10);
-	}
-	cfi_cmd(flash, 0xff, 0);
-	return ERR_OK;
-}
-
-static int cfi_erase(flash_info_t *flash, uint32_t s_first, uint32_t s_last)
-{
-	int sect;
-	int rc = ERR_OK;
-
-	for (sect = s_first; sect <= s_last; sect++) {
-		if (flash->protect[sect] == 0) {
-			rc = cfi_erase_oneblock(flash, sect);
-			if (rc != ERR_OK) break;
-		}
-	}
-	printf (" done\n");
-	return rc;
-}
-
-static int jedec_erase(flash_info_t *flash, uint32_t s_first, uint32_t s_last)
-{
-	int sect;
-	cfi_word status;
-	int sa = -1;
-	int flag;
-	ulong start, last, now;
-
-	flag = disable_interrupts();
-
-	cfi_cmd(flash, 0xaa, 0x555);
-	cfi_cmd(flash, 0x55, 0x2aa);
-	cfi_cmd(flash, 0x80, 0x555);
-	cfi_cmd(flash, 0xaa, 0x555);
-	cfi_cmd(flash, 0x55, 0x2aa);
-	for ( sect = s_first; sect <= s_last; sect++) {
-		if (flash->protect[sect] == 0) {
-			sa = flash->start[sect] - flash->start[0];
-			write32(flash->start[sect], 0x00300030);
-		}
-	}
-	if (flag)
-		enable_interrupts();
-
-	if (sa < 0)
-		goto DONE;
-
-	udelay (1000);
-	start = get_timer (0);
-	last  = start;
-	for(;;) {
-		status = cfi_read(flash, sa);
-		if (status == CMD(0xffff))
-			break;
-
-		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
-			printf ("Timeout\n");
-			return ERR_TIMOUT;
-		}
-
-		if ((now - last) > 1000) {
-			serial_putc ('.');
-			last = now;
-		}
-		udelay(10);
-	}
-DONE:
-	cfi_cmd(flash, 0xf0, 0);
-
-	printf (" done\n");
-
-	return ERR_OK;
-}
-
-int flash_erase (flash_info_t *flash, int s_first, int s_last)
-{
-	int sect;
-	int prot;
-
-	if ((s_first < 0) || (s_first > s_last)) {
-		if (flash->flash_id == FLASH_UNKNOWN)
-			printf ("- missing\n");
-		else
-			printf ("- no sectors to erase\n");
-		return ERR_NOT_ERASED;
-	}
-	if (flash->flash_id == FLASH_UNKNOWN) {
-		printf ("Can't erase unknown flash type - aborted\n");
-		return ERR_NOT_ERASED;
-	}
-
-	prot = 0;
-	for (sect = s_first; sect <= s_last; sect++)
-		if (flash->protect[sect]) prot++;
-
-	if (prot)
-		printf ("- Warning: %d protected sectors will not be erased!\n",
-								prot);
-	else
-		printf ("\n");
-
-	return do_flash_erase(flash, s_first, s_last);
-}
-
-struct jedec_flash_info {
-	const uint16_t mfr_id;
-	const uint16_t dev_id;
-	const char *name;
-	const int DevSize;
-	const int InterfaceDesc;
-	const int NumEraseRegions;
-	const ulong regions[4];
-};
-
-#define ERASEINFO(size,blocks) (size<<8)|(blocks-1)
-
-#define SIZE_1MiB 20
-#define SIZE_2MiB 21
-#define SIZE_4MiB 22
-
-static const struct jedec_flash_info jedec_table[] = {
-	{
-		mfr_id: (uint16_t)AMD_MANUFACT,
-		dev_id: (uint16_t)AMD_ID_LV800T,
-		name: "AMD AM29LV800T",
-		DevSize: SIZE_1MiB,
-		NumEraseRegions: 4,
-		regions: {ERASEINFO(0x10000,15),
-			  ERASEINFO(0x08000,1),
-			  ERASEINFO(0x02000,2),
-			  ERASEINFO(0x04000,1)
-		}
-	}, {
-		mfr_id: (uint16_t)AMD_MANUFACT,
-		dev_id: (uint16_t)AMD_ID_LV800B,
-		name: "AMD AM29LV800B",
-		DevSize: SIZE_1MiB,
-		NumEraseRegions: 4,
-		regions: {ERASEINFO(0x10000,15),
-			  ERASEINFO(0x08000,1),
-			  ERASEINFO(0x02000,2),
-			  ERASEINFO(0x04000,1)
-		}
-	}, {
-		mfr_id: (uint16_t)AMD_MANUFACT,
-		dev_id: (uint16_t)AMD_ID_LV160T,
-		name: "AMD AM29LV160T",
-		DevSize: SIZE_2MiB,
-		NumEraseRegions: 4,
-		regions: {ERASEINFO(0x10000,31),
-			  ERASEINFO(0x08000,1),
-			  ERASEINFO(0x02000,2),
-			  ERASEINFO(0x04000,1)
-		}
-	}, {
-		mfr_id: (uint16_t)AMD_MANUFACT,
-		dev_id: (uint16_t)AMD_ID_LV160B,
-		name: "AMD AM29LV160B",
-		DevSize: SIZE_2MiB,
-		NumEraseRegions: 4,
-		regions: {ERASEINFO(0x04000,1),
-			  ERASEINFO(0x02000,2),
-			  ERASEINFO(0x08000,1),
-			  ERASEINFO(0x10000,31)
-		}
-	}, {
-		mfr_id: (uint16_t)AMD_MANUFACT,
-		dev_id: (uint16_t)AMD_ID_LV320T,
-		name: "AMD AM29LV320T",
-		DevSize: SIZE_4MiB,
-		NumEraseRegions: 2,
-		regions: {ERASEINFO(0x10000,63),
-			  ERASEINFO(0x02000,8)
-		}
-
-	}, {
-		mfr_id: (uint16_t)AMD_MANUFACT,
-		dev_id: (uint16_t)AMD_ID_LV320B,
-		name: "AMD AM29LV320B",
-		DevSize: SIZE_4MiB,
-		NumEraseRegions: 2,
-		regions: {ERASEINFO(0x02000,8),
-			  ERASEINFO(0x10000,63)
-		}
-	}
-};
-
-static ulong cfi_init(uint32_t base,  flash_info_t *flash)
-{
-	int sector;
-	int block;
-	int block_count;
-	int offset = 0;
-	int reverse = 0;
-	int primary;
-	int mfr_id;
-	int dev_id;
-
-	flash->start[0] = base;
-	cfi_cmd(flash, 0xF0, 0);
-	cfi_cmd(flash, 0x98, 0);
-	if ( !( cfi_read_query(flash, 0x10) == 'Q' &&
-		cfi_read_query(flash, 0x11) == 'R' &&
-		cfi_read_query(flash, 0x12) == 'Y' )) {
-		cfi_cmd(flash, 0xff, 0);
-		return 0;
-	}
-
-	flash->size = 1 << cfi_read_query(flash, 0x27);
-	flash->size *= 4;
-	block_count = cfi_read_query(flash, 0x2c);
-	primary = cfi_read_query(flash, 0x15);
-	if ( cfi_read_query(flash, primary + 4) == 0x30)
-		reverse = (cfi_read_query(flash, 0x1) & 0x01);
-	else
-		reverse = (cfi_read_query(flash, primary+15) == 3);
-
-	flash->sector_count = 0;
-
-	for ( block = reverse ? block_count - 1	: 0;
-		      reverse ? block >= 0	: block < block_count;
-		      reverse ? block--		: block ++) {
-		int sector_size =
-			(cfi_read_query(flash, 0x2d + block*4+2) |
-			(cfi_read_query(flash, 0x2d + block*4+3) << 8)) << 8;
-		int sector_count =
-			(cfi_read_query(flash, 0x2d + block*4+0) |
-			(cfi_read_query(flash, 0x2d + block*4+1) << 8)) + 1;
-		for(sector = 0; sector < sector_count; sector++) {
-			flash->start[flash->sector_count++] = base + offset;
-			offset += sector_size * 4;
-		}
-	}
-	mfr_id = cfi_read_query(flash, 0x00);
-	dev_id = cfi_read_query(flash, 0x01);
-
-	cfi_cmd(flash, 0xff, 0);
-
-	flash->flash_id = (mfr_id << 16) | dev_id;
-
-	for (sector = 0; sector < flash->sector_count; sector++) {
-		write32(flash->start[sector], 0x00600060);
-		write32(flash->start[sector], 0x00d000d0);
-	}
-	cfi_cmd(flash, 0xff, 0);
-
-	for (sector = 0; sector < flash->sector_count; sector++)
-		flash->protect[sector] = 0;
-
-	do_flash_erase = cfi_erase;
-	write_dword = cfi_write_dword;
-
-	return flash->size;
-}
-
-static ulong jedec_init(unsigned long base, flash_info_t *flash)
-{
-	int i;
-	int block, block_count;
-	int sector, offset;
-	int mfr_id, dev_id;
-	flash->start[0] = base;
-	cfi_cmd(flash, 0xF0, 0x000);
-	cfi_cmd(flash, 0xAA, 0x555);
-	cfi_cmd(flash, 0x55, 0x2AA);
-	cfi_cmd(flash, 0x90, 0x555);
-	mfr_id = cfi_read_query(flash, 0x000);
-	dev_id = cfi_read_query(flash, 0x0001);
-	cfi_cmd(flash, 0xf0, 0x000);
-
-	for(i=0; i<sizeof(jedec_table)/sizeof(struct jedec_flash_info); i++) {
-		if((jedec_table[i].mfr_id == mfr_id) &&
-			(jedec_table[i].dev_id == dev_id)) {
-
-			flash->flash_id = (mfr_id << 16) | dev_id;
-			flash->size = 1 << jedec_table[0].DevSize;
-			flash->size *= 4;
-			block_count = jedec_table[i].NumEraseRegions;
-			offset = 0;
-			flash->sector_count = 0;
-			for (block = 0; block < block_count; block++) {
-				int sector_size = jedec_table[i].regions[block];
-				int sector_count = (sector_size & 0xff) + 1;
-				sector_size >>= 8;
-				for (sector=0; sector<sector_count; sector++) {
-					flash->start[flash->sector_count++] =
-						base + offset;
-					offset += sector_size * 4;
-				}
-			}
-			break;
-		}
-	}
-
-	for (sector = 0; sector < flash->sector_count; sector++)
-		flash->protect[sector] = 0;
-
-	do_flash_erase = jedec_erase;
-	write_dword = jedec_write_dword;
-
-	return flash->size;
-}
-
-inline void mtibat1u(unsigned int x)
-{
-	__asm__ __volatile__ ("mtspr   530, %0" :: "r" (x));
-}
-
-inline void mtibat1l(unsigned int x)
-{
-	__asm__ __volatile__ ("mtspr   531, %0" :: "r" (x));
-}
-
-inline void mtdbat1u(unsigned int x)
-{
-	__asm__ __volatile__ ("mtspr   538, %0" :: "r" (x));
-}
-
-inline void mtdbat1l(unsigned int x)
-{
-	__asm__ __volatile__ ("mtspr   539, %0" :: "r" (x));
-}
-
-unsigned long flash_init (void)
-{
-	unsigned long size = 0;
-	int i;
-	unsigned int msr;
-
-	/* BAT1 */
-	CONFIG_WRITE_WORD(ERCR3, 0x0C00000C);
-	CONFIG_WRITE_WORD(ERCR4, 0x0800000C);
-	msr = get_msr();
-	set_msr(msr & ~(MSR_IR | MSR_DR));
-	mtibat1l(0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT);
-	mtibat1u(0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP);
-	mtdbat1l(0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT);
-	mtdbat1u(0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP);
-	set_msr(msr);
-
-	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
-		flash_info[i].flash_id = FLASH_UNKNOWN;
-	size = cfi_init(FLASH_BASE0_PRELIM, &flash_info[0]);
-	if (!size)
-		size = jedec_init(FLASH_BASE0_PRELIM, &flash_info[0]);
-
-	if (flash_info[0].flash_id == FLASH_UNKNOWN)
-		printf ("# Unknown FLASH on Bank 1 - Size = 0x%08lx = %ld MB\n",
-			size, size<<20);
-
-	return size;
-}
-
-void flash_print_info  (flash_info_t *flash)
-{
-	int i;
-	int k;
-	int size;
-	int erased;
-	volatile unsigned long *p;
-
-	if (flash->flash_id == FLASH_UNKNOWN) {
-		printf ("missing or unknown FLASH type\n");
-		flash_init();
-	}
-
-	if (flash->flash_id == FLASH_UNKNOWN) {
-		printf ("missing or unknown FLASH type\n");
-		return;
-	}
-
-	switch (((flash->flash_id) >> 16) & 0xff) {
-	case 0x01:
-		printf ("AMD ");
-		break;
-	case 0x04:
-		printf("FUJITSU ");
-		break;
-	case 0x20:
-		printf("STM ");
-		break;
-	case 0xBF:
-		printf("SST ");
-		break;
-	case 0x89:
-	case 0xB0:
-		printf("INTEL ");
-		break;
-	default:
-		printf ("Unknown Vendor ");
-		break;
-	}
-
-	switch ((flash->flash_id) & 0xffff) {
-	case (uint16_t)AMD_ID_LV800T:
-		printf ("AM29LV800T\n");
-		break;
-	case (uint16_t)AMD_ID_LV800B:
-		printf ("AM29LV800B\n");
-		break;
-	case (uint16_t)AMD_ID_LV160T:
-		printf ("AM29LV160T\n");
-		break;
-	case (uint16_t)AMD_ID_LV160B:
-		printf ("AM29LV160B\n");
-		break;
-	case (uint16_t)AMD_ID_LV320T:
-		printf ("AM29LV320T\n");
-		break;
-	case (uint16_t)AMD_ID_LV320B:
-		printf ("AM29LV320B\n");
-		break;
-	case (uint16_t)INTEL_ID_28F800C3T:
-		printf ("28F800C3T\n");
-		break;
-	case (uint16_t)INTEL_ID_28F800C3B:
-		printf ("28F800C3B\n");
-		break;
-	case (uint16_t)INTEL_ID_28F160C3T:
-		printf ("28F160C3T\n");
-		break;
-	case (uint16_t)INTEL_ID_28F160C3B:
-		printf ("28F160C3B\n");
-		break;
-	case (uint16_t)INTEL_ID_28F320C3T:
-		printf ("28F320C3T\n");
-		break;
-	case (uint16_t)INTEL_ID_28F320C3B:
-		printf ("28F320C3B\n");
-		break;
-	case (uint16_t)INTEL_ID_28F640C3T:
-		printf ("28F640C3T\n");
-		break;
-	case (uint16_t)INTEL_ID_28F640C3B:
-		printf ("28F640C3B\n");
-		break;
-	default:
-		printf ("Unknown Chip Type\n");
-		break;
-	}
-
-	if (flash->size >= (1 << 20)) {
-		printf ("  Size: %ld MB in %d Sectors\n",
-				flash->size >> 20, flash->sector_count);
-	} else {
-		printf ("  Size: %ld kB in %d Sectors\n",
-				flash->size >> 10, flash->sector_count);
-	}
-
-	printf ("  Sector Start Addresses:");
-	for (i = 0; i < flash->sector_count; ++i) {
-		/* Check if whole sector is erased*/
-		if (i != (flash->sector_count-1))
-			size = flash->start[i+1] - flash->start[i];
-		else
-			size = flash->start[0] + flash->size - flash->start[i];
-
-		erased = 1;
-		p = (volatile unsigned long *)flash->start[i];
-		size = size >> 2;        /* divide by 4 for longword access */
-		for (k=0; k<size; k++) {
-			if (*p++ != 0xffffffff) {
-				erased = 0;
-				break;
-			}
-		}
-
-		if ((i % 5) == 0)
-			printf ("\n   ");
-
-		printf (" %08lX%s%s",
-			flash->start[i],
-			erased ? " E" : "  ",
-			flash->protect[i] ? "RO " : "   ");
-	}
-	printf ("\n");
-}
diff --git a/board/etin/debris/phantom.c b/board/etin/debris/phantom.c
deleted file mode 100644
index 3d5aa14086..0000000000
--- a/board/etin/debris/phantom.c
+++ /dev/null
@@ -1,301 +0,0 @@
-/*
- * board/eva/phantom.c
- *
- * Phantom RTC device driver for EVA
- *
- * Author: Sangmoon Kim
- *         dogoil@etinsys.com
- *
- * Copyright 2002 Etinsys Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <rtc.h>
-
-#if defined(CONFIG_CMD_DATE)
-
-#define RTC_BASE (CONFIG_SYS_NVRAM_BASE_ADDR + 0x7fff8)
-
-#define RTC_YEAR                ( RTC_BASE + 7 )
-#define RTC_MONTH               ( RTC_BASE + 6 )
-#define RTC_DAY_OF_MONTH        ( RTC_BASE + 5 )
-#define RTC_DAY_OF_WEEK         ( RTC_BASE + 4 )
-#define RTC_HOURS               ( RTC_BASE + 3 )
-#define RTC_MINUTES             ( RTC_BASE + 2 )
-#define RTC_SECONDS             ( RTC_BASE + 1 )
-#define RTC_CENTURY             ( RTC_BASE + 0 )
-
-#define RTC_CONTROLA            RTC_CENTURY
-#define RTC_CONTROLB            RTC_SECONDS
-#define RTC_CONTROLC            RTC_DAY_OF_WEEK
-
-#define RTC_CA_WRITE            0x80
-#define RTC_CA_READ             0x40
-
-#define RTC_CB_OSC_DISABLE      0x80
-
-#define RTC_CC_BATTERY_FLAG     0x80
-#define RTC_CC_FREQ_TEST        0x40
-
-
-static int phantom_flag = -1;
-static int century_flag = -1;
-
-static uchar rtc_read(unsigned int addr)
-{
-	return *(volatile unsigned char *)(addr);
-}
-
-static void rtc_write(unsigned int addr, uchar val)
-{
-	*(volatile unsigned char *)(addr) = val;
-}
-
-static unsigned char phantom_rtc_sequence[] = {
-	0xc5, 0x3a, 0xa3, 0x5c, 0xc5, 0x3a, 0xa3, 0x5c
-};
-
-static unsigned char* phantom_rtc_read(int addr, unsigned char rtc[8])
-{
-	int i, j;
-	unsigned char v;
-	unsigned char save = rtc_read(addr);
-
-	for (j = 0; j < 8; j++) {
-		v = phantom_rtc_sequence[j];
-		for (i = 0; i < 8; i++) {
-			rtc_write(addr, v & 1);
-			v >>= 1;
-		}
-	}
-	for (j = 0; j < 8; j++) {
-		v = 0;
-		for (i = 0; i < 8; i++) {
-			if(rtc_read(addr) & 1)
-				v |= 1 << i;
-		}
-		rtc[j] = v;
-	}
-	rtc_write(addr, save);
-	return rtc;
-}
-
-static void phantom_rtc_write(int addr, unsigned char rtc[8])
-{
-	int i, j;
-	unsigned char v;
-	unsigned char save = rtc_read(addr);
-	for (j = 0; j < 8; j++) {
-		v = phantom_rtc_sequence[j];
-		for (i = 0; i < 8; i++) {
-			rtc_write(addr, v & 1);
-			v >>= 1;
-		}
-	}
-	for (j = 0; j < 8; j++) {
-		v = rtc[j];
-		for (i = 0; i < 8; i++) {
-			rtc_write(addr, v & 1);
-			v >>= 1;
-		}
-	}
-	rtc_write(addr, save);
-}
-
-static int get_phantom_flag(void)
-{
-	int i;
-	unsigned char rtc[8];
-
-	phantom_rtc_read(RTC_BASE, rtc);
-
-	for(i = 1; i < 8; i++) {
-		if (rtc[i] != rtc[0])
-			return 1;
-	}
-	return 0;
-}
-
-void rtc_reset(void)
-{
-	if (phantom_flag < 0)
-		phantom_flag = get_phantom_flag();
-
-	if (phantom_flag) {
-		unsigned char rtc[8];
-		phantom_rtc_read(RTC_BASE, rtc);
-		if(rtc[4] & 0x30) {
-			printf( "real-time-clock was stopped. Now starting...\n" );
-			rtc[4] &= 0x07;
-			phantom_rtc_write(RTC_BASE, rtc);
-		}
-	} else {
-		uchar reg_a, reg_b, reg_c;
-		reg_a = rtc_read( RTC_CONTROLA );
-		reg_b = rtc_read( RTC_CONTROLB );
-
-		if ( reg_b & RTC_CB_OSC_DISABLE )
-		{
-			printf( "real-time-clock was stopped. Now starting...\n" );
-			reg_a |= RTC_CA_WRITE;
-			reg_b &= ~RTC_CB_OSC_DISABLE;
-			rtc_write( RTC_CONTROLA, reg_a );
-			rtc_write( RTC_CONTROLB, reg_b );
-		}
-
-		/* make sure read/write clock register bits are cleared */
-		reg_a &= ~( RTC_CA_WRITE | RTC_CA_READ );
-		rtc_write( RTC_CONTROLA, reg_a );
-
-		reg_c = rtc_read( RTC_CONTROLC );
-		if (( reg_c & RTC_CC_BATTERY_FLAG ) == 0 )
-			printf( "RTC battery low. Clock setting may not be reliable.\n");
-	}
-}
-
-static int get_century_flag(void)
-{
-	int flag = 0;
-	int bcd, century;
-	bcd = rtc_read( RTC_CENTURY );
-	century = bcd2bin( bcd & 0x3F );
-	rtc_write( RTC_CENTURY, bin2bcd(century+1));
-	if (bcd == rtc_read( RTC_CENTURY ))
-		flag = 1;
-	rtc_write( RTC_CENTURY, bcd);
-	return flag;
-}
-
-int rtc_get( struct rtc_time *tmp)
-{
-	if (phantom_flag < 0)
-		phantom_flag = get_phantom_flag();
-
-	if (phantom_flag)
-	{
-		unsigned char rtc[8];
-
-		phantom_rtc_read(RTC_BASE, rtc);
-
-		tmp->tm_sec	= bcd2bin(rtc[1] & 0x7f);
-		tmp->tm_min	= bcd2bin(rtc[2] & 0x7f);
-		tmp->tm_hour	= bcd2bin(rtc[3] & 0x1f);
-		tmp->tm_wday	= bcd2bin(rtc[4] & 0x7);
-		tmp->tm_mday	= bcd2bin(rtc[5] & 0x3f);
-		tmp->tm_mon	= bcd2bin(rtc[6] & 0x1f);
-		tmp->tm_year	= bcd2bin(rtc[7]) + 1900;
-		tmp->tm_yday = 0;
-		tmp->tm_isdst = 0;
-
-		if( (rtc[3] & 0x80)  && (rtc[3] & 0x40) ) tmp->tm_hour += 12;
-		if (tmp->tm_year < 1970) tmp->tm_year += 100;
-	} else {
-		uchar sec, min, hour;
-		uchar mday, wday, mon, year;
-
-		int century;
-
-		uchar reg_a;
-
-		if (century_flag < 0)
-			century_flag = get_century_flag();
-
-		reg_a = rtc_read( RTC_CONTROLA );
-		/* lock clock registers for read */
-		rtc_write( RTC_CONTROLA, ( reg_a | RTC_CA_READ ));
-
-		sec     = rtc_read( RTC_SECONDS );
-		min     = rtc_read( RTC_MINUTES );
-		hour    = rtc_read( RTC_HOURS );
-		mday    = rtc_read( RTC_DAY_OF_MONTH );
-		wday    = rtc_read( RTC_DAY_OF_WEEK );
-		mon     = rtc_read( RTC_MONTH );
-		year    = rtc_read( RTC_YEAR );
-		century = rtc_read( RTC_CENTURY );
-
-		/* unlock clock registers after read */
-		rtc_write( RTC_CONTROLA, ( reg_a & ~RTC_CA_READ ));
-
-		tmp->tm_sec  = bcd2bin( sec  & 0x7F );
-		tmp->tm_min  = bcd2bin( min  & 0x7F );
-		tmp->tm_hour = bcd2bin( hour & 0x3F );
-		tmp->tm_mday = bcd2bin( mday & 0x3F );
-		tmp->tm_mon  = bcd2bin( mon & 0x1F );
-		tmp->tm_wday = bcd2bin( wday & 0x07 );
-
-		if (century_flag) {
-			tmp->tm_year = bcd2bin( year ) +
-				( bcd2bin( century & 0x3F ) * 100 );
-		} else {
-			tmp->tm_year = bcd2bin( year ) + 1900;
-			if (tmp->tm_year < 1970) tmp->tm_year += 100;
-		}
-
-		tmp->tm_yday = 0;
-		tmp->tm_isdst= 0;
-	}
-
-	return 0;
-}
-
-int rtc_set( struct rtc_time *tmp )
-{
-	if (phantom_flag < 0)
-		phantom_flag = get_phantom_flag();
-
-	if (phantom_flag) {
-		uint year;
-		unsigned char rtc[8];
-
-		year = tmp->tm_year;
-		year -= (year < 2000) ? 1900 : 2000;
-
-		rtc[0] = bin2bcd(0);
-		rtc[1] = bin2bcd(tmp->tm_sec);
-		rtc[2] = bin2bcd(tmp->tm_min);
-		rtc[3] = bin2bcd(tmp->tm_hour);
-		rtc[4] = bin2bcd(tmp->tm_wday);
-		rtc[5] = bin2bcd(tmp->tm_mday);
-		rtc[6] = bin2bcd(tmp->tm_mon);
-		rtc[7] = bin2bcd(year);
-
-		phantom_rtc_write(RTC_BASE, rtc);
-	} else {
-		uchar reg_a;
-		if (century_flag < 0)
-			century_flag = get_century_flag();
-
-		/* lock clock registers for write */
-		reg_a = rtc_read( RTC_CONTROLA );
-		rtc_write( RTC_CONTROLA, ( reg_a | RTC_CA_WRITE ));
-
-		rtc_write( RTC_MONTH, bin2bcd( tmp->tm_mon ));
-
-		rtc_write( RTC_DAY_OF_WEEK, bin2bcd( tmp->tm_wday ));
-		rtc_write( RTC_DAY_OF_MONTH, bin2bcd( tmp->tm_mday ));
-		rtc_write( RTC_HOURS, bin2bcd( tmp->tm_hour ));
-		rtc_write( RTC_MINUTES, bin2bcd( tmp->tm_min ));
-		rtc_write( RTC_SECONDS, bin2bcd( tmp->tm_sec ));
-
-		/* break year up into century and year in century */
-		if (century_flag) {
-			rtc_write( RTC_YEAR, bin2bcd( tmp->tm_year % 100 ));
-			rtc_write( RTC_CENTURY, bin2bcd( tmp->tm_year / 100 ));
-			reg_a &= 0xc0;
-			reg_a |= bin2bcd( tmp->tm_year / 100 );
-		} else {
-			rtc_write(RTC_YEAR, bin2bcd(tmp->tm_year -
-				((tmp->tm_year < 2000) ? 1900 : 2000)));
-		}
-
-		/* unlock clock registers after read */
-		rtc_write( RTC_CONTROLA, ( reg_a  & ~RTC_CA_WRITE ));
-	}
-
-	return 0;
-}
-
-#endif
diff --git a/board/etin/kvme080/Makefile b/board/etin/kvme080/Makefile
deleted file mode 100644
index d1b6f30440..0000000000
--- a/board/etin/kvme080/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	= kvme080.o multiverse.o
diff --git a/board/etin/kvme080/kvme080.c b/board/etin/kvme080/kvme080.c
deleted file mode 100644
index baf4cbc4da..0000000000
--- a/board/etin/kvme080/kvme080.c
+++ /dev/null
@@ -1,184 +0,0 @@
-/*
- * (C) Copyright 2005
- * Sangmoon Kim, Etin Systems. dogoil@etinsys.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc824x.h>
-#include <pci.h>
-#include <i2c.h>
-#include <netdev.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-
-int checkboard(void)
-{
-	puts ("Board: KVME080\n");
-	return 0;
-}
-
-unsigned long setdram(int m, int row, int col, int bank)
-{
-	int i;
-	unsigned long start, end;
-	uint32_t mccr1;
-	uint32_t mear1 = 0, emear1 = 0, msar1 = 0, emsar1 = 0;
-	uint32_t mear2 = 0, emear2 = 0, msar2 = 0, emsar2 = 0;
-	uint8_t mber = 0;
-
-	CONFIG_READ_WORD(MCCR1, mccr1);
-	mccr1 &= 0xffff0000;
-
-	start = CONFIG_SYS_SDRAM_BASE;
-	end = start + (1 << (col + row + 3) ) * bank - 1;
-
-	for (i = 0; i < m; i++) {
-		mccr1 |= ((row == 13)? 2 : (bank == 4)? 0 : 3) << i * 2;
-		if (i < 4) {
-			msar1  |= ((start >> 20) & 0xff) << i * 8;
-			emsar1 |= ((start >> 28) & 0xff) << i * 8;
-			mear1  |= ((end >> 20) & 0xff) << i * 8;
-			emear1 |= ((end >> 28) & 0xff) << i * 8;
-		} else {
-			msar2  |= ((start >> 20) & 0xff) << (i-4) * 8;
-			emsar2 |= ((start >> 28) & 0xff) << (i-4) * 8;
-			mear2  |= ((end >> 20) & 0xff) << (i-4) * 8;
-			emear2 |= ((end >> 28) & 0xff) << (i-4) * 8;
-		}
-		mber |= 1 << i;
-		start += (1 << (col + row + 3) ) * bank;
-		end += (1 << (col + row + 3) ) * bank;
-	}
-	for (; i < 8; i++) {
-		if (i < 4) {
-			msar1  |= 0xff << i * 8;
-			emsar1 |= 0x30 << i * 8;
-			mear1  |= 0xff << i * 8;
-			emear1 |= 0x30 << i * 8;
-		} else {
-			msar2  |= 0xff << (i-4) * 8;
-			emsar2 |= 0x30 << (i-4) * 8;
-			mear2  |= 0xff << (i-4) * 8;
-			emear2 |= 0x30 << (i-4) * 8;
-		}
-	}
-
-	CONFIG_WRITE_WORD(MCCR1, mccr1);
-	CONFIG_WRITE_WORD(MSAR1, msar1);
-	CONFIG_WRITE_WORD(EMSAR1, emsar1);
-	CONFIG_WRITE_WORD(MEAR1, mear1);
-	CONFIG_WRITE_WORD(EMEAR1, emear1);
-	CONFIG_WRITE_WORD(MSAR2, msar2);
-	CONFIG_WRITE_WORD(EMSAR2, emsar2);
-	CONFIG_WRITE_WORD(MEAR2, mear2);
-	CONFIG_WRITE_WORD(EMEAR2, emear2);
-	CONFIG_WRITE_BYTE(MBER, mber);
-
-	return (1 << (col + row + 3) ) * bank * m;
-}
-
-phys_size_t initdram(int board_type)
-{
-	unsigned int msr;
-	long int size = 0;
-
-	msr = mfmsr();
-	mtmsr(msr & ~(MSR_IR | MSR_DR));
-	mtspr(IBAT2L, CONFIG_SYS_IBAT0L + 0x10000000);
-	mtspr(IBAT2U, CONFIG_SYS_IBAT0U + 0x10000000);
-	mtspr(DBAT2L, CONFIG_SYS_DBAT0L + 0x10000000);
-	mtspr(DBAT2U, CONFIG_SYS_DBAT0U + 0x10000000);
-	mtmsr(msr);
-
-	if (setdram(2,13,10,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x20000000))
-		size = 0x20000000;	/* 512MB */
-	else if (setdram(1,13,10,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x10000000))
-		size = 0x10000000;	/* 256MB */
-	else if (setdram(2,13,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x10000000))
-		size = 0x10000000;	/* 256MB */
-	else if (setdram(1,13,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x08000000))
-		size = 0x08000000;	/* 128MB */
-	else if (setdram(2,12,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x08000000))
-		size = 0x08000000;	/* 128MB */
-	else if (setdram(1,12,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x04000000))
-		size = 0x04000000;	/* 64MB */
-
-	msr = mfmsr();
-	mtmsr(msr & ~(MSR_IR | MSR_DR));
-	mtspr(IBAT2L, CONFIG_SYS_IBAT2L);
-	mtspr(IBAT2U, CONFIG_SYS_IBAT2U);
-	mtspr(DBAT2L, CONFIG_SYS_DBAT2L);
-	mtspr(DBAT2U, CONFIG_SYS_DBAT2U);
-	mtmsr(msr);
-
-	return size;
-}
-
-struct pci_controller hose;
-
-void pci_init_board(void)
-{
-	pci_mpc824x_init(&hose);
-}
-
-int board_early_init_f(void)
-{
-	*(volatile unsigned char *)(0xff080120) = 0xfb;
-
-	return 0;
-}
-
-int board_early_init_r(void)
-{
-	unsigned int msr;
-
-	CONFIG_WRITE_WORD(ERCR1, 0x95ff8000);
-	CONFIG_WRITE_WORD(ERCR3, 0x0c00000e);
-	CONFIG_WRITE_WORD(ERCR4, 0x0800000e);
-
-	msr = mfmsr();
-	mtmsr(msr & ~(MSR_IR | MSR_DR));
-	mtspr(IBAT1L, 0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT);
-	mtspr(IBAT1U, 0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP);
-	mtspr(DBAT1L, 0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT);
-	mtspr(DBAT1U, 0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP);
-	mtmsr(msr);
-
-	return 0;
-}
-
-extern int multiverse_init(void);
-
-int misc_init_r(void)
-{
-	multiverse_init();
-	return 0;
-}
-
-void *nvram_read(void *dest, const long src, size_t count)
-{
-	volatile uchar *d = (volatile uchar*) dest;
-	volatile uchar *s = (volatile uchar*) src;
-	while(count--) {
-		*d++ = *s++;
-		asm volatile("sync");
-	}
-	return dest;
-}
-
-void nvram_write(long dest, const void *src, size_t count)
-{
-	volatile uchar *d = (volatile uchar*)dest;
-	volatile uchar *s = (volatile uchar*)src;
-	while(count--) {
-		*d++ = *s++;
-		asm volatile("sync");
-	}
-}
-
-int board_eth_init(bd_t *bis)
-{
-	return pci_eth_init(bis);
-}
diff --git a/board/etin/kvme080/multiverse.c b/board/etin/kvme080/multiverse.c
deleted file mode 100644
index 2bcfe2ea04..0000000000
--- a/board/etin/kvme080/multiverse.c
+++ /dev/null
@@ -1,184 +0,0 @@
-/*
- * multiverse.c
- *
- * VME driver for Multiverse
- *
- * Author : Sangmoon Kim
- *	    dogoil@etinsys.com
- *
- * Copyright 2005 ETIN SYSTEMS Co.,Ltd.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <pci.h>
-#include <linux/compiler.h>
-
-#include "multiverse.h"
-
-static unsigned long vme_asi_addr;
-static unsigned long vme_iack_addr;
-static unsigned long pci_reg_addr;
-static unsigned long vme_reg_addr;
-
-int multiv_reset(unsigned long base)
-{
-	writeb(0x09, base + VME_SLAVE32_AM);
-	writeb(0x39, base + VME_SLAVE24_AM);
-	writeb(0x29, base + VME_SLAVE16_AM);
-	writeb(0x2f, base + VME_SLAVE_REG_AM);
-	writeb((VME_A32_SLV_BUS >> 24) & 0xff, base + VME_SLAVE32_A);
-	writeb((VME_A24_SLV_BUS >> 16) & 0xff, base + VME_SLAVE24_A);
-	writeb((VME_A16_SLV_BUS >> 8 ) & 0xff, base + VME_SLAVE16_A);
-#ifdef A32_SLV_WINDOW
-	if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
-		writeb(((~(VME_A32_SLV_SIZE-1)) >> 24) & 0xff,
-				base + VME_SLAVE32_MASK);
-		writeb(0x01, base + VME_SLAVE32_EN);
-	} else {
-		writeb(0xff, base + VME_SLAVE32_MASK);
-		writeb(0x00, base + VME_SLAVE32_EN);
-	}
-#else
-	writeb(0xff, base + VME_SLAVE32_MASK);
-	writeb(0x00, base + VME_SLAVE32_EN);
-#endif
-#ifdef A24_SLV_WINDOW
-	if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
-		writeb(((~(VME_A24_SLV_SIZE-1)) >> 16) & 0xff,
-				base + VME_SLAVE24_MASK);
-		writeb(0x01, base + VME_SLAVE24_EN);
-	} else {
-		writeb(0xff, base + VME_SLAVE24_MASK);
-		writeb(0x00, base + VME_SLAVE24_EN);
-	}
-#else
-	writeb(0xff, base + VME_SLAVE24_MASK);
-	writeb(0x00, base + VME_SLAVE24_EN);
-#endif
-#ifdef A16_SLV_WINDOW
-	if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
-		writeb(((~(VME_A16_SLV_SIZE-1)) >> 8) & 0xff,
-				base + VME_SLAVE16_MASK);
-		writeb(0x01, base + VME_SLAVE16_EN);
-	} else {
-		writeb(0xff, base + VME_SLAVE16_MASK);
-		writeb(0x00, base + VME_SLAVE16_EN);
-	}
-#else
-	writeb(0xff, base + VME_SLAVE16_MASK);
-	writeb(0x00, base + VME_SLAVE16_EN);
-#endif
-#ifdef REG_SLV_WINDOW
-	if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
-		writeb(((~(VME_REG_SLV_SIZE-1)) >> 16) & 0xff,
-				base + VME_SLAVE_REG_MASK);
-		writeb(0x01, base + VME_SLAVE_REG_EN);
-	} else {
-		writeb(0xf8, base + VME_SLAVE_REG_MASK);
-	}
-#else
-	writeb(0xf8, base + VME_SLAVE_REG_MASK);
-#endif
-	writeb(0x09, base + VME_MASTER32_AM);
-	writeb(0x39, base + VME_MASTER24_AM);
-	writeb(0x29, base + VME_MASTER16_AM);
-	writeb(0x2f, base + VME_MASTER_REG_AM);
-	writel(0x00000000, base + VME_RMW_ADRS);
-	writeb(0x00, base + VME_IRQ);
-	writeb(0x00, base + VME_INT_EN);
-	writel(0x00000000, base + VME_IRQ1_REG);
-	writel(0x00000000, base + VME_IRQ2_REG);
-	writel(0x00000000, base + VME_IRQ3_REG);
-	writel(0x00000000, base + VME_IRQ4_REG);
-	writel(0x00000000, base + VME_IRQ5_REG);
-	writel(0x00000000, base + VME_IRQ6_REG);
-	writel(0x00000000, base + VME_IRQ7_REG);
-	return 0;
-}
-
-void multiv_auto_slot_id(unsigned long base)
-{
-	__maybe_unused unsigned int vector;
-	int slot_id = 1;
-	if (readb(base + VME_CTRL) & VME_CTRL_SYSFAIL) {
-		*(volatile unsigned int*)(base + VME_IRQ2_REG) = 0xfe;
-		writeb(readb(base + VME_IRQ) | 0x04, base + VME_IRQ);
-		writeb(readb(base + VME_CTRL) & ~VME_CTRL_SYSFAIL,
-				base + VME_CTRL);
-		while (readb(base + VME_STATUS) & VME_STATUS_SYSFAIL);
-		if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
-			while (readb(base + VME_INT) & 0x04) {
-				vector = *(volatile unsigned int*)
-					(vme_iack_addr + VME_IACK2);
-				*(unsigned char*)(vme_asi_addr + 0x7ffff)
-					= (slot_id << 3) & 0xff;
-				slot_id ++;
-				if (slot_id > 31)
-					break;
-			}
-		}
-	}
-}
-
-int multiverse_init(void)
-{
-	int i;
-	pci_dev_t pdev;
-	unsigned int bar[6];
-
-	pdev = pci_find_device(0x1895, 0x0001, 0);
-
-	if (pdev == 0)
-		return -1;
-
-	for (i = 0; i < 6; i++)
-		pci_read_config_dword (pdev,
-				PCI_BASE_ADDRESS_0 + i * 4, &bar[i]);
-
-	pci_reg_addr = bar[0];
-	vme_reg_addr = bar[1] + 0x00F00000;
-	vme_iack_addr = bar[1] + 0x00200000;
-	vme_asi_addr = bar[3];
-
-	pci_write_config_dword (pdev, PCI_COMMAND,
-		PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
-
-	writel(0xFF000000, pci_reg_addr + P_TA1);
-	writel(0x04, pci_reg_addr + P_IMG_CTRL1);
-	writel(0xf0000000, pci_reg_addr + P_TA2);
-	writel(0x04, pci_reg_addr + P_IMG_CTRL2);
-	writel(0xF1000000, pci_reg_addr + P_TA3);
-	writel(0x04, pci_reg_addr + P_IMG_CTRL3);
-	writel(VME_A32_MSTR_BUS, pci_reg_addr + P_TA5);
-	writel(~(VME_A32_MSTR_SIZE-1), pci_reg_addr + P_AM5);
-	writel(0x04, pci_reg_addr + P_IMG_CTRL5);
-
-	writel(VME_A32_SLV_BUS, pci_reg_addr + W_BA1);
-	writel(~(VME_A32_SLV_SIZE-1), pci_reg_addr + W_AM1);
-	writel(VME_A32_SLV_LOCAL, pci_reg_addr + W_TA1);
-	writel(0x04, pci_reg_addr + W_IMG_CTRL1);
-
-	writel(0xF0000000, pci_reg_addr + W_BA2);
-	writel(0xFF000000, pci_reg_addr + W_AM2);
-	writel(VME_A24_SLV_LOCAL, pci_reg_addr + W_TA2);
-	writel(0x04, pci_reg_addr + W_IMG_CTRL2);
-
-	writel(0xFF000000, pci_reg_addr + W_BA3);
-	writel(0xFF000000, pci_reg_addr + W_AM3);
-	writel(VME_A16_SLV_LOCAL, pci_reg_addr + W_TA3);
-	writel(0x04, pci_reg_addr + W_IMG_CTRL3);
-
-	writel(0x00000001, pci_reg_addr + W_ERR_CS);
-	writel(0x00000001, pci_reg_addr + P_ERR_CS);
-
-	multiv_reset(vme_reg_addr);
-	writeb(readb(vme_reg_addr + VME_CTRL) | VME_CTRL_SHORT_D,
-		vme_reg_addr + VME_CTRL);
-
-	multiv_auto_slot_id(vme_reg_addr);
-
-	return 0;
-}
diff --git a/board/etin/kvme080/multiverse.h b/board/etin/kvme080/multiverse.h
deleted file mode 100644
index b3b79b7ee3..0000000000
--- a/board/etin/kvme080/multiverse.h
+++ /dev/null
@@ -1,173 +0,0 @@
-/*
- * multiverse.h
- *
- * VME driver for Multiverse
- *
- * Author : Sangmoon Kim
- *	    dogoil@etinsys.com
- *
- * Copyright 2005 ETIN SYSTEMS Co.,Ltd.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __MULTIVERSE_H__
-#define __MULTIVERSE_H__
-
-#define VME_A32_MSTR_BUS	0x90000000
-#define VME_A32_MSTR_SIZE	0x01000000
-
-#define VME_A32_SLV_SIZE	0x01000000
-
-#define VME_A32_SLV_BUS		0x90000000
-#define VME_A24_SLV_BUS		0x00000000
-#define VME_A16_SLV_BUS		0x00000000
-
-#define VME_A32_SLV_LOCAL	0x00000000
-#define VME_A24_SLV_LOCAL	0x00000000
-#define VME_A16_SLV_LOCAL	0x00000000
-
-#define A32_SLV_WINDOW
-#undef	A24_SLV_WINDOW
-#undef	A16_SLV_WINDOW
-#undef	REG_SLV_WINDOW
-
-/* PCI Registers */
-
-#define P_IMG_CTRL0		0x100
-#define P_BA0			0x104
-#define P_AM0			0x108
-#define P_TA0			0x10C
-#define P_IMG_CTRL1		0x110
-#define P_BA1			0x114
-#define P_AM1			0x118
-#define P_TA1			0x11C
-#define P_IMG_CTRL2		0x120
-#define P_BA2			0x124
-#define P_AM2			0x128
-#define P_TA2			0x12C
-#define P_IMG_CTRL3		0x130
-#define P_BA3			0x134
-#define P_AM3			0x138
-#define P_TA3			0x13C
-#define P_IMG_CTRL4		0x140
-#define P_BA4			0x144
-#define P_AM4			0x148
-#define P_TA4			0x14C
-#define P_IMG_CTRL5		0x150
-#define P_BA5			0x154
-#define P_AM5			0x158
-#define P_TA5			0x15C
-#define P_ERR_CS		0x160
-#define P_ERR_ADDR		0x164
-#define P_ERR_DATA		0x168
-
-#define WB_CONF_SPC_BAR		0x180
-#define W_IMG_CTRL1		0x184
-#define W_BA1			0x188
-#define W_AM1			0x18C
-#define W_TA1			0x190
-#define W_IMG_CTRL2		0x194
-#define W_BA2			0x198
-#define W_AM2			0x19C
-#define W_TA2			0x1A0
-#define W_IMG_CTRL3		0x1A4
-#define W_BA3			0x1A8
-#define W_AM3			0x1AC
-#define W_TA3			0x1B0
-#define W_IMG_CTRL4		0x1B4
-#define W_BA4			0x1B8
-#define W_AM4			0x1BC
-#define W_TA4			0x1C0
-#define W_IMG_CTRL5		0x1C4
-#define W_BA5			0x1C8
-#define W_AM5			0x1CC
-#define W_TA5			0x1D0
-#define W_ERR_CS		0x1D4
-#define W_ERR_ADDR		0x1D8
-#define W_ERR_DATA		0x1DC
-#define CNF_ADDR		0x1E0
-#define CNF_DATA		0x1E4
-#define INT_ACK			0x1E8
-#define ICR			0x1EC
-#define ISR			0x1F0
-
-/* VME registers */
-
-#define VME_SLAVE32_AM		0x03
-#define VME_SLAVE24_AM		0x02
-#define VME_SLAVE16_AM		0x01
-#define VME_SLAVE_REG_AM	0x00
-#define VME_SLAVE32_A		0x07
-#define VME_SLAVE24_A		0x06
-#define VME_SLAVE16_A		0x05
-#define VME_SLAVE_REG_A		0x04
-#define VME_SLAVE32_MASK	0x0B
-#define VME_SLAVE24_MASK	0x0A
-#define VME_SLAVE16_MASK	0x09
-#define VME_SLAVE_REG_MASK	0x08
-#define VME_SLAVE32_EN		0x0F
-#define VME_SLAVE24_EN		0x0E
-#define VME_SLAVE16_EN		0x0D
-#define VME_SLAVE_REG_EN	0x0C
-#define VME_MASTER32_AM		0x13
-#define VME_MASTER24_AM		0x12
-#define VME_MASTER16_AM		0x11
-#define VME_MASTER_REG_AM	0x10
-#define VME_RMW_ADRS		0x14
-#define VME_MBOX		0x18
-#define VME_STATUS		0x1E
-#define VME_CTRL		0x1C
-#define VME_IRQ			0x20
-#define VME_INT_EN		0x21
-#define VME_INT			0x22
-#define VME_IRQ1_REG		0x24
-#define VME_IRQ2_REG		0x28
-#define VME_IRQ3_REG		0x2C
-#define VME_IRQ4_REG		0x30
-#define VME_IRQ5_REG		0x34
-#define VME_IRQ6_REG		0x38
-#define VME_IRQ7_REG		0x3C
-
-/* VME control register */
-
-#define VME_CTRL_BRDRST		0x01
-#define VME_CTRL_SYSRST		0x02
-#define VME_CTRL_RMW		0x04
-#define VME_CTRL_SHORT_D	0x08
-#define VME_CTRL_SYSFAIL	0x10
-#define VME_CTRL_VOWN		0x20
-#define VME_CTRL_A16_REG_MODE	0x40
-
-/* VME status register */
-
-#define VME_STATUS_SYSCON	0x01
-#define VME_STATUS_SYSFAIL	0x02
-#define VME_STATUS_ACFAIL	0x04
-#define VME_STATUS_SYSRST	0x08
-#define VME_STATUS_VOWN		0x10
-
-/* Interrupt types */
-
-#define LVL1			0x0002
-#define LVL2			0x0004
-#define LVL3			0x0008
-#define LVL4			0x0010
-#define LVL5			0x0020
-#define LVL6			0x0040
-#define LVL7			0x0080
-#define MULTIVERSE_INTI_INT	0x0100
-#define MULTIVERSE_WB_INT	0x0200
-#define MULTIVERSE_PCI_INT	0x0400
-
-/* interrupt acknowledge */
-
-#define VME_IACK1		0x04
-#define VME_IACK2		0x08
-#define VME_IACK3		0x0c
-#define VME_IACK4		0x10
-#define VME_IACK5		0x14
-#define VME_IACK6		0x18
-#define VME_IACK7		0x1c
-
-#endif /* __MULTIVERSE_H__ */
diff --git a/board/freescale/b4860qds/b4860qds.c b/board/freescale/b4860qds/b4860qds.c
index b2d5378143..9d6b9a7b66 100644
--- a/board/freescale/b4860qds/b4860qds.c
+++ b/board/freescale/b4860qds/b4860qds.c
@@ -488,6 +488,9 @@ int configure_vsc3316_3308(void)
 	}
 
 	switch (serdes2_prtcl) {
+#ifdef CONFIG_PPC_B4420
+	case 0x9d:
+#endif
 	case 0x9E:
 	case 0x9A:
 	case 0x98:
@@ -852,6 +855,9 @@ int config_serdes2_refclks(void)
 	 * For this SerDes2's Refclk1 need to be set to 100MHz
 	 */
 	switch (serdes2_prtcl) {
+#ifdef CONFIG_PPC_B4420
+	case 0x9d:
+#endif
 	case 0x9E:
 	case 0x9A:
 	case 0xb2:
diff --git a/board/freescale/m5253demo/flash.c b/board/freescale/m5253demo/flash.c
index 387e454cef..16bba59ba8 100644
--- a/board/freescale/m5253demo/flash.c
+++ b/board/freescale/m5253demo/flash.c
@@ -177,7 +177,7 @@ int flash_erase(flash_info_t * info, int s_first, int s_last)
 {
 	FPWV *addr;
 	int flag, prot, sect, count;
-	ulong type, start, last;
+	ulong type, start;
 	int rcode = 0, flashtype = 0;
 
 	if ((s_first < 0) || (s_first > s_last)) {
@@ -217,7 +217,6 @@ int flash_erase(flash_info_t * info, int s_first, int s_last)
 	flag = disable_interrupts();
 
 	start = get_timer(0);
-	last = start;
 
 	if ((s_last - s_first) == (CONFIG_SYS_SST_SECT - 1)) {
 		if (prot == 0) {
@@ -319,14 +318,13 @@ int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
 {
 	ulong wp, count;
 	u16 data;
-	int rc, port_width;
+	int rc;
 
 	if (info->flash_id == FLASH_UNKNOWN)
 		return 4;
 
 	/* get lower word aligned address */
 	wp = addr;
-	port_width = sizeof(FPW);
 
 	/* handle unaligned start bytes */
 	if (wp & 1) {
diff --git a/board/freescale/mpc8260ads/Makefile b/board/freescale/mpc8260ads/Makefile
deleted file mode 100644
index 007d9580ae..0000000000
--- a/board/freescale/mpc8260ads/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= mpc8260ads.o flash.o
diff --git a/board/freescale/mpc8260ads/flash.c b/board/freescale/mpc8260ads/flash.c
deleted file mode 100644
index 4012d45868..0000000000
--- a/board/freescale/mpc8260ads/flash.c
+++ /dev/null
@@ -1,476 +0,0 @@
-/*
- * (C) Copyright 2000, 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
- * Add support the Sharp chips on the mpc8260ads.
- * I started with board/ip860/flash.c and made changes I found in
- * the MTD project by David Schleef.
- *
- * (C) Copyright 2003 Arabella Software Ltd.
- * Yuli Barcohen <yuli@arabellasw.com>
- * Re-written to support multi-bank flash SIMMs.
- * Added support for real protection and JFFS2.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-
-/* Intel-compatible flash ID */
-#define INTEL_COMPAT  0x89898989
-#define INTEL_ALT     0xB0B0B0B0
-
-/* Intel-compatible flash commands */
-#define INTEL_PROGRAM 0x10101010
-#define INTEL_ERASE   0x20202020
-#define INTEL_CLEAR   0x50505050
-#define INTEL_LOCKBIT 0x60606060
-#define INTEL_PROTECT 0x01010101
-#define INTEL_STATUS  0x70707070
-#define INTEL_READID  0x90909090
-#define INTEL_CONFIRM 0xD0D0D0D0
-#define INTEL_RESET   0xFFFFFFFF
-
-/* Intel-compatible flash status bits */
-#define INTEL_FINISHED 0x80808080
-#define INTEL_OK       0x80808080
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/*-----------------------------------------------------------------------
- * This board supports 32-bit wide flash SIMMs (4x8-bit configuration.)
- * Up to 32MB of flash supported (up to 4 banks.)
- * BCSR is used for flash presence detect (page 4-65 of the User's Manual)
- *
- * The following code can not run from flash!
- */
-unsigned long flash_init (void)
-{
-	ulong size = 0, sect_start, sect_size = 0, bank_size;
-	ushort sect_count = 0;
-	int i, j, nbanks;
-	vu_long *addr = (vu_long *)CONFIG_SYS_FLASH_BASE;
-	vu_long *bcsr = (vu_long *)CONFIG_SYS_BCSR;
-
-	switch (bcsr[2] & 0xF) {
-	case 0:
-		nbanks = 4;
-		break;
-	case 1:
-		nbanks = 2;
-		break;
-	case 2:
-		nbanks = 1;
-		break;
-	default:		/* Unsupported configurations */
-		nbanks = CONFIG_SYS_MAX_FLASH_BANKS;
-	}
-
-	if (nbanks > CONFIG_SYS_MAX_FLASH_BANKS)
-		nbanks = CONFIG_SYS_MAX_FLASH_BANKS;
-
-	for (i = 0; i < nbanks; i++) {
-		*addr = INTEL_READID;	/* Read Intelligent Identifier */
-		if ((addr[0] == INTEL_COMPAT) || (addr[0] == INTEL_ALT)) {
-			switch (addr[1]) {
-			case SHARP_ID_28F016SCL:
-			case SHARP_ID_28F016SCZ:
-				flash_info[i].flash_id = FLASH_MAN_SHARP | FLASH_LH28F016SCT;
-				sect_count = 32;
-				sect_size = 0x40000;
-				break;
-			default:
-				flash_info[i].flash_id = FLASH_UNKNOWN;
-				sect_count = CONFIG_SYS_MAX_FLASH_SECT;
-				sect_size =
-				   CONFIG_SYS_FLASH_SIZE / CONFIG_SYS_MAX_FLASH_BANKS / CONFIG_SYS_MAX_FLASH_SECT;
-			}
-		}
-		else
-			flash_info[i].flash_id = FLASH_UNKNOWN;
-		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
-			printf("### Unknown flash ID %08lX %08lX at address %08lX ###\n",
-			       addr[0], addr[1], (ulong)addr);
-			size = 0;
-			*addr = INTEL_RESET; /* Reset bank to Read Array mode */
-			break;
-		}
-		flash_info[i].sector_count = sect_count;
-		flash_info[i].size = bank_size = sect_size * sect_count;
-		size += bank_size;
-		sect_start = (ulong)addr;
-		for (j = 0; j < sect_count; j++) {
-			addr = (vu_long *)sect_start;
-			flash_info[i].start[j]   = sect_start;
-			flash_info[i].protect[j] = (addr[2] == 0x01010101);
-			sect_start += sect_size;
-		}
-		*addr = INTEL_RESET; /* Reset bank to Read Array mode */
-		addr = (vu_long *)sect_start;
-	}
-
-	if (size == 0) {	/* Unknown flash, fill with hard-coded values */
-		sect_start = CONFIG_SYS_FLASH_BASE;
-		for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
-			flash_info[i].flash_id = FLASH_UNKNOWN;
-			flash_info[i].size = CONFIG_SYS_FLASH_SIZE / CONFIG_SYS_MAX_FLASH_BANKS;
-			flash_info[i].sector_count = sect_count;
-			for (j = 0; j < sect_count; j++) {
-				flash_info[i].start[j]   = sect_start;
-				flash_info[i].protect[j] = 0;
-				sect_start += sect_size;
-			}
-		}
-		size = CONFIG_SYS_FLASH_SIZE;
-	}
-	else
-		for (i = nbanks; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
-			flash_info[i].flash_id = FLASH_UNKNOWN;
-			flash_info[i].size = 0;
-			flash_info[i].sector_count = 0;
-		}
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
-	/* monitor protection ON by default */
-	flash_protect(FLAG_PROTECT_SET,
-		      CONFIG_SYS_MONITOR_BASE,
-		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
-		      &flash_info[0]);
-#endif
-
-#ifdef	CONFIG_ENV_IS_IN_FLASH
-	/* ENV protection ON by default */
-	flash_protect(FLAG_PROTECT_SET,
-		      CONFIG_ENV_ADDR,
-		      CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1,
-		      &flash_info[0]);
-#endif
-	return (size);
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info  (flash_info_t *info)
-{
-	int i;
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf ("missing or unknown FLASH type\n");
-		return;
-	}
-
-	switch (info->flash_id & FLASH_VENDMASK) {
-	case FLASH_MAN_INTEL:	printf ("Intel ");		break;
-	case FLASH_MAN_SHARP:   printf ("Sharp ");		break;
-	default:		printf ("Unknown Vendor ");	break;
-	}
-
-	switch (info->flash_id & FLASH_TYPEMASK) {
-	case FLASH_28F016SV:	printf ("28F016SV (16 Mbit, 32 x 64k)\n");
-				break;
-	case FLASH_28F160S3:	printf ("28F160S3 (16 Mbit, 32 x 512K)\n");
-				break;
-	case FLASH_28F320S3:	printf ("28F320S3 (32 Mbit, 64 x 512K)\n");
-				break;
-	case FLASH_LH28F016SCT: printf ("28F016SC (16 Mbit, 32 x 64K)\n");
-				break;
-	default:		printf ("Unknown Chip Type\n");
-				break;
-	}
-
-	printf ("  Size: %ld MB in %d Sectors\n",
-		info->size >> 20, info->sector_count);
-
-	printf ("  Sector Start Addresses:");
-	for (i=0; i<info->sector_count; ++i) {
-		if ((i % 5) == 0)
-			printf ("\n   ");
-		printf (" %08lX%s",
-			info->start[i],
-			info->protect[i] ? " (RO)" : "     "
-		);
-	}
-	printf ("\n");
-}
-
-/*-----------------------------------------------------------------------
- */
-int	flash_erase (flash_info_t *info, int s_first, int s_last)
-{
-	int flag, prot, sect;
-	ulong start, now, last;
-
-	if ((s_first < 0) || (s_first > s_last)) {
-		if (info->flash_id == FLASH_UNKNOWN) {
-			printf ("- missing\n");
-		} else {
-			printf ("- no sectors to erase\n");
-		}
-		return 1;
-	}
-
-	if (    ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL)
-	     && ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_SHARP) ) {
-		printf ("Can't erase unknown flash type %08lx - aborted\n",
-			info->flash_id);
-		return 1;
-	}
-
-	prot = 0;
-	for (sect=s_first; sect<=s_last; ++sect) {
-		if (info->protect[sect]) {
-			prot++;
-		}
-	}
-
-	if (prot) {
-		printf ("- Warning: %d protected sectors will not be erased!\n",
-			prot);
-	} else {
-		printf ("\n");
-	}
-
-	/* Start erase on unprotected sectors */
-	for (sect = s_first; sect<=s_last; sect++) {
-		if (info->protect[sect] == 0) {	/* not protected */
-			vu_long *addr = (vu_long *)(info->start[sect]);
-
-			last = start = get_timer (0);
-
-			/* Disable interrupts which might cause a timeout here */
-			flag = disable_interrupts();
-
-			/* Clear Status Register */
-			*addr = INTEL_CLEAR;
-			/* Single Block Erase Command */
-			*addr = INTEL_ERASE;
-			/* Confirm */
-			*addr = INTEL_CONFIRM;
-
-			if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) {
-			    /* Resume Command, as per errata update */
-			    *addr = INTEL_CONFIRM;
-			}
-
-			/* re-enable interrupts if necessary */
-			if (flag)
-				enable_interrupts();
-
-			while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
-				if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
-					printf ("Timeout\n");
-					*addr = INTEL_RESET;	/* reset bank */
-					return 1;
-				}
-				/* show that we're waiting */
-				if ((now - last) > 1000) {	/* every second */
-					putc ('.');
-					last = now;
-				}
-			}
-
-			if (*addr != INTEL_OK) {
-				printf("Block erase failed at %08X, CSR=%08X\n",
-				       (uint)addr, (uint)*addr);
-				*addr = INTEL_RESET;	/* reset bank */
-				return 1;
-			}
-
-			/* reset to read mode */
-			*addr = INTEL_RESET;
-		}
-	}
-
-	printf (" done\n");
-	return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t *info, ulong dest, ulong data)
-{
-	ulong start;
-	int rc = 0;
-	int flag;
-	vu_long *addr = (vu_long *)dest;
-
-	/* Check if Flash is (sufficiently) erased */
-	if ((*addr & data) != data) {
-		return (2);
-	}
-
-	*addr = INTEL_CLEAR; /* Clear status register */
-
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
-
-	/* Write Command */
-	*addr = INTEL_PROGRAM;
-
-	/* Write Data */
-	*addr = data;
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts();
-
-	/* data polling for D7 */
-	start = get_timer (0);
-	while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
-		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
-			printf("Write timed out\n");
-			rc = 1;
-			break;
-		}
-	}
-	if (*addr != INTEL_OK) {
-		printf ("Write failed at %08X, CSR=%08X\n", (uint)addr, (uint)*addr);
-		rc = 1;
-	}
-
-	*addr = INTEL_RESET; /* Reset to read array mode */
-
-	return rc;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
-	ulong cp, wp, data;
-	int i, l, rc;
-
-	wp = (addr & ~3);	/* get lower word aligned address */
-
-	*(vu_long *)wp = INTEL_RESET; /* Reset to read array mode */
-
-	/*
-	 * handle unaligned start bytes
-	 */
-	if ((l = addr - wp) != 0) {
-		data = 0;
-		for (i=0, cp=wp; i<l; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *)cp);
-		}
-		for (; i<4 && cnt>0; ++i) {
-			data = (data << 8) | *src++;
-			--cnt;
-			++cp;
-		}
-		for (; cnt==0 && i<4; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *)cp);
-		}
-
-		if ((rc = write_word(info, wp, data)) != 0) {
-			return (rc);
-		}
-		wp += 4;
-	}
-
-	/*
-	 * handle word aligned part
-	 */
-	while (cnt >= 4) {
-		data = 0;
-		for (i=0; i<4; ++i) {
-			data = (data << 8) | *src++;
-		}
-		if ((rc = write_word(info, wp, data)) != 0) {
-			return (rc);
-		}
-		wp  += 4;
-		cnt -= 4;
-	}
-
-	if (cnt == 0) {
-		return (0);
-	}
-
-	/*
-	 * handle unaligned tail bytes
-	 */
-	data = 0;
-	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
-		data = (data << 8) | *src++;
-		--cnt;
-	}
-	for (; i<4; ++i, ++cp) {
-		data = (data << 8) | (*(uchar *)cp);
-	}
-
-	rc = write_word(info, wp, data);
-
-	return rc;
-}
-
-/*-----------------------------------------------------------------------
- * Set/Clear sector's lock bit, returns:
- * 0 - OK
- * 1 - Error (timeout, voltage problems, etc.)
- */
-int flash_real_protect(flash_info_t *info, long sector, int prot)
-{
-	ulong start;
-	int i;
-	int rc = 0;
-	vu_long *addr = (vu_long *)(info->start[sector]);
-	int flag = disable_interrupts();
-
-	*addr = INTEL_CLEAR;	/* Clear status register */
-	if (prot) {			/* Set sector lock bit */
-		*addr = INTEL_LOCKBIT;	/* Sector lock bit */
-		*addr = INTEL_PROTECT;	/* set */
-	}
-	else {				/* Clear sector lock bit */
-		*addr = INTEL_LOCKBIT;	/* All sectors lock bits */
-		*addr = INTEL_CONFIRM;	/* clear */
-	}
-
-	start = get_timer(0);
-	while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
-		if (get_timer(start) > CONFIG_SYS_FLASH_UNLOCK_TOUT) {
-			printf("Flash lock bit operation timed out\n");
-			rc = 1;
-			break;
-		}
-	}
-
-	if (*addr != INTEL_OK) {
-		printf("Flash lock bit operation failed at %08X, CSR=%08X\n",
-		       (uint)addr, (uint)*addr);
-		rc = 1;
-	}
-
-	if (!rc)
-		info->protect[sector] = prot;
-
-	/*
-	 * Clear lock bit command clears all sectors lock bits, so
-	 * we have to restore lock bits of protected sectors.
-	 */
-	if (!prot)
-		for (i = 0; i < info->sector_count; i++)
-			if (info->protect[i]) {
-				addr = (vu_long *)(info->start[i]);
-				*addr = INTEL_LOCKBIT;	/* Sector lock bit */
-				*addr = INTEL_PROTECT;	/* set */
-				udelay(CONFIG_SYS_FLASH_LOCK_TOUT * 1000);
-			}
-
-	if (flag)
-		enable_interrupts();
-
-	*addr = INTEL_RESET;		/* Reset to read array mode */
-
-	return rc;
-}
diff --git a/board/freescale/mpc8260ads/mpc8260ads.c b/board/freescale/mpc8260ads/mpc8260ads.c
deleted file mode 100644
index b8c8ce9603..0000000000
--- a/board/freescale/mpc8260ads/mpc8260ads.c
+++ /dev/null
@@ -1,544 +0,0 @@
-/*
- * (C) Copyright 2001-2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Modified during 2001 by
- * Advanced Communications Technologies (Australia) Pty. Ltd.
- * Howard Walker, Tuong Vu-Dinh
- *
- * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
- * Added support for the 16M dram simm on the 8260ads boards
- *
- * (C) Copyright 2003-2004 Arabella Software Ltd.
- * Yuli Barcohen <yuli@arabellasw.com>
- * Added support for SDRAM DIMMs SPD EEPROM, MII, Ethernet PHY init.
- *
- * Copyright (c) 2005 MontaVista Software, Inc.
- * Vitaly Bordug <vbordug@ru.mvista.com>
- * Added support for PCI.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <ioports.h>
-#include <mpc8260.h>
-#include <asm/m8260_pci.h>
-#include <i2c.h>
-#include <spd.h>
-#include <miiphy.h>
-#ifdef CONFIG_PCI
-#include <pci.h>
-#endif
-#ifdef CONFIG_OF_LIBFDT
-#include <libfdt.h>
-#include <fdt_support.h>
-#endif
-
-/*
- * I/O Port configuration table
- *
- * if conf is 1, then that port pin will be configured at boot time
- * according to the five values podr/pdir/ppar/psor/pdat for that entry
- */
-
-#define CONFIG_SYS_FCC1 (CONFIG_ETHER_INDEX == 1)
-#define CONFIG_SYS_FCC2 (CONFIG_ETHER_INDEX == 2)
-#define CONFIG_SYS_FCC3 (CONFIG_ETHER_INDEX == 3)
-
-const iop_conf_t iop_conf_tab[4][32] = {
-
-    /* Port A configuration */
-    {	/*	      conf      ppar psor pdir podr pdat */
-	/* PA31 */ { CONFIG_SYS_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII COL   */
-	/* PA30 */ { CONFIG_SYS_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII CRS   */
-	/* PA29 */ { CONFIG_SYS_FCC1,   1,   1,   1,   0,   0 }, /* FCC1 MII TX_ER */
-	/* PA28 */ { CONFIG_SYS_FCC1,   1,   1,   1,   0,   0 }, /* FCC1 MII TX_EN */
-	/* PA27 */ { CONFIG_SYS_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII RX_DV */
-	/* PA26 */ { CONFIG_SYS_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII RX_ER */
-	/* PA25 */ { 0,          0,   0,   0,   0,   0 }, /* PA25 */
-	/* PA24 */ { 0,          0,   0,   0,   0,   0 }, /* PA24 */
-	/* PA23 */ { 0,          0,   0,   0,   0,   0 }, /* PA23 */
-	/* PA22 */ { 0,          0,   0,   0,   0,   0 }, /* PA22 */
-	/* PA21 */ { CONFIG_SYS_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[3] */
-	/* PA20 */ { CONFIG_SYS_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[2] */
-	/* PA19 */ { CONFIG_SYS_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[1] */
-	/* PA18 */ { CONFIG_SYS_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[0] */
-	/* PA17 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[0] */
-	/* PA16 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[1] */
-	/* PA15 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[2] */
-	/* PA14 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[3] */
-	/* PA13 */ { 0,          0,   0,   0,   0,   0 }, /* PA13 */
-	/* PA12 */ { 0,          0,   0,   0,   0,   0 }, /* PA12 */
-	/* PA11 */ { 0,          0,   0,   0,   0,   0 }, /* PA11 */
-	/* PA10 */ { 0,          0,   0,   0,   0,   0 }, /* PA10 */
-	/* PA9  */ { 0,          0,   0,   0,   0,   0 }, /* PA9 */
-	/* PA8  */ { 0,          0,   0,   0,   0,   0 }, /* PA8 */
-	/* PA7  */ { 0,          0,   0,   1,   0,   0 }, /* PA7 */
-	/* PA6  */ { 0,          0,   0,   0,   0,   0 }, /* PA6 */
-	/* PA5  */ { 0,          0,   0,   1,   0,   0 }, /* PA5 */
-	/* PA4  */ { 0,          0,   0,   1,   0,   0 }, /* PA4 */
-	/* PA3  */ { 0,          0,   0,   1,   0,   0 }, /* PA3 */
-	/* PA2  */ { 0,          0,   0,   1,   0,   0 }, /* PA2 */
-	/* PA1  */ { 0,          0,   0,   0,   0,   0 }, /* PA1 */
-	/* PA0  */ { 0,          0,   0,   1,   0,   0 }  /* PA0 */
-    },
-
-    /* Port B configuration */
-    {   /*	      conf      ppar psor pdir podr pdat */
-	/* PB31 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TX_ER */
-	/* PB30 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RX_DV */
-	/* PB29 */ { CONFIG_SYS_FCC2,   1,   1,   1,   0,   0 }, /* FCC2 MII TX_EN */
-	/* PB28 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RX_ER */
-	/* PB27 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII COL */
-	/* PB26 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII CRS */
-	/* PB25 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[3] */
-	/* PB24 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[2] */
-	/* PB23 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[1] */
-	/* PB22 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[0] */
-	/* PB21 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[0] */
-	/* PB20 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[1] */
-	/* PB19 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[2] */
-	/* PB18 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[3] */
-	/* PB17 */ { CONFIG_SYS_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:RX_DIV */
-	/* PB16 */ { CONFIG_SYS_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:RX_ERR */
-	/* PB15 */ { CONFIG_SYS_FCC3,   1,   0,   1,   0,   0 }, /* FCC3:TX_ERR */
-	/* PB14 */ { CONFIG_SYS_FCC3,   1,   0,   1,   0,   0 }, /* FCC3:TX_EN */
-	/* PB13 */ { CONFIG_SYS_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:COL */
-	/* PB12 */ { CONFIG_SYS_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:CRS */
-	/* PB11 */ { CONFIG_SYS_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:RXD */
-	/* PB10 */ { CONFIG_SYS_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:RXD */
-	/* PB9  */ { CONFIG_SYS_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:RXD */
-	/* PB8  */ { CONFIG_SYS_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:RXD */
-	/* PB7  */ { CONFIG_SYS_FCC3,   1,   0,   1,   0,   0 }, /* FCC3:TXD */
-	/* PB6  */ { CONFIG_SYS_FCC3,   1,   0,   1,   0,   0 }, /* FCC3:TXD */
-	/* PB5  */ { CONFIG_SYS_FCC3,   1,   0,   1,   0,   0 }, /* FCC3:TXD */
-	/* PB4  */ { CONFIG_SYS_FCC3,   1,   0,   1,   0,   0 }, /* FCC3:TXD */
-	/* PB3  */ { 0,          0,   0,   0,   0,   0 }, /* pin doesn't exist */
-	/* PB2  */ { 0,          0,   0,   0,   0,   0 }, /* pin doesn't exist */
-	/* PB1  */ { 0,          0,   0,   0,   0,   0 }, /* pin doesn't exist */
-	/* PB0  */ { 0,          0,   0,   0,   0,   0 }  /* pin doesn't exist */
-    },
-
-    /* Port C */
-    {   /*	      conf      ppar psor pdir podr pdat */
-	/* PC31 */ { 0,          0,   0,   0,   0,   0 }, /* PC31 */
-	/* PC30 */ { 0,          0,   0,   0,   0,   0 }, /* PC30 */
-	/* PC29 */ { 0,          0,   0,   0,   0,   0 }, /* PC29 */
-	/* PC28 */ { 0,          0,   0,   0,   0,   0 }, /* PC28 */
-	/* PC27 */ { 0,          0,   0,   0,   0,   0 }, /* PC27 */
-	/* PC26 */ { 0,          0,   0,   0,   0,   0 }, /* PC26 */
-	/* PC25 */ { 0,          0,   0,   0,   0,   0 }, /* PC25 */
-	/* PC24 */ { 0,          0,   0,   0,   0,   0 }, /* PC24 */
-	/* PC23 */ { 0,          0,   0,   0,   0,   0 }, /* PC23 */
-	/* PC22 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII Tx Clock (CLK10) */
-	/* PC21 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII Rx Clock (CLK11) */
-	/* PC20 */ { 0,          0,   0,   0,   0,   0 }, /* PC20 */
-#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
-	/* PC19 */ { 1,          0,   0,   1,   0,   0 }, /* FETHMDC  */
-	/* PC18 */ { 1,          0,   0,   0,   0,   0 }, /* FETHMDIO */
-	/* PC17 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII Rx Clock (CLK15) */
-	/* PC16 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII Tx Clock (CLK16) */
-#else
-	/* PC19 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII Rx Clock (CLK13) */
-	/* PC18 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII Tx Clock (CLK14) */
-	/* PC17 */ { 0,          0,   0,   0,   0,   0 }, /* PC17 */
-	/* PC16 */ { 0,          0,   0,   0,   0,   0 }, /* PC16 */
-#endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */
-	/* PC15 */ { 0,          0,   0,   0,   0,   0 }, /* PC15 */
-	/* PC14 */ { 0,          0,   0,   0,   0,   0 }, /* PC14 */
-	/* PC13 */ { 0,          0,   0,   0,   0,   0 }, /* PC13 */
-	/* PC12 */ { 0,          0,   0,   0,   0,   0 }, /* PC12 */
-	/* PC11 */ { 0,          0,   0,   0,   0,   0 }, /* PC11 */
-#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
-	/* PC10 */ { 0,          0,   0,   0,   0,   0 }, /* PC10 */
-	/* PC9  */ { 0,          0,   0,   0,   0,   0 }, /* PC9  */
-#else
-	/* PC10 */ { 1,          0,   0,   1,   0,   0 }, /* FETHMDC  */
-	/* PC9  */ { 1,          0,   0,   0,   0,   0 }, /* FETHMDIO */
-#endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */
-	/* PC8  */ { 0,          0,   0,   0,   0,   0 }, /* PC8 */
-	/* PC7  */ { 0,          0,   0,   0,   0,   0 }, /* PC7 */
-	/* PC6  */ { 0,          0,   0,   0,   0,   0 }, /* PC6 */
-	/* PC5  */ { 0,          0,   0,   0,   0,   0 }, /* PC5 */
-	/* PC4  */ { 0,          0,   0,   0,   0,   0 }, /* PC4 */
-	/* PC3  */ { 0,          0,   0,   0,   0,   0 }, /* PC3 */
-	/* PC2  */ { 0,          0,   0,   0,   0,   0 }, /* PC2 */
-	/* PC1  */ { 0,          0,   0,   0,   0,   0 }, /* PC1 */
-	/* PC0  */ { 0,          0,   0,   0,   0,   0 }, /* PC0 */
-    },
-
-    /* Port D */
-    {   /*	      conf ppar psor pdir podr pdat */
-	/* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 UART RxD */
-	/* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 UART TxD */
-	/* PD29 */ {   0,   0,   0,   0,   0,   0   }, /* PD29 */
-	/* PD28 */ {   0,   1,   0,   0,   0,   0   }, /* PD28 */
-	/* PD27 */ {   0,   1,   1,   1,   0,   0   }, /* PD27 */
-	/* PD26 */ {   0,   0,   0,   1,   0,   0   }, /* PD26 */
-	/* PD25 */ {   0,   0,   0,   1,   0,   0   }, /* PD25 */
-	/* PD24 */ {   0,   0,   0,   1,   0,   0   }, /* PD24 */
-	/* PD23 */ {   0,   0,   0,   1,   0,   0   }, /* PD23 */
-	/* PD22 */ {   0,   0,   0,   1,   0,   0   }, /* PD22 */
-	/* PD21 */ {   0,   0,   0,   1,   0,   0   }, /* PD21 */
-	/* PD20 */ {   0,   0,   0,   1,   0,   0   }, /* PD20 */
-	/* PD19 */ {   0,   0,   0,   1,   0,   0   }, /* PD19 */
-	/* PD18 */ {   0,   0,   0,   1,   0,   0   }, /* PD18 */
-	/* PD17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXPRTY */
-	/* PD16 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXPRTY */
-	/* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
-	/* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
-	/* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
-	/* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
-	/* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
-	/* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
-	/* PD9  */ {   0,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
-	/* PD8  */ {   0,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
-	/* PD7  */ {   0,   0,   0,   1,   0,   1   }, /* PD7 */
-	/* PD6  */ {   0,   0,   0,   1,   0,   1   }, /* PD6 */
-	/* PD5  */ {   0,   0,   0,   1,   0,   1   }, /* PD5 */
-	/* PD4  */ {   0,   0,   0,   1,   0,   1   }, /* PD4 */
-	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
-    }
-};
-
-void reset_phy (void)
-{
-	vu_long *bcsr = (vu_long *)CONFIG_SYS_BCSR;
-
-	/* Reset the PHY */
-#if CONFIG_SYS_PHY_ADDR == 0
-	bcsr[1] &= ~(FETHIEN1 | FETH1_RST);
-	udelay(2);
-	bcsr[1] |=  FETH1_RST;
-#else
-	bcsr[3] &= ~(FETHIEN2 | FETH2_RST);
-	udelay(2);
-	bcsr[3] |=  FETH2_RST;
-#endif /* CONFIG_SYS_PHY_ADDR == 0 */
-	udelay(1000);
-#ifdef CONFIG_MII
-#if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
-	/*
-	 * Do not bypass Rx/Tx (de)scrambler (fix configuration error)
-	 * Enable autonegotiation.
-	 */
-	bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, 16, 0x610);
-	bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, MII_BMCR,
-			BMCR_ANENABLE | BMCR_ANRESTART);
-#else
-	/*
-	 * Ethernet PHY is configured (by means of configuration pins)
-	 * to work at 10Mb/s only. We reconfigure it using MII
-	 * to advertise all capabilities, including 100Mb/s, and
-	 * restart autonegotiation.
-	 */
-
-	/* Advertise all capabilities */
-	bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, MII_ADVERTISE, 0x01E1);
-
-	/* Do not bypass Rx/Tx (de)scrambler */
-	bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, MII_FCSCOUNTER,  0x0000);
-
-	bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, MII_BMCR,
-			BMCR_ANENABLE | BMCR_ANRESTART);
-#endif /* CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS */
-#endif /* CONFIG_MII */
-}
-
-#ifdef CONFIG_PCI
-typedef struct pci_ic_s {
-	unsigned long pci_int_stat;
-	unsigned long pci_int_mask;
-}pci_ic_t;
-#endif
-
-int board_early_init_f (void)
-{
-	vu_long *bcsr = (vu_long *)CONFIG_SYS_BCSR;
-
-#ifdef CONFIG_PCI
-	volatile pci_ic_t* pci_ic = (pci_ic_t *) CONFIG_SYS_PCI_INT;
-
-	/* mask alll the PCI interrupts */
-	pci_ic->pci_int_mask |= 0xfff00000;
-#endif
-#if (CONFIG_CONS_INDEX == 1) || (CONFIG_KGDB_INDEX == 1)
-	bcsr[1] &= ~RS232EN_1;
-#endif
-#if (CONFIG_CONS_INDEX > 1) || (CONFIG_KGDB_INDEX > 1)
-	bcsr[1] &= ~RS232EN_2;
-#endif
-
-#if CONFIG_ADSTYPE != CONFIG_SYS_8260ADS /* PCI mode can be selected */
-#if CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
-	if ((bcsr[3] & BCSR_PCI_MODE) == 0) /* PCI mode selected by JP9 */
-#endif /* CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS */
-	{
-		volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-
-		immap->im_clkrst.car_sccr |= M826X_SCCR_PCI_MODE_EN;
-		immap->im_siu_conf.sc_siumcr =
-			(immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
-			| SIUMCR_LBPC01;
-	}
-#endif /* CONFIG_ADSTYPE != CONFIG_SYS_8260ADS */
-
-	return 0;
-}
-
-#define ns2clk(ns) (ns / (1000000000 / CONFIG_8260_CLKIN) + 1)
-
-phys_size_t initdram (int board_type)
-{
-#if   CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
-	long int msize = 32;
-#elif CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
-	long int msize = 64;
-#else
-	long int msize = 16;
-#endif
-
-#ifndef CONFIG_SYS_RAMBOOT
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile memctl8260_t *memctl = &immap->im_memctl;
-	volatile uchar *ramaddr, c = 0xff;
-	uint or;
-	uint psdmr;
-	uint psrt;
-
-	int i;
-
-	immap->im_siu_conf.sc_ppc_acr  = 0x00000002;
-	immap->im_siu_conf.sc_ppc_alrh = 0x01267893;
-	immap->im_siu_conf.sc_tescr1   = 0x00004000;
-
-	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
-#ifdef CONFIG_SYS_LSDRAM_BASE
-	/*
-	  Initialise local bus SDRAM only if the pins
-	  are configured as local bus pins and not as PCI.
-	  The configuration is determined by the HRCW.
-	*/
-	if ((immap->im_siu_conf.sc_siumcr & SIUMCR_LBPC11) == SIUMCR_LBPC00) {
-		memctl->memc_lsrt  = CONFIG_SYS_LSRT;
-#if CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS /* CS3 */
-		memctl->memc_or3   = 0xFF803280;
-		memctl->memc_br3   = CONFIG_SYS_LSDRAM_BASE | 0x00001861;
-#else				  /* CS4 */
-		memctl->memc_or4   = 0xFFC01480;
-		memctl->memc_br4   = CONFIG_SYS_LSDRAM_BASE | 0x00001861;
-#endif /* CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS */
-		memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x28000000;
-		ramaddr = (uchar *) CONFIG_SYS_LSDRAM_BASE;
-		*ramaddr = c;
-		memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x08000000;
-		for (i = 0; i < 8; i++)
-			*ramaddr = c;
-		memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x18000000;
-		*ramaddr = c;
-		memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x40000000;
-	}
-#endif /* CONFIG_SYS_LSDRAM_BASE */
-
-	/* Init 60x bus SDRAM */
-#ifdef CONFIG_SPD_EEPROM
-	{
-		spd_eeprom_t spd;
-		uint pbi, bsel, rowst, lsb, tmp;
-
-		i2c_read (CONFIG_SPD_ADDR, 0, 1, (uchar *) & spd, sizeof (spd));
-
-		/* Bank-based interleaving is not supported for physical bank
-		   sizes greater than 128MB which is encoded as 0x20 in SPD
-		 */
-		pbi = (spd.row_dens > 32) ? 1 : CONFIG_SDRAM_PBI;
-		msize = spd.nrows * (4 * spd.row_dens);	/* Mixed size not supported */
-		or = ~(msize - 1) << 20;	/* SDAM */
-		switch (spd.nbanks) {	/* BPD */
-		case 2:
-			bsel = 1;
-			break;
-		case 4:
-			bsel = 2;
-			or |= 0x00002000;
-			break;
-		case 8:
-			bsel = 3;
-			or |= 0x00004000;
-			break;
-		}
-		lsb = 3;	/* For 64-bit port, lsb is 3 bits */
-
-		if (pbi) {	/* Bus partition depends on interleaving */
-			rowst = 32 - (spd.nrow_addr + spd.ncol_addr + bsel + lsb);
-			or |= (rowst << 9);	/* ROWST */
-		} else {
-			rowst = 32 - (spd.nrow_addr + spd.ncol_addr + lsb);
-			or |= ((rowst * 2 - 12) << 9);	/* ROWST */
-		}
-		or |= ((spd.nrow_addr - 9) << 6);	/* NUMR */
-
-		psdmr = (pbi << 31);	/* PBI */
-		/* Bus multiplexing parameters */
-		tmp = 32 - (lsb + spd.nrow_addr);	/* Tables 10-19 and 10-20 */
-		psdmr |= ((tmp - (rowst - 5) - 13) << 24);	/* SDAM */
-		psdmr |= ((tmp - 3 - 12) << 21);	/* BSMA */
-
-		tmp = (31 - lsb - 10) - tmp;
-		/* Pin connected to SDA10 is (31 - lsb - 10).
-		   rowst is multiplexed over (32 - (lsb + spd.nrow_addr)),
-		   so (rowst + tmp) alternates with AP.
-		 */
-		if (pbi)				/* Table 10-7 */
-			psdmr |= ((10 - (rowst + tmp)) << 18);	/* SDA10 */
-		else
-			psdmr |= ((12 - (rowst + tmp)) << 18);	/* SDA10 */
-
-		/* SDRAM device-specific parameters */
-		tmp = ns2clk (70);	/* Refresh recovery is not in SPD, so assume 70ns */
-		switch (tmp) {		/* RFRC */
-		case 1:
-		case 2:
-			psdmr |= (1 << 15);
-			break;
-		case 3:
-		case 4:
-		case 5:
-		case 6:
-		case 7:
-		case 8:
-			psdmr |= ((tmp - 2) << 15);
-			break;
-		default:
-			psdmr |= (7 << 15);
-		}
-		psdmr |= (ns2clk (spd.trp) % 8 << 12);	/* PRETOACT */
-		psdmr |= (ns2clk (spd.trcd) % 8 << 9);	/* ACTTORW */
-		/* BL=0 because for 64-bit SDRAM burst length must be 4 */
-		/* LDOTOPRE ??? */
-		for (i = 0, tmp = spd.write_lat; (i < 4) && ((tmp & 1) == 0); i++)
-			tmp >>= 1;
-		switch (i) {			/* WRC */
-		case 0:
-		case 1:
-			psdmr |= (1 << 4);
-			break;
-		case 2:
-		case 3:
-			psdmr |= (i << 4);
-			break;
-		}
-		/* EAMUX=0 - no external address multiplexing */
-		/* BUFCMD=0 - no external buffers */
-		for (i = 1, tmp = spd.cas_lat; (i < 3) && ((tmp & 1) == 0); i++)
-			tmp >>= 1;
-		psdmr |= i;				/* CL */
-
-		switch (spd.refresh & 0x7F) {
-		case 1:
-			tmp = 3900;
-			break;
-		case 2:
-			tmp = 7800;
-			break;
-		case 3:
-			tmp = 31300;
-			break;
-		case 4:
-			tmp = 62500;
-			break;
-		case 5:
-			tmp = 125000;
-			break;
-		default:
-			tmp = 15625;
-		}
-		psrt = tmp / (1000000000 / CONFIG_8260_CLKIN *
-				  ((memctl->memc_mptpr >> 8) + 1)) - 1;
-#ifdef SPD_DEBUG
-		printf ("\nDIMM type:       %-18.18s\n", spd.mpart);
-		printf ("SPD size:        %d\n", spd.info_size);
-		printf ("EEPROM size:     %d\n", 1 << spd.chip_size);
-		printf ("Memory type:     %d\n", spd.mem_type);
-		printf ("Row addr:        %d\n", spd.nrow_addr);
-		printf ("Column addr:     %d\n", spd.ncol_addr);
-		printf ("# of rows:       %d\n", spd.nrows);
-		printf ("Row density:     %d\n", spd.row_dens);
-		printf ("# of banks:      %d\n", spd.nbanks);
-		printf ("Data width:      %d\n",
-				256 * spd.dataw_msb + spd.dataw_lsb);
-		printf ("Chip width:      %d\n", spd.primw);
-		printf ("Refresh rate:    %02X\n", spd.refresh);
-		printf ("CAS latencies:   %02X\n", spd.cas_lat);
-		printf ("Write latencies: %02X\n", spd.write_lat);
-		printf ("tRP:             %d\n", spd.trp);
-		printf ("tRCD:            %d\n", spd.trcd);
-
-		printf ("OR=%X, PSDMR=%08X, PSRT=%0X\n", or, psdmr, psrt);
-#endif /* SPD_DEBUG */
-	}
-#else  /* !CONFIG_SPD_EEPROM */
-	or    = CONFIG_SYS_OR2;
-	psdmr = CONFIG_SYS_PSDMR;
-	psrt  = CONFIG_SYS_PSRT;
-#endif /* CONFIG_SPD_EEPROM */
-	memctl->memc_psrt = psrt;
-	memctl->memc_or2 = or;
-	memctl->memc_br2 = CONFIG_SYS_SDRAM_BASE | 0x00000041;
-	ramaddr = (uchar *) CONFIG_SYS_SDRAM_BASE;
-	memctl->memc_psdmr = psdmr | 0x28000000;	/* Precharge all banks */
-	*ramaddr = c;
-	memctl->memc_psdmr = psdmr | 0x08000000;	/* CBR refresh */
-	for (i = 0; i < 8; i++)
-		*ramaddr = c;
-
-	memctl->memc_psdmr = psdmr | 0x18000000;	/* Mode Register write */
-	*ramaddr = c;
-	memctl->memc_psdmr = psdmr | 0x40000000;	/* Refresh enable */
-	*ramaddr = c;
-#endif /* CONFIG_SYS_RAMBOOT */
-
-	/* return total 60x bus SDRAM size */
-	return (msize * 1024 * 1024);
-}
-
-int checkboard (void)
-{
-#if   CONFIG_ADSTYPE == CONFIG_SYS_8260ADS
-	puts ("Board: Motorola MPC8260ADS\n");
-#elif CONFIG_ADSTYPE == CONFIG_SYS_8266ADS
-	puts ("Board: Motorola MPC8266ADS\n");
-#elif CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
-	puts ("Board: Motorola PQ2FADS-ZU\n");
-#elif CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
-	puts ("Board: Motorola MPC8272ADS\n");
-#else
-	puts ("Board: unknown\n");
-#endif
-	return 0;
-}
-
-#ifdef CONFIG_PCI
-struct pci_controller hose;
-
-extern void pci_mpc8250_init(struct pci_controller *);
-
-void pci_init_board(void)
-{
-	pci_mpc8250_init(&hose);
-}
-#endif
-
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup(blob, bd);
-#ifdef CONFIG_PCI
-	ft_pci_setup(blob, bd);
-#endif
-}
-#endif
diff --git a/board/freescale/mx31ads/u-boot.lds b/board/freescale/mx31ads/u-boot.lds
index 61b83bfc63..8a4a8a2f07 100644
--- a/board/freescale/mx31ads/u-boot.lds
+++ b/board/freescale/mx31ads/u-boot.lds
@@ -70,6 +70,8 @@ SECTIONS
 		*(.__rel_dyn_end)
 	}
 
+	.hash : { *(.hash*) }
+
 	.end :
 	{
 		*(.__end)
@@ -100,7 +102,7 @@ SECTIONS
 	.dynbss : { *(.dynbss) }
 	.dynstr : { *(.dynstr*) }
 	.dynamic : { *(.dynamic*) }
-	.hash : { *(.hash*) }
+	.gnu.hash : { *(.gnu.hash) }
 	.plt : { *(.plt*) }
 	.interp : { *(.interp*) }
 	.gnu : { *(.gnu*) }
diff --git a/board/freescale/p1023rds/p1023rds.c b/board/freescale/p1023rds/p1023rds.c
index d8c87458e8..2b883c719e 100644
--- a/board/freescale/p1023rds/p1023rds.c
+++ b/board/freescale/p1023rds/p1023rds.c
@@ -182,11 +182,6 @@ void ft_board_setup(void *blob, bd_t *bd)
 
 	fdt_fixup_memory(blob, (u64)base, (u64)size);
 
-	/* By default NOR is on, and NAND is disabled */
-#ifdef CONFIG_NAND_U_BOOT
-	do_fixup_by_path_string(blob, "nor_flash", "status", "disabled");
-	do_fixup_by_path_string(blob, "nand_flash", "status", "okay");
-#endif
 #ifdef CONFIG_HAS_FSL_DR_USB
 	fdt_fixup_dr_usb(blob, bd);
 #endif
diff --git a/board/freescale/p1023rds/tlb.c b/board/freescale/p1023rds/tlb.c
index 8b2bf50799..3c92c14ae3 100644
--- a/board/freescale/p1023rds/tlb.c
+++ b/board/freescale/p1023rds/tlb.c
@@ -36,7 +36,6 @@ struct fsl_e_tlb_entry tlb_table[] = {
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 1, BOOKE_PAGESZ_4M, 1),
 
-#ifndef CONFIG_NAND_SPL
 	/* *W*G* - BCSR and NOR flash on local bus*/
 	/* This will be changed to *I*G* after relocation to RAM. */
 	SET_TLB_ENTRY(1, CONFIG_SYS_BCSR_BASE, CONFIG_SYS_BCSR_BASE_PHYS,
@@ -79,7 +78,6 @@ struct fsl_e_tlb_entry tlb_table[] = {
 		      CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 10, BOOKE_PAGESZ_1M, 1),
-#endif
 
 	/* *I*G - NAND */
 	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
diff --git a/board/freescale/t208xqds/ddr.h b/board/freescale/t208xqds/ddr.h
index 9fc879a4ef..ed52fef621 100644
--- a/board/freescale/t208xqds/ddr.h
+++ b/board/freescale/t208xqds/ddr.h
@@ -25,21 +25,21 @@ struct board_specific_parameters {
 static const struct board_specific_parameters udimm0[] = {
 	/*
 	 * memory controller 0
-	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl |
-	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |
+	 *   num|  hi| rank|  clk| wrlvl | wrlvl | wrlvl |
+	 * ranks| mhz| GB  |adjst| start | ctl2  | ctl3  |
 	 */
-	{2,  1200, 2, 5,     7, 0x0808090a, 0x0b0c0c0a},
-	{2,  1500, 2, 5,     6, 0x07070809, 0x0a0b0b09},
-	{2,  1600, 2, 5,     8, 0x090b0b0d, 0x0d0e0f0b},
-	{2,  1700, 2, 4,     7, 0x080a0a0c, 0x0c0d0e0a},
-	{2,  1900, 2, 5,     9, 0x0a0b0c0e, 0x0f10120c},
-	{2,  2140, 2, 4,     8, 0x090a0b0d, 0x0e0f110b},
-	{1,  1200, 2, 5,     7, 0x0808090a, 0x0b0c0c0a},
-	{1,  1500, 2, 5,     6, 0x07070809, 0x0a0b0b09},
-	{1,  1600, 2, 5,     8, 0x090b0b0d, 0x0d0e0f0b},
-	{1,  1700, 2, 4,     7, 0x080a0a0c, 0x0c0d0e0a},
-	{1,  1900, 2, 5,     9, 0x0a0b0c0e, 0x0f10120c},
-	{1,  2140, 2, 4,     8, 0x090a0b0d, 0x0e0f110b},
+	{2,  1200,  0,  5,  7,  0x0808090a,  0x0b0c0c0a},
+	{2,  1500,  0,  5,  6,  0x07070809,  0x0a0b0b09},
+	{2,  1600,  0,  5,  8,  0x090b0b0d,  0x0d0e0f0b},
+	{2,  1700,  0,  4,  7,  0x080a0a0c,  0x0c0d0e0a},
+	{2,  1900,  0,  5,  9,  0x0a0b0c0e,  0x0f10120c},
+	{2,  2140,  0,  4,  8,  0x090a0b0d,  0x0e0f110b},
+	{1,  1200,  0,  5,  7,  0x0808090a,  0x0b0c0c0a},
+	{1,  1500,  0,  5,  6,  0x07070809,  0x0a0b0b09},
+	{1,  1600,  0,  5,  8,  0x090b0b0d,  0x0d0e0f0b},
+	{1,  1700,  0,  4,  7,  0x080a0a0c,  0x0c0d0e0a},
+	{1,  1900,  0,  5,  9,  0x0a0b0c0e,  0x0f10120c},
+	{1,  2140,  0,  4,  8,  0x090a0b0d,  0x0e0f110b},
 	{}
 };
 
diff --git a/board/freescale/t208xqds/eth_t208xqds.c b/board/freescale/t208xqds/eth_t208xqds.c
index d7a804d22a..5879198e4d 100644
--- a/board/freescale/t208xqds/eth_t208xqds.c
+++ b/board/freescale/t208xqds/eth_t208xqds.c
@@ -416,6 +416,7 @@ int board_eth_init(bd_t *bis)
 		fm_info_set_phy_address(FM1_DTSEC10, RGMII_PHY2_ADDR);
 
 	switch (srds_s1) {
+	case 0x1b:
 	case 0x1c:
 	case 0x95:
 	case 0xa2:
@@ -429,8 +430,11 @@ int board_eth_init(bd_t *bis)
 		fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
 		fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
 		break;
+	case 0x50:
 	case 0x51:
+	case 0x5e:
 	case 0x5f:
+	case 0x64:
 	case 0x65:
 		/* T2080QDS: XAUI/HiGig in Slot3;  T2081QDS: in Slot2 */
 		fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
@@ -439,6 +443,7 @@ int board_eth_init(bd_t *bis)
 		fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
 		break;
 	case 0x66:
+	case 0x67:
 		/*
 		 * XFI does not need a PHY to work, but to avoid U-boot use
 		 * default PHY address which is zero to a MAC when it found
@@ -453,6 +458,7 @@ int board_eth_init(bd_t *bis)
 		fm_info_set_phy_address(FM1_10GEC3, 6);
 		fm_info_set_phy_address(FM1_10GEC4, 7);
 		break;
+	case 0x6a:
 	case 0x6b:
 		fm_info_set_phy_address(FM1_10GEC1, 4);
 		fm_info_set_phy_address(FM1_10GEC2, 5);
@@ -470,6 +476,7 @@ int board_eth_init(bd_t *bis)
 		fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
 		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
 		break;
+	case 0x70:
 	case 0x71:
 		/* SGMII in Slot3 */
 		fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
@@ -625,6 +632,7 @@ int board_eth_init(bd_t *bis)
 			fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
 
 			if ((srds_s1 == 0x66) || (srds_s1 == 0x6b) ||
+			    (srds_s1 == 0x6a) || (srds_s1 == 0x70) ||
 			    (srds_s1 == 0x6c) || (srds_s1 == 0x6d) ||
 			    (srds_s1 == 0x71)) {
 				/* As XFI is in cage intead of a slot, so
diff --git a/board/freescale/t208xqds/t2080_rcw.cfg b/board/freescale/t208xqds/t2080_rcw.cfg
index c2ad0fda55..972dedc687 100644
--- a/board/freescale/t208xqds/t2080_rcw.cfg
+++ b/board/freescale/t208xqds/t2080_rcw.cfg
@@ -3,6 +3,6 @@ aa55aa55 010e0100
 #SerDes Protocol: 0x66_0x16
 #Core/DDR: 1533Mhz/2133MT/s
 12100017 15000000 00000000 00000000
-66160002 00008400 e8104000 c1000000
+66150002 00008400 e8104000 c1000000
 00000000 00000000 00000000 000307fc
 00000000 00000000 00000000 00000004
diff --git a/board/freescale/t208xqds/t208xqds.c b/board/freescale/t208xqds/t208xqds.c
index 9cfc0bd7c3..135343949e 100644
--- a/board/freescale/t208xqds/t208xqds.c
+++ b/board/freescale/t208xqds/t208xqds.c
@@ -105,6 +105,7 @@ int brd_mux_lane_to_slot(void)
 		/* SerDes1 is not enabled */
 		break;
 #if defined(CONFIG_T2080QDS)
+	case 0x1b:
 	case 0x1c:
 	case 0xa2:
 		/* SD1(A:D) => SLOT3 SGMII
@@ -126,6 +127,7 @@ int brd_mux_lane_to_slot(void)
 		 */
 		QIXIS_WRITE(brdcfg[12], 0x3a);
 		break;
+	case 0x50:
 	case 0x51:
 		/* SD1(A:D) => SLOT3 XAUI
 		 * SD1(E)   => SLOT1 PCIe4
@@ -140,6 +142,7 @@ int brd_mux_lane_to_slot(void)
 		 */
 		QIXIS_WRITE(brdcfg[12], 0xfe);
 		break;
+	case 0x6a:
 	case 0x6b:
 		/* SD1(A:D) => XFI cage
 		 * SD1(E)   => SLOT1 PCIe4
@@ -184,6 +187,7 @@ int brd_mux_lane_to_slot(void)
 		 QIXIS_WRITE(brdcfg[12], 0x1a);
 		 break;
 #elif defined(CONFIG_T2081QDS)
+	case 0x50:
 	case 0x51:
 		/* SD1(A:D) => SLOT2 XAUI
 		 * SD1(E)   => SLOT1 PCIe4 x1
@@ -192,6 +196,7 @@ int brd_mux_lane_to_slot(void)
 		QIXIS_WRITE(brdcfg[12], 0x98);
 		QIXIS_WRITE(brdcfg[13], 0x70);
 		break;
+	case 0x6a:
 	case 0x6b:
 		/* SD1(A:D) => XFI SFP Module
 		 * SD1(E)   => SLOT1 PCIe4 x1
@@ -201,13 +206,6 @@ int brd_mux_lane_to_slot(void)
 		QIXIS_WRITE(brdcfg[13], 0x70);
 		break;
 	case 0x6c:
-		/* SD1(A:B) => XFI SFP Module
-		 * SD1(C:D) => SLOT2 SGMII
-		 * SD1(E:H) => SLOT1 PCIe4 x4
-		 */
-		QIXIS_WRITE(brdcfg[12], 0xe8);
-		QIXIS_WRITE(brdcfg[13], 0x0);
-		break;
 	case 0x6d:
 		/* SD1(A:B) => XFI SFP Module
 		 * SD1(C:D) => SLOT2 SGMII
diff --git a/board/freescale/t208xrdb/t2080_rcw.cfg b/board/freescale/t208xrdb/t2080_rcw.cfg
index cd62cc8641..15e1bf43dd 100644
--- a/board/freescale/t208xrdb/t2080_rcw.cfg
+++ b/board/freescale/t208xrdb/t2080_rcw.cfg
@@ -3,6 +3,6 @@ aa55aa55 010e0100
 #SerDes Protocol: 0x66_0x16
 #Core/DDR: 1533Mhz/1600MT/s
 120c0017 15000000 00000000 00000000
-66160002 00008400 ec104000 c1000000
+66150002 00008400 ec104000 c1000000
 00000000 00000000 00000000 000307fc
 00000000 00000000 00000000 00000004
diff --git a/board/freescale/t4qds/eth.c b/board/freescale/t4qds/eth.c
index 24cf907430..6210e4618f 100644
--- a/board/freescale/t4qds/eth.c
+++ b/board/freescale/t4qds/eth.c
@@ -449,7 +449,9 @@ int board_eth_init(bd_t *bis)
 		fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
 		fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR);
 		break;
+	case 27:
 	case 28:
+	case 35:
 	case 36:
 		/* SGMII in Slot1 and Slot2 */
 		fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
@@ -465,6 +467,7 @@ int board_eth_init(bd_t *bis)
 						slot_qsgmii_phyaddr[1][2]);
 		}
 		break;
+	case 37:
 	case 38:
 		fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
 		fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
@@ -479,8 +482,11 @@ int board_eth_init(bd_t *bis)
 						slot_qsgmii_phyaddr[1][3]);
 		}
 		break;
+	case 39:
 	case 40:
+	case 45:
 	case 46:
+	case 47:
 	case 48:
 		fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
 		fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
@@ -585,12 +591,17 @@ int board_eth_init(bd_t *bis)
 		fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
 		fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC2_PHY_ADDR);
 		break;
+	case 6:
 	case 7:
+	case 12:
 	case 13:
 	case 14:
+	case 15:
 	case 16:
+	case 21:
 	case 22:
 	case 23:
+	case 24:
 	case 25:
 	case 26:
 		/* XAUI/HiGig in Slot3, SGMII in Slot4 */
@@ -600,7 +611,9 @@ int board_eth_init(bd_t *bis)
 		fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
 		fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
 		break;
+	case 27:
 	case 28:
+	case 35:
 	case 36:
 		/* SGMII in Slot3 and Slot4 */
 		fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
@@ -612,6 +625,7 @@ int board_eth_init(bd_t *bis)
 		fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]);
 		fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]);
 		break;
+	case 37:
 	case 38:
 		/* QSGMII in Slot3 and Slot4 */
 		fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
@@ -623,8 +637,11 @@ int board_eth_init(bd_t *bis)
 		fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][2]);
 		fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][3]);
 		break;
+	case 39:
 	case 40:
+	case 45:
 	case 46:
+	case 47:
 	case 48:
 		/* SGMII in Slot3 */
 		fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
@@ -637,8 +654,11 @@ int board_eth_init(bd_t *bis)
 		fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
 		fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
 		break;
+	case 49:
 	case 50:
+	case 51:
 	case 52:
+	case 53:
 	case 54:
 		fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
 		fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
diff --git a/board/freescale/t4qds/t4240qds.c b/board/freescale/t4qds/t4240qds.c
index 79b770b488..fe1bc7f08d 100644
--- a/board/freescale/t4qds/t4240qds.c
+++ b/board/freescale/t4qds/t4240qds.c
@@ -354,14 +354,18 @@ int config_frontside_crossbar_vsc3316(void)
 			FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
 	srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
 	switch (srds_prtcl_s1) {
+	case 37:
 	case 38:
 		/* swap first lane and third lane on slot1 */
 		vsc3316_fsm1_tx[0][1] = 14;
 		vsc3316_fsm1_tx[6][1] = 0;
 		vsc3316_fsm1_rx[1][1] = 2;
 		vsc3316_fsm1_rx[6][1] = 13;
+	case 39:
 	case 40:
+	case 45:
 	case 46:
+	case 47:
 	case 48:
 		/* swap first lane and third lane on slot2 */
 		vsc3316_fsm1_tx[2][1] = 8;
@@ -382,17 +386,24 @@ int config_frontside_crossbar_vsc3316(void)
 				FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
 	srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
 	switch (srds_prtcl_s2) {
+	case 37:
 	case 38:
 		/* swap first lane and third lane on slot3 */
 		vsc3316_fsm2_tx[2][1] = 11;
 		vsc3316_fsm2_tx[5][1] = 4;
 		vsc3316_fsm2_rx[2][1] = 9;
 		vsc3316_fsm2_rx[4][1] = 7;
+	case 39:
 	case 40:
+	case 45:
 	case 46:
+	case 47:
 	case 48:
+	case 49:
 	case 50:
+	case 51:
 	case 52:
+	case 53:
 	case 54:
 		/* swap first lane and third lane on slot4 */
 		vsc3316_fsm2_tx[6][1] = 3;
@@ -425,6 +436,7 @@ int config_backside_crossbar_mux(void)
 	case 0:
 		/* SerDes3 is not enabled */
 		break;
+	case 1:
 	case 2:
 	case 9:
 	case 10:
@@ -434,13 +446,20 @@ int config_backside_crossbar_mux(void)
 		brdcfg |= BRDCFG12_SD3MX_SLOT5;
 		QIXIS_WRITE(brdcfg[12], brdcfg);
 		break;
+	case 3:
 	case 4:
+	case 5:
 	case 6:
+	case 7:
 	case 8:
+	case 11:
 	case 12:
+	case 13:
 	case 14:
+	case 15:
 	case 16:
 	case 17:
+	case 18:
 	case 19:
 	case 20:
 		/* SD3(4:7) => SLOT6(0:3) */
@@ -462,6 +481,7 @@ int config_backside_crossbar_mux(void)
 	case 0:
 		/* SerDes4 is not enabled */
 		break;
+	case 1:
 	case 2:
 		/* 10b, SD4(0:7) => SLOT7(0:7) */
 		brdcfg = QIXIS_READ(brdcfg[12]);
@@ -469,8 +489,11 @@ int config_backside_crossbar_mux(void)
 		brdcfg |= BRDCFG12_SD4MX_SLOT7;
 		QIXIS_WRITE(brdcfg[12], brdcfg);
 		break;
+	case 3:
 	case 4:
+	case 5:
 	case 6:
+	case 7:
 	case 8:
 		/* x1b, SD4(4:7) => SLOT8(0:3) */
 		brdcfg = QIXIS_READ(brdcfg[12]);
@@ -478,9 +501,13 @@ int config_backside_crossbar_mux(void)
 		brdcfg |= BRDCFG12_SD4MX_SLOT8;
 		QIXIS_WRITE(brdcfg[12], brdcfg);
 		break;
+	case 9:
 	case 10:
+	case 11:
 	case 12:
+	case 13:
 	case 14:
+	case 15:
 	case 16:
 	case 18:
 		/* 00b, SD4(4:5) => AURORA, SD4(6:7) => SATA */
diff --git a/board/freescale/t4qds/t4_rcw.cfg b/board/freescale/t4qds/t4_rcw.cfg
index 3e56817204..6f09a7bba2 100644
--- a/board/freescale/t4qds/t4_rcw.cfg
+++ b/board/freescale/t4qds/t4_rcw.cfg
@@ -1,7 +1,7 @@
 #PBL preamble and RCW header
 aa55aa55 010e0100
-#serdes protocol  1_28_6_12
+#serdes protocol  1_27_5_11
 16070019 18101916 00000000 00000000
-04383060 30548c00 ec020000 f5000000
+04362858 30548c00 ec020000 f5000000
 00000000 ee0000ee 00000000 000307fc
 00000000 00000000 00000000 00000028
diff --git a/board/freescale/t4rdb/eth.c b/board/freescale/t4rdb/eth.c
index d220475b5a..142c6a877b 100644
--- a/board/freescale/t4rdb/eth.c
+++ b/board/freescale/t4rdb/eth.c
@@ -67,7 +67,7 @@ int board_eth_init(bd_t *bis)
 	/* Register the 10G MDIO bus */
 	fm_memac_mdio_init(bis, &tgec_mdio_info);
 
-	if (srds_prtcl_s1 == 28) {
+	if ((srds_prtcl_s1 == 28) || (srds_prtcl_s1 == 27)) {
 		/* SGMII */
 		fm_info_set_phy_address(FM1_DTSEC1, SGMII_PHY_ADDR1);
 		fm_info_set_phy_address(FM1_DTSEC2, SGMII_PHY_ADDR2);
diff --git a/board/freescale/t4rdb/t4_rcw.cfg b/board/freescale/t4rdb/t4_rcw.cfg
index 13408bd01f..fdbbe5ef65 100644
--- a/board/freescale/t4rdb/t4_rcw.cfg
+++ b/board/freescale/t4rdb/t4_rcw.cfg
@@ -1,7 +1,7 @@
 #PBL preamble and RCW header
 aa55aa55 010e0100
-#serdes protocol  28_56_2_10
+#serdes protocol  27_56_1_9
 16070019 18101916 00000000 00000000
-70701050 00448c00 6c020000 f5000000
+6c700848 00448c00 6c020000 f5000000
 00000000 ee0000ee 00000000 000287fc
 00000000 50000000 00000000 00000028
diff --git a/board/gdsys/405ex/io64.c b/board/gdsys/405ex/io64.c
index 2f8e306261..3a075c471f 100644
--- a/board/gdsys/405ex/io64.c
+++ b/board/gdsys/405ex/io64.c
@@ -287,7 +287,7 @@ int last_stage_init(void)
 	for (fpga = 0; fpga < 2; ++fpga) {
 		for (k = 0; k < 32; ++k) {
 			u16 status;
-			FPGA_GET_REG(k, ch[k].status_int, &status);
+			FPGA_GET_REG(fpga, ch[k].status_int, &status);
 			if (!(status & (1 << 4))) {
 				failed = 1;
 				printf("fpga %d channel %d: no serdes lock\n",
@@ -304,7 +304,7 @@ int last_stage_init(void)
 	for (fpga = 0; fpga < 2; ++fpga) {
 		for (k = 0; k < 32; ++k) {
 			u16 status;
-			FPGA_GET_REG(k, hicb_ch[k].status_int, &status);
+			FPGA_GET_REG(fpga, hicb_ch[k].status_int, &status);
 			if (status)
 				printf("fpga %d hicb %d: hicb status %04x\n",
 					fpga, k, status);
diff --git a/board/gdsys/p1022/controlcenterd-id.c b/board/gdsys/p1022/controlcenterd-id.c
index 3fca3c53b2..7e13c9051c 100644
--- a/board/gdsys/p1022/controlcenterd-id.c
+++ b/board/gdsys/p1022/controlcenterd-id.c
@@ -30,7 +30,7 @@
 #include <i2c.h>
 #include <mmc.h>
 #include <tpm.h>
-#include <sha1.h>
+#include <u-boot/sha1.h>
 #include <asm/byteorder.h>
 #include <asm/unaligned.h>
 #include <pca9698.h>
diff --git a/board/gdsys/p1022/controlcenterd.c b/board/gdsys/p1022/controlcenterd.c
index 8ccd9ce6ba..642b807e80 100644
--- a/board/gdsys/p1022/controlcenterd.c
+++ b/board/gdsys/p1022/controlcenterd.c
@@ -221,11 +221,7 @@ void hw_watchdog_reset(void)
 #ifdef CONFIG_TRAILBLAZER
 int do_bootd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
-	int rcode = 0;
-
-	if (run_command(getenv("bootcmd"), flag) < 0)
-		rcode = 1;
-	return rcode;
+	return run_command(getenv("bootcmd"), flag);
 }
 
 int board_early_init_r(void)
diff --git a/board/hidden_dragon/Makefile b/board/hidden_dragon/Makefile
deleted file mode 100644
index eb1c5fdf86..0000000000
--- a/board/hidden_dragon/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y =  hidden_dragon.o flash.o
diff --git a/board/hidden_dragon/README b/board/hidden_dragon/README
deleted file mode 100644
index 529fe2be0e..0000000000
--- a/board/hidden_dragon/README
+++ /dev/null
@@ -1,60 +0,0 @@
-U-Boot for Hidden Dragon board
-------------------------------
-
-Hidden Dragon is a MPC824x-based board by Motorola. For the most
-part it is similar to Sandpoint8245 board. So unless otherwise
-mentioned, the codes in this directory are adapted from ../sandpoint
-directory.
-
-Apparently there are very few of this board out there. Even Motorola
-website does not have any info on it.
-
-RAM:
-  start = 0x0000 0000
-  size	= 0x0200 0000 (32 MB)
-
-Flash:
-  BANK ONE:
-    start = 0xFFE0 0000
-    size  = 0x0020 0000 (2 MB)
-    flash chip = 29LV160TE (1x16 Mbits or 2x8 Mbits)
-    flash sectors = 16K, 2x8K, 32K, 31x64K
-
-  BANK TWO:
-    NONE
-
-The processor interrupt vectors reside on the first 256 bytes
-starting from address 0xFFF00000. The "reset vector" (first
-instruction executed after reset) is located on 0xFFF0 0100.
-
-U-Boot is configured to reside in flash starting at the address of
-0xFFF00000. The environment space is located in flash separately from
-U-Boot, at the second sector of the first flash bank, starting from
-0xFFE04000 until 0xFFE06000 (8KB).
-
-Network:
-  - RTL8139 chip on the base board	  (SUPPORTED)
-  - RTL8129 chip on the processor board	  (NOT SUPPORTED)
-
-Serial:
-  - Two NS16550 compatible UART on the processor board	(SUPPORTED)
-  - One NS16550 compatible UART on the base board	(UNTESTED)
-
-Misc:
-  VIA686A PCI SuperIO peripheral controller
-  - 2 USB ports		    (UNTESTED)
-  - 2 PS2 ports		    (UNTESTED)
-  - Parallel port	    (UNTESTED)
-  - IDE & floppy interface  (UNTESTED)
-
-  S3 Savage4 video card	    (UNTESTED)
-
-TODO:
------
-- Support for the VIA686A based peripherals
-- The RTL8139 driver frequently gives rx error.
-- Support for RTL8129 network controller. (Why is the support removed from
-  rtl8139.c driver?)
-
-(C) Copyright 2004
-Yusdi Santoso, Adaptec Inc., yusdi_santoso@adaptec.com
diff --git a/board/hidden_dragon/flash.c b/board/hidden_dragon/flash.c
deleted file mode 100644
index fc91a03aed..0000000000
--- a/board/hidden_dragon/flash.c
+++ /dev/null
@@ -1,559 +0,0 @@
-/*
- * (C) Copyright 2004
- * Yusdi Santoso, Adaptec Inc., yusdi_santoso@adaptec.com
- *
- * (C) Copyright 2000-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc824x.h>
-#include <asm/processor.h>
-#include <asm/pci_io.h>
-#include <w83c553f.h>
-
-#define ROM_CS0_START	0xFF800000
-#define ROM_CS1_START	0xFF000000
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips    */
-
-#if defined(CONFIG_ENV_IS_IN_FLASH)
-# ifndef  CONFIG_ENV_ADDR
-#  define CONFIG_ENV_ADDR  (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-# endif
-# ifndef  CONFIG_ENV_SIZE
-#  define CONFIG_ENV_SIZE  CONFIG_ENV_SECT_SIZE
-# endif
-# ifndef  CONFIG_ENV_SECT_SIZE
-#  define CONFIG_ENV_SECT_SIZE  CONFIG_ENV_SIZE
-# endif
-#endif
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-
-/*flash command address offsets*/
-
-#define ADDR0		(0xAAA)
-#define ADDR1		(0x555)
-#define ADDR3		(0x001)
-
-#define FLASH_WORD_SIZE unsigned char
-
-/*-----------------------------------------------------------------------
- */
-
-static unsigned long flash_id (unsigned char mfct, unsigned char chip)
-	__attribute__ ((const));
-
-typedef struct {
-	FLASH_WORD_SIZE extval;
-	unsigned short intval;
-} map_entry;
-
-static unsigned long flash_id (unsigned char mfct, unsigned char chip)
-{
-	static const map_entry mfct_map[] = {
-		{(FLASH_WORD_SIZE) AMD_MANUFACT,
-		 (unsigned short) ((unsigned long) FLASH_MAN_AMD >> 16)},
-		{(FLASH_WORD_SIZE) FUJ_MANUFACT,
-		 (unsigned short) ((unsigned long) FLASH_MAN_FUJ >> 16)},
-		{(FLASH_WORD_SIZE) STM_MANUFACT,
-		 (unsigned short) ((unsigned long) FLASH_MAN_STM >> 16)},
-		{(FLASH_WORD_SIZE) MT_MANUFACT,
-		 (unsigned short) ((unsigned long) FLASH_MAN_MT >> 16)},
-		{(FLASH_WORD_SIZE) INTEL_MANUFACT,
-		 (unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)},
-		{(FLASH_WORD_SIZE) INTEL_ALT_MANU,
-		 (unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)}
-	};
-
-	static const map_entry chip_map[] = {
-		{AMD_ID_F040B, FLASH_AM040},
-		{(FLASH_WORD_SIZE) STM_ID_x800AB, FLASH_STM800AB}
-	};
-
-	const map_entry *p;
-	unsigned long result = FLASH_UNKNOWN;
-
-	/* find chip id */
-	for (p = &chip_map[0];
-	     p < &chip_map[sizeof chip_map / sizeof chip_map[0]]; p++)
-		if (p->extval == chip) {
-			result = FLASH_VENDMASK | p->intval;
-			break;
-		}
-
-	/* find vendor id */
-	for (p = &mfct_map[0];
-	     p < &mfct_map[sizeof mfct_map / sizeof mfct_map[0]]; p++)
-		if (p->extval == mfct) {
-			result &= ~FLASH_VENDMASK;
-			result |= (unsigned long) p->intval << 16;
-			break;
-		}
-
-	return result;
-}
-
-unsigned long flash_init (void)
-{
-	unsigned long i;
-	unsigned char j;
-	static const ulong flash_banks[] = CONFIG_SYS_FLASH_BANKS;
-
-	/* Init: no FLASHes known */
-	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
-		flash_info_t *const pflinfo = &flash_info[i];
-
-		pflinfo->flash_id = FLASH_UNKNOWN;
-		pflinfo->size = 0;
-		pflinfo->sector_count = 0;
-	}
-
-	/* Enable writes to Hidden Dragon flash */
-	{
-		register unsigned char temp;
-
-		CONFIG_READ_BYTE (CONFIG_SYS_WINBOND_ISA_CFG_ADDR + WINBOND_CSCR,
-				  temp);
-		temp &= ~0x20;	/* clear BIOSWP bit */
-		CONFIG_WRITE_BYTE (CONFIG_SYS_WINBOND_ISA_CFG_ADDR + WINBOND_CSCR,
-				   temp);
-	}
-
-	for (i = 0; i < sizeof flash_banks / sizeof flash_banks[0]; i++) {
-		flash_info_t *const pflinfo = &flash_info[i];
-		const unsigned long base_address = flash_banks[i];
-		volatile FLASH_WORD_SIZE *const flash =
-			(FLASH_WORD_SIZE *) base_address;
-
-		flash[0xAAA << (3 * i)] = 0xaa;
-		flash[0x555 << (3 * i)] = 0x55;
-		flash[0xAAA << (3 * i)] = 0x90;
-		__asm__ __volatile__ ("sync");
-
-		pflinfo->flash_id =
-			flash_id (flash[0x0], flash[0x2 + 14 * i]);
-
-		switch (pflinfo->flash_id & FLASH_TYPEMASK) {
-		case FLASH_AM040:
-			pflinfo->size = 0x00080000;
-			pflinfo->sector_count = 8;
-			for (j = 0; j < 8; j++) {
-				pflinfo->start[j] =
-					base_address + 0x00010000 * j;
-				pflinfo->protect[j] = flash[(j << 16) | 0x2];
-			}
-			break;
-		case FLASH_STM800AB:
-			pflinfo->size = 0x00100000;
-			pflinfo->sector_count = 19;
-			pflinfo->start[0] = base_address;
-			pflinfo->start[1] = base_address + 0x4000;
-			pflinfo->start[2] = base_address + 0x6000;
-			pflinfo->start[3] = base_address + 0x8000;
-			for (j = 1; j < 16; j++) {
-				pflinfo->start[j + 3] =
-					base_address + 0x00010000 * j;
-			}
-			break;
-		default:
-			/* The chip used is not listed in flash_id
-			   TODO: Change this to explicitly detect the flash type
-			 */
-			{
-				int sector_addr = base_address;
-
-				pflinfo->size = 0x00200000;
-				pflinfo->sector_count = 35;
-				pflinfo->start[0] = sector_addr;
-				sector_addr += 0x4000;	/* 16K */
-				pflinfo->start[1] = sector_addr;
-				sector_addr += 0x2000;	/* 8K */
-				pflinfo->start[2] = sector_addr;
-				sector_addr += 0x2000;	/* 8K */
-				pflinfo->start[3] = sector_addr;
-				sector_addr += 0x8000;	/* 32K */
-
-				for (j = 4; j < 35; j++) {
-					pflinfo->start[j] = sector_addr;
-					sector_addr += 0x10000;	/* 64K */
-				}
-			}
-			break;
-		}
-		/* Protect monitor and environment sectors
-		 */
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
-		flash_protect (FLAG_PROTECT_SET,
-			       CONFIG_SYS_MONITOR_BASE,
-			       CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
-			       &flash_info[0]);
-#endif
-
-#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
-		flash_protect (FLAG_PROTECT_SET,
-			       CONFIG_ENV_ADDR,
-			       CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
-			       &flash_info[0]);
-#endif
-
-		/* reset device to read mode */
-		flash[0x0000] = 0xf0;
-		__asm__ __volatile__ ("sync");
-	}
-
-	/* only have 1 bank */
-	return flash_info[0].size;
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t * info)
-{
-	static const char unk[] = "Unknown";
-	const char *mfct = unk, *type = unk;
-	unsigned int i;
-
-	if (info->flash_id != FLASH_UNKNOWN) {
-		switch (info->flash_id & FLASH_VENDMASK) {
-		case FLASH_MAN_AMD:
-			mfct = "AMD";
-			break;
-		case FLASH_MAN_FUJ:
-			mfct = "FUJITSU";
-			break;
-		case FLASH_MAN_STM:
-			mfct = "STM";
-			break;
-		case FLASH_MAN_SST:
-			mfct = "SST";
-			break;
-		case FLASH_MAN_BM:
-			mfct = "Bright Microelectonics";
-			break;
-		case FLASH_MAN_INTEL:
-			mfct = "Intel";
-			break;
-		}
-
-		switch (info->flash_id & FLASH_TYPEMASK) {
-		case FLASH_AM040:
-			type = "AM29F040B (512K * 8, uniform sector size)";
-			break;
-		case FLASH_AM400B:
-			type = "AM29LV400B (4 Mbit, bottom boot sect)";
-			break;
-		case FLASH_AM400T:
-			type = "AM29LV400T (4 Mbit, top boot sector)";
-			break;
-		case FLASH_AM800B:
-			type = "AM29LV800B (8 Mbit, bottom boot sect)";
-			break;
-		case FLASH_AM800T:
-			type = "AM29LV800T (8 Mbit, top boot sector)";
-			break;
-		case FLASH_AM160T:
-			type = "AM29LV160T (16 Mbit, top boot sector)";
-			break;
-		case FLASH_AM320B:
-			type = "AM29LV320B (32 Mbit, bottom boot sect)";
-			break;
-		case FLASH_AM320T:
-			type = "AM29LV320T (32 Mbit, top boot sector)";
-			break;
-		case FLASH_STM800AB:
-			type = "M29W800AB (8 Mbit, bottom boot sect)";
-			break;
-		case FLASH_SST800A:
-			type = "SST39LF/VF800 (8 Mbit, uniform sector size)";
-			break;
-		case FLASH_SST160A:
-			type = "SST39LF/VF160 (16 Mbit, uniform sector size)";
-			break;
-		}
-	}
-
-	printf ("\n  Brand: %s Type: %s\n"
-		"  Size: %lu KB in %d Sectors\n",
-		mfct, type, info->size >> 10, info->sector_count);
-
-	printf ("  Sector Start Addresses:");
-
-	for (i = 0; i < info->sector_count; i++) {
-		unsigned long size;
-		unsigned int erased;
-		unsigned long *flash = (unsigned long *) info->start[i];
-
-		/*
-		 * Check if whole sector is erased
-		 */
-		size = (i != (info->sector_count - 1)) ?
-			(info->start[i + 1] - info->start[i]) >> 2 :
-			(info->start[0] + info->size - info->start[i]) >> 2;
-
-		for (flash = (unsigned long *) info->start[i], erased = 1;
-		     (flash != (unsigned long *) info->start[i] + size)
-		     && erased; flash++)
-			erased = *flash == ~0x0UL;
-
-		printf ("%s %08lX %s %s",
-			(i % 5) ? "" : "\n   ",
-			info->start[i],
-			erased ? "E" : " ", info->protect[i] ? "RO" : "  ");
-	}
-
-	puts ("\n");
-	return;
-}
-
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
-	volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]);
-	int flag, prot, sect, l_sect;
-	ulong start, now, last;
-	unsigned char sh8b;
-
-	if ((s_first < 0) || (s_first > s_last)) {
-		if (info->flash_id == FLASH_UNKNOWN) {
-			printf ("- missing\n");
-		} else {
-			printf ("- no sectors to erase\n");
-		}
-		return 1;
-	}
-
-	if ((info->flash_id == FLASH_UNKNOWN) ||
-	    (info->flash_id > (FLASH_MAN_STM | FLASH_AMD_COMP))) {
-		printf ("Can't erase unknown flash type - aborted\n");
-		return 1;
-	}
-
-	prot = 0;
-	for (sect = s_first; sect <= s_last; ++sect) {
-		if (info->protect[sect]) {
-			prot++;
-		}
-	}
-
-	if (prot) {
-		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
-	} else {
-		printf ("\n");
-	}
-
-	l_sect = -1;
-
-	/* Check the ROM CS */
-	if ((info->start[0] >= ROM_CS1_START)
-	    && (info->start[0] < ROM_CS0_START))
-		sh8b = 3;
-	else
-		sh8b = 0;
-
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts ();
-
-	addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA;
-	addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055;
-	addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00800080;
-	addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA;
-	addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055;
-
-	/* Start erase on unprotected sectors */
-	for (sect = s_first; sect <= s_last; sect++) {
-		if (info->protect[sect] == 0) {	/* not protected */
-			addr = (FLASH_WORD_SIZE *) (info->start[0] +
-						    ((info->start[sect] -
-						      info->start[0]) << sh8b));
-			if (info->flash_id & FLASH_MAN_SST) {
-				addr[ADDR0 << sh8b] =
-					(FLASH_WORD_SIZE) 0x00AA00AA;
-				addr[ADDR1 << sh8b] =
-					(FLASH_WORD_SIZE) 0x00550055;
-				addr[ADDR0 << sh8b] =
-					(FLASH_WORD_SIZE) 0x00800080;
-				addr[ADDR0 << sh8b] =
-					(FLASH_WORD_SIZE) 0x00AA00AA;
-				addr[ADDR1 << sh8b] =
-					(FLASH_WORD_SIZE) 0x00550055;
-				addr[0] = (FLASH_WORD_SIZE) 0x00500050;	/* block erase */
-				udelay (30000);	/* wait 30 ms */
-			} else
-				addr[0] = (FLASH_WORD_SIZE) 0x00300030;	/* sector erase */
-			l_sect = sect;
-		}
-	}
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts ();
-
-	/* wait at least 80us - let's wait 1 ms */
-	udelay (1000);
-
-	/*
-	 * We wait for the last triggered sector
-	 */
-	if (l_sect < 0)
-		goto DONE;
-
-	start = get_timer (0);
-	last = start;
-	addr = (FLASH_WORD_SIZE *) (info->start[0] + ((info->start[l_sect] -
-						       info->
-						       start[0]) << sh8b));
-	while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) !=
-	       (FLASH_WORD_SIZE) 0x00800080) {
-		if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
-			printf ("Timeout\n");
-			return 1;
-		}
-		/* show that we're waiting */
-		if ((now - last) > 1000) {	/* every second */
-			serial_putc ('.');
-			last = now;
-		}
-	}
-
-      DONE:
-	/* reset to read mode */
-	addr = (FLASH_WORD_SIZE *) info->start[0];
-	addr[0] = (FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
-
-	printf (" done\n");
-	return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
-	ulong cp, wp, data;
-	int i, l, rc;
-
-	wp = (addr & ~3);	/* get lower word aligned address */
-
-	/*
-	 * handle unaligned start bytes
-	 */
-	if ((l = addr - wp) != 0) {
-		data = 0;
-		for (i = 0, cp = wp; i < l; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *) cp);
-		}
-		for (; i < 4 && cnt > 0; ++i) {
-			data = (data << 8) | *src++;
-			--cnt;
-			++cp;
-		}
-		for (; cnt == 0 && i < 4; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *) cp);
-		}
-
-		if ((rc = write_word (info, wp, data)) != 0) {
-			return (rc);
-		}
-		wp += 4;
-	}
-
-	/*
-	 * handle word aligned part
-	 */
-	while (cnt >= 4) {
-		data = 0;
-		for (i = 0; i < 4; ++i) {
-			data = (data << 8) | *src++;
-		}
-		if ((rc = write_word (info, wp, data)) != 0) {
-			return (rc);
-		}
-		wp += 4;
-		cnt -= 4;
-	}
-
-	if (cnt == 0) {
-		return (0);
-	}
-
-	/*
-	 * handle unaligned tail bytes
-	 */
-	data = 0;
-	for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
-		data = (data << 8) | *src++;
-		--cnt;
-	}
-	for (; i < 4; ++i, ++cp) {
-		data = (data << 8) | (*(uchar *) cp);
-	}
-
-	return (write_word (info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t * info, ulong dest, ulong data)
-{
-	volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) info->start[0];
-	volatile FLASH_WORD_SIZE *dest2;
-	volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data;
-	ulong start;
-	int flag;
-	int i;
-	unsigned char sh8b;
-
-	/* Check the ROM CS */
-	if ((info->start[0] >= ROM_CS1_START)
-	    && (info->start[0] < ROM_CS0_START))
-		sh8b = 3;
-	else
-		sh8b = 0;
-
-	dest2 = (FLASH_WORD_SIZE *) (((dest - info->start[0]) << sh8b) +
-				     info->start[0]);
-
-	/* Check if Flash is (sufficiently) erased */
-	if ((*dest2 & (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
-		return (2);
-	}
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts ();
-
-	for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) {
-		addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA;
-		addr2[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055;
-		addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00A000A0;
-
-		dest2[i << sh8b] = data2[i];
-
-		/* re-enable interrupts if necessary */
-		if (flag)
-			enable_interrupts ();
-
-		/* data polling for D7 */
-		start = get_timer (0);
-		while ((dest2[i << sh8b] & (FLASH_WORD_SIZE) 0x00800080) !=
-		       (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) {
-			if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
-				return (1);
-			}
-		}
-	}
-
-	return (0);
-}
diff --git a/board/hidden_dragon/hidden_dragon.c b/board/hidden_dragon/hidden_dragon.c
deleted file mode 100644
index 8d47f37955..0000000000
--- a/board/hidden_dragon/hidden_dragon.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * (C) Copyright 2004
- * Yusdi Santoso, Adaptec Inc., yusdi_santoso@adaptec.com
- *
- * (C) Copyright 2000
- * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc824x.h>
-#include <pci.h>
-#include <netdev.h>
-
-int checkboard (void)
-{
-	/*TODO: Check processor type */
-
-	puts (	"Board: Hidden Dragon "
-#ifdef CONFIG_MPC8240
-		"8240"
-#endif
-#ifdef CONFIG_MPC8245
-		"8245"
-#endif
-		" ##Test not implemented yet##\n");
-	/* TODO: Implement board test */
-	return 0;
-}
-
-phys_size_t initdram (int board_type)
-{
-	long size;
-	long new_bank0_end;
-	long mear1;
-	long emear1;
-
-	size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE);
-
-	new_bank0_end = size - 1;
-	mear1 = mpc824x_mpc107_getreg(MEAR1);
-	emear1 = mpc824x_mpc107_getreg(EMEAR1);
-	mear1 = (mear1  & 0xFFFFFF00) |
-		((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
-	emear1 = (emear1 & 0xFFFFFF00) |
-		((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
-	mpc824x_mpc107_setreg(MEAR1, mear1);
-	mpc824x_mpc107_setreg(EMEAR1, emear1);
-
-	return (size);
-}
-
-/*
- * Initialize PCI Devices, report devices found.
- */
-#ifndef CONFIG_PCI_PNP
-static struct pci_config_table pci_hidden_dragon_config_table[] = {
-	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
-	  pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
-				       PCI_ENET0_MEMADDR,
-				       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
-	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x10, PCI_ANY_ID,
-	  pci_cfgfunc_config_device, { PCI_ENET1_IOADDR,
-				       PCI_ENET1_MEMADDR,
-				       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
-	{ }
-};
-#endif
-
-struct pci_controller hose = {
-#ifndef CONFIG_PCI_PNP
-	config_table: pci_hidden_dragon_config_table,
-#endif
-};
-
-void pci_init_board(void)
-{
-	pci_mpc824x_init(&hose);
-}
-
-int board_eth_init(bd_t *bis)
-{
-	return pci_eth_init(bis);
-}
diff --git a/board/hymod/hymod.c b/board/hymod/hymod.c
index 5fec914f5a..0183f781de 100644
--- a/board/hymod/hymod.c
+++ b/board/hymod/hymod.c
@@ -8,6 +8,8 @@
  */
 
 #include <common.h>
+#include <bootretry.h>
+#include <cli.h>
 #include <mpc8260.h>
 #include <mpc8260_irq.h>
 #include <ioports.h>
@@ -413,13 +415,11 @@ last_stage_init (void)
 	hymod_conf_t *cp = &gd->bd->bi_hymod_conf;
 	int rc;
 
-#ifdef CONFIG_BOOT_RETRY_TIME
 	/*
-	 * we use the readline () function, but we also want
+	 * we use the cli_readline() function, but we also want
 	 * command timeout enabled
 	 */
-	init_cmd_timeout ();
-#endif
+	bootretry_init_cmd_timeout();
 
 	memset ((void *) cp, 0, sizeof (*cp));
 
diff --git a/board/hymod/input.c b/board/hymod/input.c
index 184902cde5..a9035d3405 100644
--- a/board/hymod/input.c
+++ b/board/hymod/input.c
@@ -6,6 +6,8 @@
  */
 
 #include <common.h>
+#include <bootretry.h>
+#include <cli.h>
 
 int
 hymod_get_serno (const char *prompt)
@@ -14,11 +16,9 @@ hymod_get_serno (const char *prompt)
 		int n, serno;
 		char *p;
 
-#ifdef CONFIG_BOOT_RETRY_TIME
-		reset_cmd_timeout ();
-#endif
+		bootretry_reset_cmd_timeout();
 
-		n = readline (prompt);
+		n = cli_readline(prompt);
 
 		if (n < 0)
 			return (n);
@@ -42,11 +42,9 @@ hymod_get_ethaddr (void)
 	for (;;) {
 		int n;
 
-#ifdef CONFIG_BOOT_RETRY_TIME
-		reset_cmd_timeout ();
-#endif
+		bootretry_reset_cmd_timeout();
 
-		n = readline ("Enter board ethernet address: ");
+		n = cli_readline("Enter board ethernet address: ");
 
 		if (n < 0)
 			return (n);
diff --git a/board/ispan/Makefile b/board/ispan/Makefile
deleted file mode 100644
index 39931fdfd6..0000000000
--- a/board/ispan/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# Copyright (C) 2004 Arabella Software Ltd.
-# Yuli Barcohen <yuli@arabellasw.com>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= ispan.o
diff --git a/board/ispan/ispan.c b/board/ispan/ispan.c
deleted file mode 100644
index c610c3bd7e..0000000000
--- a/board/ispan/ispan.c
+++ /dev/null
@@ -1,448 +0,0 @@
-/*
- * Copyright (C) 2004 Arabella Software Ltd.
- * Yuli Barcohen <yuli@arabellasw.com>
- *
- * Support for Interphase iSPAN Communications Controllers
- * (453x and others). Tested on 4532.
- *
- * Derived from iSPAN 4539 port (iphase4539) by
- * Wolfgang Grandegger <wg@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <ioports.h>
-#include <mpc8260.h>
-#include <asm/io.h>
-
-/*
- * I/O Ports configuration table
- *
- * If conf is 1, then that port pin will be configured at boot time
- * according to the five values podr/pdir/ppar/psor/pdat for that entry
- */
-
-#define CONFIG_SYS_FCC1 (CONFIG_ETHER_INDEX == 1)
-#define CONFIG_SYS_FCC2 (CONFIG_ETHER_INDEX == 2)
-#define CONFIG_SYS_FCC3 (CONFIG_ETHER_INDEX == 3)
-
-const iop_conf_t iop_conf_tab[4][32] = {
-    /* Port A */
-    {	/*	      conf      ppar psor pdir podr pdat */
-	/* PA31 */ { CONFIG_SYS_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII COL   */
-	/* PA30 */ { CONFIG_SYS_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII CRS   */
-	/* PA29 */ { CONFIG_SYS_FCC1,   1,   1,   1,   0,   0 }, /* FCC1 MII TX_ER */
-	/* PA28 */ { CONFIG_SYS_FCC1,   1,   1,   1,   0,   0 }, /* FCC1 MII TX_EN */
-	/* PA27 */ { CONFIG_SYS_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII RX_DV */
-	/* PA26 */ { CONFIG_SYS_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII RX_ER */
-	/* PA25 */ { 0,          0,   0,   0,   0,   0 }, /* PA25 */
-	/* PA24 */ { 0,          0,   0,   0,   0,   0 }, /* PA24 */
-	/* PA23 */ { 0,          0,   0,   0,   0,   0 }, /* PA23 */
-	/* PA22 */ { 0,          0,   0,   0,   0,   0 }, /* PA22 */
-	/* PA21 */ { CONFIG_SYS_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[3] */
-	/* PA20 */ { CONFIG_SYS_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[2] */
-	/* PA19 */ { CONFIG_SYS_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[1] */
-	/* PA18 */ { CONFIG_SYS_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[0] */
-	/* PA17 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[0] */
-	/* PA16 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[1] */
-	/* PA15 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[2] */
-	/* PA14 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[3] */
-	/* PA13 */ { 0,          0,   0,   0,   0,   0 }, /* PA13 */
-	/* PA12 */ { 0,          0,   0,   0,   0,   0 }, /* PA12 */
-	/* PA11 */ { 0,          0,   0,   0,   0,   0 }, /* PA11 */
-	/* PA10 */ { 0,          0,   0,   0,   0,   0 }, /* PA10 */
-	/* PA9  */ { 0,          1,   0,   1,   0,   0 }, /* SMC2 SMTXD */
-	/* PA8  */ { 0,          1,   0,   0,   0,   0 }, /* SMC2 SMRXD */
-	/* PA7  */ { 0,          0,   0,   0,   0,   0 }, /* PA7 */
-	/* PA6  */ { 0,          0,   0,   0,   0,   0 }, /* PA6 */
-	/* PA5  */ { 0,          0,   0,   0,   0,   0 }, /* PA5 */
-	/* PA4  */ { 0,          0,   0,   0,   0,   0 }, /* PA4 */
-	/* PA3  */ { 0,          0,   0,   0,   0,   0 }, /* PA3 */
-	/* PA2  */ { 0,          0,   0,   0,   0,   0 }, /* PA2 */
-	/* PA1  */ { 0,          0,   0,   0,   0,   0 }, /* PA1 */
-	/* PA0  */ { 0,          0,   0,   0,   0,   0 }  /* PA0 */
-    },
-
-    /* Port B */
-    {   /*	      conf      ppar psor pdir podr pdat */
-	/* PB31 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TX_ER  */
-	/* PB30 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RX_DV  */
-	/* PB29 */ { CONFIG_SYS_FCC2,   1,   1,   1,   0,   0 }, /* FCC2 MII TX_EN  */
-	/* PB28 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RX_ER  */
-	/* PB27 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII COL    */
-	/* PB26 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII CRS    */
-	/* PB25 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[3] */
-	/* PB24 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[2] */
-	/* PB23 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[1] */
-	/* PB22 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[0] */
-	/* PB21 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[0] */
-	/* PB20 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[1] */
-	/* PB19 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[2] */
-	/* PB18 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[3] */
-	/* PB17 */ { CONFIG_SYS_FCC3,   1,   0,   0,   0,   0 }, /* FCC3 MII RX_DV  */
-	/* PB16 */ { CONFIG_SYS_FCC3,   1,   0,   0,   0,   0 }, /* FCC3 MII RX_ER  */
-	/* PB15 */ { CONFIG_SYS_FCC3,   1,   0,   1,   0,   0 }, /* FCC3 MII TX_ER  */
-	/* PB14 */ { CONFIG_SYS_FCC3,   1,   0,   1,   0,   0 }, /* FCC3 MII TX_EN  */
-	/* PB13 */ { CONFIG_SYS_FCC3,   1,   0,   0,   0,   0 }, /* FCC3 MII COL    */
-	/* PB12 */ { CONFIG_SYS_FCC3,   1,   0,   0,   0,   0 }, /* FCC3 MII CRS    */
-	/* PB11 */ { CONFIG_SYS_FCC3,   1,   0,   0,   0,   0 }, /* FCC3 MII RxD[3] */
-	/* PB10 */ { CONFIG_SYS_FCC3,   1,   0,   0,   0,   0 }, /* FCC3 MII RxD[2] */
-	/* PB9  */ { CONFIG_SYS_FCC3,   1,   0,   0,   0,   0 }, /* FCC3 MII RxD[1] */
-	/* PB8  */ { CONFIG_SYS_FCC3,   1,   0,   0,   0,   0 }, /* FCC3 MII RxD[0] */
-	/* PB7  */ { CONFIG_SYS_FCC3,   1,   0,   1,   0,   0 }, /* FCC3 MII TxD[0] */
-	/* PB6  */ { CONFIG_SYS_FCC3,   1,   0,   1,   0,   0 }, /* FCC3 MII TxD[1] */
-	/* PB5  */ { CONFIG_SYS_FCC3,   1,   0,   1,   0,   0 }, /* FCC3 MII TxD[2] */
-	/* PB4  */ { CONFIG_SYS_FCC3,   1,   0,   1,   0,   0 }, /* FCC3 MII TxD[3] */
-	/* PB3  */ { 0,          0,   0,   0,   0,   0 }, /* pin doesn't exist */
-	/* PB2  */ { 0,          0,   0,   0,   0,   0 }, /* pin doesn't exist */
-	/* PB1  */ { 0,          0,   0,   0,   0,   0 }, /* pin doesn't exist */
-	/* PB0  */ { 0,          0,   0,   0,   0,   0 }  /* pin doesn't exist */
-    },
-
-    /* Port C */
-    {   /*	      conf      ppar psor pdir podr pdat */
-	/* PC31 */ { 0,          0,   0,   0,   0,   0 }, /* PC31 */
-	/* PC30 */ { 0,          0,   0,   0,   0,   0 }, /* PC30 */
-	/* PC29 */ { 0,          0,   0,   0,   0,   0 }, /* PC29 */
-	/* PC28 */ { 0,          0,   0,   0,   0,   0 }, /* PC28 */
-	/* PC27 */ { 0,          0,   0,   0,   0,   0 }, /* PC27 */
-	/* PC26 */ { 0,          0,   0,   0,   0,   0 }, /* PC26 */
-	/* PC25 */ { 0,          0,   0,   0,   0,   0 }, /* PC25 */
-	/* PC24 */ { 0,          0,   0,   0,   0,   0 }, /* PC24 */
-	/* PC23 */ { 0,          0,   0,   0,   0,   0 }, /* PC23 */
-	/* PC22 */ { 0,          0,   0,   0,   0,   0 }, /* PC22 */
-	/* PC21 */ { 0,          0,   0,   0,   0,   0 }, /* PC21 */
-	/* PC20 */ { 0,          0,   0,   0,   0,   0 }, /* PC20 */
-	/* PC19 */ { 0,          0,   0,   0,   0,   0 }, /* PC19 */
-	/* PC18 */ { CONFIG_SYS_FCC3,   1,   0,   0,   0,   0 }, /* FCC3 MII Rx Clock (CLK14) */
-	/* PC17 */ { 0,          0,   0,   0,   0,   0 }, /* PC17 */
-	/* PC16 */ { CONFIG_SYS_FCC3,   1,   0,   0,   0,   0 }, /* FCC3 MII Tx Clock (CLK16) */
-	/* PC15 */ { 0,          0,   0,   0,   0,   0 }, /* PC15 */
-	/* PC14 */ { 0,          0,   0,   0,   0,   0 }, /* PC14 */
-	/* PC13 */ { 0,          0,   0,   0,   0,   0 }, /* PC13 */
-	/* PC12 */ { 0,          0,   0,   0,   0,   0 }, /* PC12 */
-	/* PC11 */ { 0,          0,   0,   0,   0,   0 }, /* PC11 */
-	/* PC10 */ { 0,          0,   0,   0,   0,   0 }, /* PC10 */
-	/* PC9  */ { 0,          0,   0,   0,   0,   0 }, /* PC9  */
-	/* PC8  */ { 0,          0,   0,   0,   0,   0 }, /* PC8  */
-	/* PC7  */ { 0,          0,   0,   0,   0,   0 }, /* PC7  */
-	/* PC6  */ { 0,          0,   0,   0,   0,   0 }, /* PC6  */
-	/* PC5  */ { 0,          0,   0,   0,   0,   0 }, /* PC5  */
-	/* PC4  */ { 0,          0,   0,   0,   0,   0 }, /* PC4  */
-	/* PC3  */ { 0,          0,   0,   0,   0,   0 }, /* PC3  */
-	/* PC2  */ { 0,          0,   0,   0,   0,   0 }, /* PC2  */
-	/* PC1  */ { 0,          0,   0,   0,   0,   0 }, /* PC1  */
-	/* PC0  */ { 0,          0,   0,   0,   0,   0 }  /* PC0  */
-    },
-
-    /* Port D */
-    {   /*	      conf      ppar psor pdir podr pdat */
-	/* PD31 */ { 0,          0,   0,   0,   0,   0 }, /* PD31 */
-	/* PD30 */ { 0,          0,   0,   0,   0,   0 }, /* PD30 */
-	/* PD29 */ { 0,          0,   0,   0,   0,   0 }, /* PD29 */
-	/* PD28 */ { 0,          0,   0,   0,   0,   0 }, /* PD28 */
-	/* PD27 */ { 0,          0,   0,   0,   0,   0 }, /* PD27 */
-	/* PD26 */ { 0,          0,   0,   0,   0,   0 }, /* PD26 */
-	/* PD25 */ { 0,          0,   0,   0,   0,   0 }, /* PD25 */
-	/* PD24 */ { 0,          0,   0,   0,   0,   0 }, /* PD24 */
-	/* PD23 */ { 0,          0,   0,   0,   0,   0 }, /* PD23 */
-	/* PD22 */ { 0,          0,   0,   0,   0,   0 }, /* PD22 */
-	/* PD21 */ { 0,          0,   0,   0,   0,   0 }, /* PD21 */
-	/* PD20 */ { 0,          0,   0,   0,   0,   0 }, /* PD20 */
-	/* PD19 */ { 0,          0,   0,   0,   0,   0 }, /* PD19 */
-	/* PD18 */ { 0,          1,   1,   0,   0,   0 }, /* SPICLK  */
-	/* PD17 */ { 0,          1,   1,   0,   0,   0 }, /* SPIMOSI */
-	/* PD16 */ { 0,          1,   1,   0,   0,   0 }, /* SPIMISO */
-	/* PD15 */ { 0,          1,   1,   0,   1,   0 }, /* I2C SDA */
-	/* PD14 */ { 0,          1,   1,   0,   1,   0 }, /* I2C SCL */
-	/* PD13 */ { 1,          0,   0,   0,   0,   0 }, /* MII MDIO */
-	/* PD12 */ { 1,          0,   0,   1,   0,   0 }, /* MII MDC  */
-	/* PD11 */ { 0,          0,   0,   0,   0,   0 }, /* PD11 */
-	/* PD10 */ { 0,          0,   0,   0,   0,   0 }, /* PD10 */
-	/* PD9  */ { 1,          1,   0,   1,   0,   0 }, /* SMC1 SMTXD */
-	/* PD8  */ { 1,          1,   0,   0,   0,   0 }, /* SMC1 SMRXD */
-	/* PD7  */ { 0,          0,   0,   0,   0,   0 }, /* PD7 */
-	/* PD6  */ { CONFIG_SYS_FCC3,   0,   0,   1,   0,   1 }, /* MII PHY Reset  */
-	/* PD5  */ { CONFIG_SYS_FCC3,   0,   0,   1,   0,   0 }, /* MII PHY Enable */
-	/* PD4  */ { 0,          0,   0,   0,   0,   0 }, /* PD4 */
-	/* PD3  */ { 0,          0,   0,   0,   0,   0 }, /* pin doesn't exist */
-	/* PD2  */ { 0,          0,   0,   0,   0,   0 }, /* pin doesn't exist */
-	/* PD1  */ { 0,          0,   0,   0,   0,   0 }, /* pin doesn't exist */
-	/* PD0  */ { 0,          0,   0,   0,   0,   0 }  /* pin doesn't exist */
-    }
-};
-
-#define PSPAN_ADDR      0xF0020000
-#define EEPROM_REG      0x408
-#define EEPROM_READ_CMD 0xA000
-#define PSPAN_WRITE(a,v) \
-    *((volatile unsigned long *)(PSPAN_ADDR+(a))) = v; eieio()
-#define PSPAN_READ(a) \
-    *((volatile unsigned long *)(PSPAN_ADDR+(a)))
-
-static int seeprom_read (int addr, uchar * data, int size)
-{
-	ulong val, cmd;
-	int i;
-
-	for (i = 0; i < size; i++) {
-
-		cmd = EEPROM_READ_CMD;
-		cmd |= ((addr + i) << 24) & 0xff000000;
-
-		/* Wait for ACT to authorize write */
-		while ((val = PSPAN_READ (EEPROM_REG)) & 0x80)
-			eieio ();
-
-		/* Write command */
-		PSPAN_WRITE (EEPROM_REG, cmd);
-
-		/* Wait for data to be valid */
-		while ((val = PSPAN_READ (EEPROM_REG)) & 0x80)
-			eieio ();
-		/* Do it twice, first read might be erratic */
-		while ((val = PSPAN_READ (EEPROM_REG)) & 0x80)
-			eieio ();
-
-		/* Read error */
-		if (val & 0x00000040) {
-			return -1;
-		} else {
-			data[i] = (val >> 16) & 0xff;
-		}
-	}
-	return 0;
-}
-
-/***************************************************************
- * We take some basic Hardware Configuration Parameter from the
- * Serial EEPROM conected to the PSpan bridge. We keep it as
- * simple as possible.
- */
-#ifdef DEBUG
-static int hwc_flash_size (void)
-{
-	uchar byte;
-
-	if (!seeprom_read (0x40, &byte, sizeof (byte))) {
-		switch ((byte >> 2) & 0x3) {
-		case 0x1:
-			return 0x0400000;
-			break;
-		case 0x2:
-			return 0x0800000;
-			break;
-		case 0x3:
-			return 0x1000000;
-		default:
-			return 0x0100000;
-		}
-	}
-	return -1;
-}
-
-static int hwc_local_sdram_size (void)
-{
-	uchar byte;
-
-	if (!seeprom_read (0x40, &byte, sizeof (byte))) {
-		switch ((byte & 0x03)) {
-		case 0x1:
-			return 0x0800000;
-		case 0x2:
-			return 0x1000000;
-		default:
-			return 0;			/* not present */
-		}
-	}
-	return -1;
-}
-#endif	/* DEBUG */
-
-static int hwc_main_sdram_size (void)
-{
-	uchar byte;
-
-	if (!seeprom_read (0x41, &byte, sizeof (byte))) {
-		return 0x1000000 << ((byte >> 5) & 0x7);
-	}
-	return -1;
-}
-
-static int hwc_serial_number (void)
-{
-	int sn = -1;
-
-	if (!seeprom_read (0xa0, (uchar *) &sn, sizeof (sn))) {
-		sn = cpu_to_le32 (sn);
-	}
-	return sn;
-}
-
-static int hwc_mac_address (char *str)
-{
-	char mac[6];
-
-	if (!seeprom_read (0xb0, (uchar *)mac, sizeof (mac))) {
-		sprintf (str, "%02X:%02X:%02X:%02X:%02X:%02X",
-				 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
-	} else {
-		strcpy (str, "ERROR");
-		return -1;
-	}
-	return 0;
-}
-
-static int hwc_manufact_date (char *str)
-{
-	uchar byte;
-	int value;
-
-	if (seeprom_read (0x92, &byte, sizeof (byte)))
-		goto out;
-	value = byte;
-	if (seeprom_read (0x93, &byte, sizeof (byte)))
-		goto out;
-	value += byte << 8;
-	sprintf (str, "%02d/%02d/%04d",
-			 value & 0x1F, (value >> 5) & 0xF,
-			 1980 + ((value >> 9) & 0x1FF));
-	return 0;
-
-out:
-	strcpy (str, "ERROR");
-	return -1;
-}
-
-static int hwc_board_type (char **str)
-{
-	ushort id = 0;
-
-	if (seeprom_read (7, (uchar *) & id, sizeof (id)) == 0) {
-		switch (id) {
-		case 0x9080:
-			*str = "4532-002";
-			break;
-		case 0x9081:
-			*str = "4532-001";
-			break;
-		case 0x9082:
-			*str = "4532-000";
-			break;
-		default:
-			*str = "Unknown";
-		}
-	} else {
-		*str = "Unknown";
-	}
-
-	return id;
-}
-
-phys_size_t initdram (int board_type)
-{
-	long maxsize = hwc_main_sdram_size();
-
-#if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SYS_USE_FIRMWARE)
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile memctl8260_t *memctl = &immap->im_memctl;
-	volatile uchar *base;
-	int i;
-
-	immap->im_siu_conf.sc_ppc_acr  = 0x00000026;
-	immap->im_siu_conf.sc_ppc_alrh = 0x01276345;
-	immap->im_siu_conf.sc_ppc_alrl = 0x89ABCDEF;
-	immap->im_siu_conf.sc_lcl_acr  = 0x00000000;
-	immap->im_siu_conf.sc_lcl_alrh = 0x01234567;
-	immap->im_siu_conf.sc_lcl_alrl = 0x89ABCDEF;
-	immap->im_siu_conf.sc_tescr1   = 0x00004000;
-	immap->im_siu_conf.sc_ltescr1  = 0x00004000;
-
-	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
-
-	/* Initialise 60x bus SDRAM */
-	base = (uchar *)(CONFIG_SYS_SDRAM_BASE | 0x110);
-	memctl->memc_psrt  = CONFIG_SYS_PSRT;
-	memctl->memc_or1   = CONFIG_SYS_60x_OR;
-	memctl->memc_br1   = CONFIG_SYS_SDRAM_BASE | CONFIG_SYS_60x_BR;
-
-	memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x28000000;
-	*base = 0xFF;
-	memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x08000000;
-	for (i = 0; i < 8; i++)
-		*base = 0xFF;
-	memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x18000000;
-	*base = 0xFF;
-	memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x40000000;
-
-	/* Initialise local bus SDRAM */
-	base = (uchar *)CONFIG_SYS_LSDRAM_BASE;
-	memctl->memc_lsrt  = CONFIG_SYS_LSRT;
-	memctl->memc_or2   = CONFIG_SYS_LOC_OR;
-	memctl->memc_br2   = CONFIG_SYS_LSDRAM_BASE | CONFIG_SYS_LOC_BR;
-
-	memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x28000000;
-	*base = 0xFF;
-	memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x08000000;
-	for (i = 0; i < 8; i++)
-		*base = 0xFF;
-	memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x18000000;
-	*base = 0xFF;
-	memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x40000000;
-
-	/* We must be able to test a location outsize the maximum legal size
-	 * to find out THAT we are outside; but this address still has to be
-	 * mapped by the controller. That means, that the initial mapping has
-	 * to be (at least) twice as large as the maximum expected size.
-	 */
-	maxsize = (~(memctl->memc_or1 & BRx_BA_MSK) + 1) / 2;
-
-	maxsize = get_ram_size((long *)(memctl->memc_br1 & BRx_BA_MSK), maxsize);
-
-	memctl->memc_or1 |= ~(maxsize - 1);
-
-	if (maxsize != hwc_main_sdram_size())
-		puts("Oops: memory test has not found all memory!\n");
-#endif /* !CONFIG_SYS_RAMBOOT && !CONFIG_SYS_USE_FIRMWARE */
-
-	/* Return total RAM size (size of 60x SDRAM) */
-	return maxsize;
-}
-
-int checkboard(void)
-{
-	char string[32], *id;
-
-	hwc_manufact_date(string);
-	hwc_board_type(&id);
-	printf("Board: Interphase iSPAN %s (#%d %s)\n",
-	       id, hwc_serial_number(), string);
-#ifdef DEBUG
-	printf("Manufacturing date: %s\n", string);
-	printf("Serial number     : %d\n", hwc_serial_number());
-	printf("FLASH size        : %d MB\n", hwc_flash_size() >> 20);
-	printf("Main SDRAM size   : %d MB\n", hwc_main_sdram_size() >> 20);
-	printf("Local SDRAM size  : %d MB\n", hwc_local_sdram_size() >> 20);
-	hwc_mac_address(string);
-	printf("MAC address       : %s\n", string);
-#endif
-	return 0;
-}
-
-int misc_init_r(void)
-{
-	char *s, str[32];
-	int num;
-
-	if ((s = getenv("serial#")) == NULL &&
-	    (num = hwc_serial_number()) != -1) {
-		sprintf(str, "%06d", num);
-		setenv("serial#", str);
-	}
-	if ((s = getenv("ethaddr")) == NULL && hwc_mac_address(str) == 0) {
-		setenv("ethaddr", str);
-	}
-
-	return 0;
-}
diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c
index f941e44e83..2ddb3da38f 100644
--- a/board/keymile/common/common.c
+++ b/board/keymile/common/common.c
@@ -12,7 +12,7 @@
 #include <ioports.h>
 #include <command.h>
 #include <malloc.h>
-#include <hush.h>
+#include <cli_hush.h>
 #include <net.h>
 #include <netdev.h>
 #include <asm/io.h>
diff --git a/board/keymile/common/ivm.c b/board/keymile/common/ivm.c
index f0e91bbdfe..b6b19ccb8e 100644
--- a/board/keymile/common/ivm.c
+++ b/board/keymile/common/ivm.c
@@ -6,7 +6,7 @@
  */
 
 #include <common.h>
-#include <hush.h>
+#include <cli_hush.h>
 #include <i2c.h>
 #include "common.h"
 
@@ -120,7 +120,7 @@ static int ivm_findinventorystring(int type,
 
 	/* Look for the requested number of CR. */
 	while ((cr != nr) && (addr < INVENTORYDATASIZE)) {
-		if ((buf[addr] == '\r'))
+		if (buf[addr] == '\r')
 			cr++;
 		addr++;
 	}
diff --git a/board/matrix_vision/mvblm7/Makefile b/board/matrix_vision/mvblm7/Makefile
index 9ed2837a78..caa6cfd34c 100644
--- a/board/matrix_vision/mvblm7/Makefile
+++ b/board/matrix_vision/mvblm7/Makefile
@@ -8,10 +8,6 @@ obj-y	:= mvblm7.o pci.o fpga.o
 
 extra-y := bootscript.img
 
-quiet_cmd_mkimage = MKIMAGE $@
-cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \
-        $(if $(KBUILD_VERBOSE:1=), >/dev/null)
-
 MKIMAGEFLAGS_bootscript.image := -T script -C none -n M7_script
 
 $(obj)/bootscript.img: $(src)/bootscript
diff --git a/board/matrix_vision/mvsmr/Makefile b/board/matrix_vision/mvsmr/Makefile
index a9c794e21a..cef1b7664c 100644
--- a/board/matrix_vision/mvsmr/Makefile
+++ b/board/matrix_vision/mvsmr/Makefile
@@ -12,10 +12,6 @@ obj-y	:= mvsmr.o fpga.o
 
 extra-y := bootscript.img
 
-quiet_cmd_mkimage = MKIMAGE $@
-cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \
-        $(if $(KBUILD_VERBOSE:1=), >/dev/null)
-
 MKIMAGEFLAGS_bootscript.image := -T script -C none -n mvSMR_Script
 
 $(obj)/bootscript.img: $(src)/bootscript
diff --git a/board/mcc200/auto_update.c b/board/mcc200/auto_update.c
index 2f622b0846..43173ce060 100644
--- a/board/mcc200/auto_update.c
+++ b/board/mcc200/auto_update.c
@@ -12,11 +12,6 @@
 #include <usb.h>
 #include <part.h>
 
-#ifdef CONFIG_SYS_HUSH_PARSER
-#include <hush.h>
-#endif
-
-
 #ifdef CONFIG_AUTO_UPDATE
 
 #ifndef CONFIG_USB_OHCI
@@ -247,7 +242,7 @@ int au_do_update(int idx, long sz)
 		/* parse_string_outer() runs off the end. */
 		addr[image_get_data_size (hdr)] = 0;
 		addr += 8;
-		parse_string_outer(addr, FLAG_PARSE_SEMICOLON);
+		run_command_list(addr, -1, 0);
 		return 0;
 	}
 
diff --git a/board/pcs440ep/pcs440ep.c b/board/pcs440ep/pcs440ep.c
index f90e809d15..267c001435 100644
--- a/board/pcs440ep/pcs440ep.c
+++ b/board/pcs440ep/pcs440ep.c
@@ -13,7 +13,7 @@
 #include <asm/processor.h>
 #include <spd_sdram.h>
 #include <status_led.h>
-#include <sha1.h>
+#include <u-boot/sha1.h>
 #include <asm/io.h>
 #include <net.h>
 #include <ata.h>
diff --git a/board/psyent/common/AMDLV065D.c b/board/psyent/common/AMDLV065D.c
index 409a7a82fb..64cb97029e 100644
--- a/board/psyent/common/AMDLV065D.c
+++ b/board/psyent/common/AMDLV065D.c
@@ -7,11 +7,7 @@
 
 
 #include <common.h>
-#if defined(CONFIG_NIOS)
-#include <nios.h>
-#else
 #include <asm/io.h>
-#endif
 
 #define SECTSZ		(64 * 1024)
 flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
diff --git a/board/quad100hd/Makefile b/board/quad100hd/Makefile
deleted file mode 100644
index b65e5ad471..0000000000
--- a/board/quad100hd/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2007
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	= quad100hd.o nand.o
diff --git a/board/quad100hd/nand.c b/board/quad100hd/nand.c
deleted file mode 100644
index 47bbb6b262..0000000000
--- a/board/quad100hd/nand.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * (C) Copyright 2008
- * Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <config.h>
-#if defined(CONFIG_CMD_NAND)
-#include <asm/ppc4xx-gpio.h>
-#include <asm/io.h>
-#include <nand.h>
-
-/*
- *	hardware specific access to control-lines
- */
-static void quad100hd_hwcontrol(struct mtd_info *mtd,
-				int cmd, unsigned int ctrl)
-{
-	struct nand_chip *this = mtd->priv;
-
-	if (ctrl & NAND_CTRL_CHANGE) {
-		gpio_write_bit(CONFIG_SYS_NAND_CLE, !!(ctrl & NAND_CLE));
-		gpio_write_bit(CONFIG_SYS_NAND_ALE, !!(ctrl & NAND_ALE));
-		gpio_write_bit(CONFIG_SYS_NAND_CE, !(ctrl & NAND_NCE));
-	}
-
-	if (cmd != NAND_CMD_NONE)
-		writeb(cmd, this->IO_ADDR_W);
-}
-
-static int quad100hd_nand_ready(struct mtd_info *mtd)
-{
-	return gpio_read_in_bit(CONFIG_SYS_NAND_RDY);
-}
-
-/*
- * Main initialization routine
- */
-int board_nand_init(struct nand_chip *nand)
-{
-	/* Set address of hardware control function */
-	nand->cmd_ctrl = quad100hd_hwcontrol;
-	nand->dev_ready = quad100hd_nand_ready;
-	nand->ecc.mode = NAND_ECC_SOFT;
-	/* 15 us command delay time */
-	nand->chip_delay =  20;
-
-	/* Return happy */
-	return 0;
-}
-#endif /* CONFIG_CMD_NAND */
diff --git a/board/quad100hd/quad100hd.c b/board/quad100hd/quad100hd.c
deleted file mode 100644
index bb14ca7056..0000000000
--- a/board/quad100hd/quad100hd.c
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * (C) Copyright 2008
- * Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de.
- *
- * Based in part on board/icecube/icecube.c from PPCBoot
- * (C) Copyright 2003 Intrinsyc Software
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <malloc.h>
-#include <environment.h>
-#include <logbuff.h>
-#include <post.h>
-
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/ppc4xx-gpio.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
-	/* taken from PPCBoot */
-	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
-	mtdcr(UIC0ER, 0x00000000);	/* disable all ints */
-	mtdcr(UIC0CR, 0x00000000);
-	mtdcr(UIC0PR, 0xFFFF7FFE);	/* set int polarities */
-	mtdcr(UIC0TR, 0x00000000);	/* set int trigger levels */
-	mtdcr(UIC0SR, 0xFFFFFFFF);	/* clear all ints */
-	mtdcr(UIC0VCR, 0x00000001);	/* set vect base=0,INT0 highest priority */
-
-	mtdcr(CPC0_SRR, 0x00040000);   /* Hold PCI bridge in reset */
-
-	return 0;
-}
-
-/*
- * Check Board Identity:
- */
-int checkboard(void)
-{
-	char buf[64];
-	int i = getenv_f("serial#", buf, sizeof(buf));
-#ifdef DISPLAY_BOARD_INFO
-	sys_info_t sysinfo;
-#endif
-
-	puts("Board: Quad100hd");
-
-	if (i > 0) {
-		puts(", serial# ");
-		puts(buf);
-	}
-	putc('\n');
-
-#ifdef DISPLAY_BOARD_INFO
-	/* taken from ppcboot */
-	get_sys_info(&sysinfo);
-
-	printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz);
-	printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
-	printf("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
-	printf("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
-	printf("\tEPB: %lu MHz\n", sysinfo.freqPLB / (sysinfo.pllExtBusDiv *
-		1000000));
-	printf("\tPCI: %lu MHz\n", sysinfo.freqPCI / 1000000);
-#endif
-
-	return 0;
-}
diff --git a/board/rattler/Makefile b/board/rattler/Makefile
deleted file mode 100644
index 9de89c8096..0000000000
--- a/board/rattler/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= rattler.o
diff --git a/board/rattler/rattler.c b/board/rattler/rattler.c
deleted file mode 100644
index f7fb349f71..0000000000
--- a/board/rattler/rattler.c
+++ /dev/null
@@ -1,215 +0,0 @@
-/*
- * Copyright (C) 2004 Arabella Software Ltd.
- * Yuli Barcohen <yuli@arabellasw.com>
- *
- * Support for Analogue&Micro Rattler boards family.
- * Tested on Rattler8248.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc8260.h>
-#include <ioports.h>
-
-/*
- * I/O Port configuration table
- *
- * if conf is 1, then that port pin will be configured at boot time
- * according to the five values podr/pdir/ppar/psor/pdat for that entry
- */
-
-#define CONFIG_SYS_FCC1 (CONFIG_ETHER_INDEX == 1)
-#define CONFIG_SYS_FCC2 (CONFIG_ETHER_INDEX == 2)
-
-const iop_conf_t iop_conf_tab[4][32] = {
-
-    /* Port A */
-    {	/*	      conf      ppar psor pdir podr pdat */
-	/* PA31 */ { CONFIG_SYS_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII COL    */
-	/* PA30 */ { CONFIG_SYS_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII CRS    */
-	/* PA29 */ { CONFIG_SYS_FCC1,   1,   1,   1,   0,   0 }, /* FCC1 MII TX_ER  */
-	/* PA28 */ { CONFIG_SYS_FCC1,   1,   1,   1,   0,   0 }, /* FCC1 MII TX_EN  */
-	/* PA27 */ { CONFIG_SYS_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII RX_DV  */
-	/* PA26 */ { CONFIG_SYS_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII RX_ER  */
-	/* PA25 */ { 0,          0,   0,   0,   0,   0 }, /* PA25            */
-	/* PA24 */ { 0,          0,   0,   0,   0,   0 }, /* PA24            */
-	/* PA23 */ { 0,          0,   0,   0,   0,   0 }, /* PA23            */
-	/* PA22 */ { 1,          0,   0,   1,   0,   1 }, /* Eth PHYs reset  */
-	/* PA21 */ { CONFIG_SYS_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[3] */
-	/* PA20 */ { CONFIG_SYS_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[2] */
-	/* PA19 */ { CONFIG_SYS_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[1] */
-	/* PA18 */ { CONFIG_SYS_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[0] */
-	/* PA17 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[0] */
-	/* PA16 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[1] */
-	/* PA15 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[2] */
-	/* PA14 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[3] */
-	/* PA13 */ { 0,          0,   0,   0,   0,   0 }, /* PA13            */
-	/* PA12 */ { 0,          0,   0,   0,   0,   0 }, /* PA12            */
-	/* PA11 */ { 0,          0,   0,   0,   0,   0 }, /* PA11            */
-	/* PA10 */ { 0,          0,   0,   0,   0,   0 }, /* PA10            */
-	/* PA9  */ { 0,          1,   0,   1,   0,   0 }, /* SMC2 TxD        */
-	/* PA8  */ { 0,          1,   0,   0,   0,   0 }, /* SMC2 RxD        */
-	/* PA7  */ { 0,          0,   0,   0,   0,   0 }, /* PA7             */
-	/* PA6  */ { 0,          0,   0,   0,   0,   0 }, /* PA6             */
-	/* PA5  */ { 0,          0,   0,   0,   0,   0 }, /* PA5             */
-	/* PA4  */ { 0,          0,   0,   0,   0,   0 }, /* PA4             */
-	/* PA3  */ { 0,          0,   0,   0,   0,   0 }, /* PA3             */
-	/* PA2  */ { 0,          0,   0,   0,   0,   0 }, /* PA2             */
-	/* PA1  */ { 0,          0,   0,   0,   0,   0 }, /* PA1             */
-	/* PA0  */ { 0,          0,   0,   0,   0,   0 }  /* PA0             */
-    },
-
-    /* Port B */
-    {   /*	      conf      ppar psor pdir podr pdat */
-	/* PB31 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TX_ER  */
-	/* PB30 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RX_DV  */
-	/* PB29 */ { CONFIG_SYS_FCC2,   1,   1,   1,   0,   0 }, /* FCC2 MII TX_EN  */
-	/* PB28 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RX_ER  */
-	/* PB27 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII COL    */
-	/* PB26 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII CRS    */
-	/* PB25 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[3] */
-	/* PB24 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[2] */
-	/* PB23 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[1] */
-	/* PB22 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[0] */
-	/* PB21 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[0] */
-	/* PB20 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[1] */
-	/* PB19 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[2] */
-	/* PB18 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[3] */
-	/* PB17 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
-	/* PB16 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
-	/* PB15 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
-	/* PB14 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
-	/* PB13 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
-	/* PB12 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
-	/* PB11 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
-	/* PB10 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
-	/* PB9  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
-	/* PB8  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
-	/* PB7  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
-	/* PB6  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
-	/* PB5  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
-	/* PB4  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
-	/* PB3  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
-	/* PB2  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
-	/* PB1  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
-	/* PB0  */ { 0,          0,   0,   0,   0,   0 }  /* non-existent    */
-    },
-
-    /* Port C */
-    {   /*	      conf      ppar psor pdir podr pdat */
-	/* PC31 */ { 0,          0,   0,   0,   0,   0 }, /* PC31            */
-	/* PC30 */ { 0,          0,   0,   0,   0,   0 }, /* PC30            */
-	/* PC29 */ { 0,          0,   0,   0,   0,   0 }, /* PC29            */
-	/* PC28 */ { 0,          0,   0,   0,   0,   0 }, /* PC28            */
-	/* PC27 */ { 0,          0,   0,   0,   0,   0 }, /* PC27            */
-	/* PC26 */ { 0,          0,   0,   0,   0,   0 }, /* PC26            */
-	/* PC25 */ { 0,          0,   0,   0,   0,   0 }, /* PC25            */
-	/* PC24 */ { 0,          0,   0,   0,   0,   0 }, /* PC24            */
-	/* PC23 */ { 0,          0,   0,   0,   0,   0 }, /* PC23            */
-	/* PC22 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 TxClk (CLK10) */
-	/* PC21 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 RxClk (CLK11) */
-	/* PC20 */ { 0,          0,   0,   0,   0,   0 }, /* PC20            */
-	/* PC19 */ { 0,          0,   0,   0,   0,   0 }, /* PC19            */
-	/* PC18 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 TxClk (CLK14) */
-	/* PC17 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 RxClk (CLK15) */
-	/* PC16 */ { 0,          0,   0,   0,   0,   0 }, /* PC16            */
-	/* PC15 */ { 0,          0,   0,   0,   0,   0 }, /* PC15            */
-	/* PC14 */ { 0,          0,   0,   0,   0,   0 }, /* PC14            */
-	/* PC13 */ { 0,          0,   0,   0,   0,   0 }, /* PC13            */
-	/* PC12 */ { 0,          0,   0,   0,   0,   0 }, /* PC12            */
-	/* PC11 */ { 0,          0,   0,   0,   0,   0 }, /* PC11            */
-	/* PC10 */ { 0,          0,   0,   0,   0,   0 }, /* PC10            */
-	/* PC9  */ { 1,          0,   0,   1,   0,   1 }, /* MDIO            */
-	/* PC8  */ { 1,          0,   0,   1,   0,   1 }, /* MDC             */
-	/* PC7  */ { 0,          0,   0,   0,   0,   0 }, /* PC7             */
-	/* PC6  */ { 0,          0,   0,   0,   0,   0 }, /* PC6             */
-	/* PC5  */ { 1,          1,   0,   1,   0,   0 }, /* SMC1 TxD        */
-	/* PC4  */ { 1,          1,   0,   0,   0,   0 }, /* SMC1 RxD        */
-	/* PC3  */ { 0,          0,   0,   0,   0,   0 }, /* PC3             */
-	/* PC2  */ { 0,          0,   0,   0,   0,   0 }, /* PC2             */
-	/* PC1  */ { 0,          0,   0,   0,   0,   0 }, /* PC1             */
-	/* PC0  */ { 0,          0,   0,   0,   0,   0 }, /* PC0             */
-    },
-
-    /* Port D */
-    {   /*	      conf      ppar psor pdir podr pdat */
-	/* PD31 */ { 1,          1,   0,   0,   0,   0 }, /* SCC1 RxD        */
-	/* PD30 */ { 1,          1,   1,   1,   0,   0 }, /* SCC1 TxD        */
-	/* PD29 */ { 0,          0,   0,   0,   0,   0 }, /* PD29            */
-	/* PD28 */ { 0,          0,   0,   0,   0,   0 }, /* PD28            */
-	/* PD27 */ { 0,          0,   0,   0,   0,   0 }, /* PD27            */
-	/* PD26 */ { 0,          0,   0,   0,   0,   0 }, /* PD26            */
-	/* PD25 */ { 0,          0,   0,   0,   0,   0 }, /* PD25            */
-	/* PD24 */ { 0,          0,   0,   0,   0,   0 }, /* PD24            */
-	/* PD23 */ { 0,          0,   0,   0,   0,   0 }, /* PD23            */
-	/* PD22 */ { 0,          0,   0,   0,   0,   0 }, /* PD22            */
-	/* PD21 */ { 0,          0,   0,   0,   0,   0 }, /* PD21            */
-	/* PD20 */ { 0,          0,   0,   0,   0,   0 }, /* PD20            */
-	/* PD19 */ { 0,          0,   0,   0,   0,   0 }, /* PD19            */
-	/* PD18 */ { 0,          0,   0,   0,   0,   0 }, /* PD18            */
-	/* PD17 */ { 0,          0,   0,   0,   0,   0 }, /* PD17            */
-	/* PD16 */ { 0,          0,   0,   0,   0,   0 }, /* PD16            */
-	/* PD15 */ { 0,          0,   0,   0,   0,   0 }, /* PD15            */
-	/* PD14 */ { 0,          0,   0,   0,   0,   0 }, /* PD14            */
-	/* PD13 */ { 0,          0,   0,   0,   0,   0 }, /* PD13            */
-	/* PD12 */ { 0,          0,   0,   0,   0,   0 }, /* PD12            */
-	/* PD11 */ { 0,          0,   0,   0,   0,   0 }, /* PD11            */
-	/* PD10 */ { 0,          0,   0,   0,   0,   0 }, /* PD10            */
-	/* PD9  */ { 0,          0,   0,   0,   0,   0 }, /* PD9             */
-	/* PD8  */ { 0,          0,   0,   0,   0,   0 }, /* PD8             */
-	/* PD7  */ { 0,          0,   0,   0,   0,   0 }, /* PD7             */
-	/* PD6  */ { 0,          0,   0,   0,   0,   0 }, /* PD6             */
-	/* PD5  */ { 0,          0,   0,   0,   0,   0 }, /* PD5             */
-	/* PD4  */ { 0,          0,   0,   0,   0,   0 }, /* PD4             */
-	/* PD3  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
-	/* PD2  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
-	/* PD1  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
-	/* PD0  */ { 0,          0,   0,   0,   0,   0 }  /* non-existent    */
-    }
-};
-
-phys_size_t initdram(int board_type)
-{
-	long int msize = CONFIG_SYS_SDRAM_SIZE;
-
-#ifndef CONFIG_SYS_RAMBOOT
-	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
-	volatile memctl8260_t *memctl = &immap->im_memctl;
-	vu_char *ramaddr = (vu_char *)CONFIG_SYS_SDRAM_BASE;
-	uchar c = 0xFF;
-	uint psdmr = CONFIG_SYS_PSDMR;
-	int i;
-
-	immap->im_siu_conf.sc_ppc_acr  = 0x02;
-	immap->im_siu_conf.sc_ppc_alrh = 0x30126745;
-	immap->im_siu_conf.sc_tescr1   = 0x00004000;
-
-	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
-
-	/* Initialise 60x bus SDRAM */
-	memctl->memc_psrt = CONFIG_SYS_PSRT;
-	memctl->memc_or1  = CONFIG_SYS_SDRAM_OR;
-	memctl->memc_br1  = CONFIG_SYS_SDRAM_BR;
-	memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; /* Precharge all banks */
-	*ramaddr = c;
-	memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */
-	for (i = 0; i < 8; i++)
-		*ramaddr = c;
-	memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;  /* Mode Register write */
-	*ramaddr = c;
-	memctl->memc_psdmr = psdmr | PSDMR_RFEN;    /* Refresh enable */
-	*ramaddr = c;
-#endif /* !CONFIG_SYS_RAMBOOT */
-
-	/* Return total 60x bus SDRAM size */
-	return msize * 1024 * 1024;
-}
-
-int checkboard(void)
-{
-	vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR;
-
-	printf("Board: Rattler Rev. %c\n", bcsr[0x20] + 0x40);
-	return 0;
-}
diff --git a/board/ronetix/pm9261/pm9261.c b/board/ronetix/pm9261/pm9261.c
index ec3ac89593..1f7679a240 100644
--- a/board/ronetix/pm9261/pm9261.c
+++ b/board/ronetix/pm9261/pm9261.c
@@ -117,20 +117,20 @@ static void pm9261_dm9000_hw_init(void)
 
 #ifdef CONFIG_LCD
 vidinfo_t panel_info = {
-	vl_col:		240,
-	vl_row:		320,
-	vl_clk:		4965000,
-	vl_sync:	ATMEL_LCDC_INVLINE_INVERTED |
-			ATMEL_LCDC_INVFRAME_INVERTED,
-	vl_bpix:	3,
-	vl_tft:		1,
-	vl_hsync_len:	5,
-	vl_left_margin:	1,
-	vl_right_margin:33,
-	vl_vsync_len:	1,
-	vl_upper_margin:1,
-	vl_lower_margin:0,
-	mmio:		ATMEL_BASE_LCDC,
+	.vl_col =		240,
+	.vl_row =		320,
+	.vl_clk =		4965000,
+	.vl_sync =		ATMEL_LCDC_INVLINE_INVERTED |
+				ATMEL_LCDC_INVFRAME_INVERTED,
+	.vl_bpix =		3,
+	.vl_tft =		1,
+	.vl_hsync_len =		5,
+	.vl_left_margin =	1,
+	.vl_right_margin =	33,
+	.vl_vsync_len =		1,
+	.vl_upper_margin =	1,
+	.vl_lower_margin =	0,
+	.mmio =			ATMEL_BASE_LCDC,
 };
 
 void lcd_enable(void)
diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c
index 3aaffa803c..1b00f08835 100644
--- a/board/ronetix/pm9263/pm9263.c
+++ b/board/ronetix/pm9263/pm9263.c
@@ -115,20 +115,20 @@ static void pm9263_macb_hw_init(void)
 
 #ifdef CONFIG_LCD
 vidinfo_t panel_info = {
-	vl_col:		240,
-	vl_row:		320,
-	vl_clk:		4965000,
-	vl_sync:	ATMEL_LCDC_INVLINE_INVERTED |
-			ATMEL_LCDC_INVFRAME_INVERTED,
-	vl_bpix:	3,
-	vl_tft:		1,
-	vl_hsync_len:	5,
-	vl_left_margin:	1,
-	vl_right_margin:33,
-	vl_vsync_len:	1,
-	vl_upper_margin:1,
-	vl_lower_margin:0,
-	mmio:		ATMEL_BASE_LCDC,
+	.vl_col =		240,
+	.vl_row =		320,
+	.vl_clk =		4965000,
+	.vl_sync =		ATMEL_LCDC_INVLINE_INVERTED |
+					ATMEL_LCDC_INVFRAME_INVERTED,
+	.vl_bpix =		3,
+	.vl_tft =		1,
+	.vl_hsync_len =		5,
+	.vl_left_margin =	1,
+	.vl_right_margin =	33,
+	.vl_vsync_len =		1,
+	.vl_upper_margin =	1,
+	.vl_lower_margin =	0,
+	.mmio =			ATMEL_BASE_LCDC,
 };
 
 void lcd_enable(void)
diff --git a/board/sheldon/simpc8313/Makefile b/board/sheldon/simpc8313/Makefile
deleted file mode 100644
index a824c41d9c..0000000000
--- a/board/sheldon/simpc8313/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= simpc8313.o sdram.o
diff --git a/board/sheldon/simpc8313/README.simpc8313 b/board/sheldon/simpc8313/README.simpc8313
deleted file mode 100644
index b362c6aeea..0000000000
--- a/board/sheldon/simpc8313/README.simpc8313
+++ /dev/null
@@ -1,80 +0,0 @@
-Sheldon Instruments SIMPC8313 Board
------------------------------------------
-
-1.	Board Switches and Jumpers
-
-	S2 is used to set CFG_RESET_SOURCE.
-
-	To boot the image in Large page NAND flash, use these DIP
-	switch settings for S2:
-
-	+----------+ ON
-	| * * **** |
-	|  * *     |
-	+----------+
-	  12345678
-
-	To boot the image in Small page NAND flash, use these DIP
-	switch settings for S2:
-
-	+----------+ ON
-	| *** **** |
-	|    *     |
-	+----------+
-	  12345678
-	(where the '*' indicates the position of the tab of the switch.)
-
-2.	Memory Map
-	The memory map looks like this:
-
-	0x0000_0000	0x1fff_ffff	DDR			512M
-	0x8000_0000	0x8fff_ffff	PCI MEM			256M
-	0x9000_0000	0x9fff_ffff	PCI_MMIO		256M
-	0xe000_0000	0xe00f_ffff	IMMR			1M
-	0xe200_0000	0xe20f_ffff	PCI IO			16M
-	0xe280_0000	0xe280_7fff	NAND FLASH (CS0)	32K
-	or
-	0xe280_0000	0xe281_ffff	NAND FLASH (CS0)	128K
-	0xff00_0000	0xff00_7fff	FPGA (CS1)		1M
-
-3.	Compilation
-
-	Assuming you're using BASH (or similar) as your shell:
-
-	export CROSS_COMPILE=your-cross-compiler-prefix-
-	make distclean
-	make SIMPC8313_LP_config
-	(or make SIMPC8313_SP_config, depending on the page size
-	of your NAND flash)
-	make
-
-4.	Downloading and Flashing Images
-
-4.1	Reflash U-boot Image using U-boot
-
-	=>run update_uboot
-
-	You may want to try
-	=>tftp $loadaddr $uboot
-	first, to make sure that the TFTP load will succeed before it
-	goes ahead and wipes out your current firmware.  And of course,
-	if the new u-boot doesn't boot, you can plug the board into
-	your PCI slot and with the supplied driver and sample app
-	you can reburn a working u-boot.
-
-4.2	Downloading and Booting Linux Kernel
-
-	Ensure that all networking-related environment variables are set
-	properly (including ipaddr, serverip, gatewayip (if needed),
-	netmask, ethaddr, eth1addr, fdtfile, and bootfile).
-
-	=>tftp $loadaddr uImage
-	=>nand write $loadaddr kernel $filesize
-	=>tftp $loadaddr $fdtfile
-	=>nand write $loadaddr 7e0000 1800
-
-	=>boot
-
-5	Notes
-
-	The console baudrate for SIMPC8313 is 115200bps.
diff --git a/board/sheldon/simpc8313/sdram.c b/board/sheldon/simpc8313/sdram.c
deleted file mode 100644
index 7c12fe851c..0000000000
--- a/board/sheldon/simpc8313/sdram.c
+++ /dev/null
@@ -1,177 +0,0 @@
-/*
- * Copyright (C) Freescale Semiconductor, Inc. 2006-2007
- * Copyright (C) Sheldon Instruments, Inc. 2008
- *
- * Author: Ron Madrid <info@sheldoninst.com>
- *
- * (C) Copyright 2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc83xx.h>
-#include <spd_sdram.h>
-#include <asm/bitops.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static long fixed_sdram(void);
-
-#if defined(CONFIG_NAND_SPL)
-void si_wait_i2c(void)
-{
-	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-
-	while (!(__raw_readb(&im->i2c[0].sr) & 0x02))
-		;
-
-	__raw_writeb(0x00, &im->i2c[0].sr);
-
-	sync();
-
-	return;
-}
-
-void si_read_i2c(u32 lbyte, int count, u8 *buffer)
-{
-	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	u32 i;
-	u8 chip = 0x50 << 1; /* boot sequencer I2C */
-	u32 ubyte = (lbyte & 0xff00) >> 8;
-
-	lbyte &= 0xff;
-
-	/*
-	 * Set up controller
-	 */
-	__raw_writeb(0x3f, &im->i2c[0].fdr);
-	__raw_writeb(0x00, &im->i2c[0].adr);
-	__raw_writeb(0x00, &im->i2c[0].sr);
-	__raw_writeb(0x00, &im->i2c[0].dr);
-
-	while (__raw_readb(&im->i2c[0].sr) & 0x20)
-		;
-
-	/*
-	 * Writing address to device
-	 */
-	__raw_writeb(0xb0, &im->i2c[0].cr);
-	sync();
-	__raw_writeb(chip, &im->i2c[0].dr);
-	si_wait_i2c();
-
-	__raw_writeb(0xb0, &im->i2c[0].cr);
-	sync();
-	__raw_writeb(ubyte, &im->i2c[0].dr);
-	si_wait_i2c();
-
-	__raw_writeb(lbyte, &im->i2c[0].dr);
-	si_wait_i2c();
-
-	__raw_writeb(0xb4, &im->i2c[0].cr);
-	sync();
-	__raw_writeb(chip + 1, &im->i2c[0].dr);
-	si_wait_i2c();
-
-	__raw_writeb(0xa0, &im->i2c[0].cr);
-	sync();
-
-	/*
-	 * Dummy read
-	 */
-	__raw_readb(&im->i2c[0].dr);
-
-	si_wait_i2c();
-
-	/*
-	 * Read actual data
-	 */
-	for (i = 0; i < count; i++)
-	{
-		if (i == (count - 2))	/* Reached next to last byte, No ACK */
-			__raw_writeb(0xa8, &im->i2c[0].cr);
-		if (i == (count - 1))	/* Reached last byte, STOP */
-			__raw_writeb(0x88, &im->i2c[0].cr);
-
-		/* Read byte of data */
-		buffer[i] = __raw_readb(&im->i2c[0].dr);
-
-		if (i == (count - 1))
-			break;
-		si_wait_i2c();
-	}
-
-	return;
-}
-#endif /* CONFIG_NAND_SPL */
-
-phys_size_t initdram(int board_type)
-{
-	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	volatile fsl_lbc_t *lbc = &im->im_lbc;
-	u32 msize;
-
-	if ((__raw_readl(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32) im)
-		return -1;
-
-	/* DDR SDRAM - Main SODIMM */
-	__raw_writel(CONFIG_SYS_DDR_BASE & LAWBAR_BAR, &im->sysconf.ddrlaw[0].bar);
-
-	msize = fixed_sdram();
-
-	/* Local Bus setup lbcr and mrtpr */
-	__raw_writel(CONFIG_SYS_LBC_LBCR, &lbc->lbcr);
-	__raw_writel(CONFIG_SYS_LBC_MRTPR, &lbc->mrtpr);
-	sync();
-
-	/* return total bus SDRAM size(bytes)  -- DDR */
-	return (msize * 1024 * 1024);
-}
-
-/*************************************************************************
- *  fixed sdram init -- reads values from boot sequencer I2C
- ************************************************************************/
-static long fixed_sdram(void)
-{
-	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	u32 msizelog2, msize = 1;
-#if defined(CONFIG_NAND_SPL)
-	u32 i;
-	const u8 bytecount = 135;
-	u8 buffer[bytecount];
-	u32 addr, data;
-
-	si_read_i2c(0, bytecount, buffer);
-
-	for (i = 18; i < bytecount; i += 7){
-		addr = (u32)buffer[i];
-		addr <<= 8;
-		addr |= (u32)buffer[i + 1];
-		addr <<= 2;
-		data = (u32)buffer[i + 2];
-		data <<= 8;
-		data |= (u32)buffer[i + 3];
-		data <<= 8;
-		data |= (u32)buffer[i + 4];
-		data <<= 8;
-		data |= (u32)buffer[i + 5];
-
-		__raw_writel(data, (u32 *)(CONFIG_SYS_IMMR + addr));
-	}
-
-	sync();
-
-	/* enable DDR controller */
-	__raw_writel((__raw_readl(&im->ddr.sdram_cfg) | SDRAM_CFG_MEM_EN), &im->ddr.sdram_cfg);
-#endif /* (CONFIG_NAND_SPL) */
-
-	msizelog2 = ((__raw_readl(&im->sysconf.ddrlaw[0].ar) & LAWAR_SIZE) + 1);
-	msize <<= (msizelog2 - 20);
-
-	return msize;
-}
diff --git a/board/sheldon/simpc8313/simpc8313.c b/board/sheldon/simpc8313/simpc8313.c
deleted file mode 100644
index 31406fa66d..0000000000
--- a/board/sheldon/simpc8313/simpc8313.c
+++ /dev/null
@@ -1,150 +0,0 @@
-/*
- * Copyright (C) Freescale Semiconductor, Inc. 2006-2007
- * Copyright (C) Sheldon Instruments, Inc. 2008
- *
- * Author: Ron Madrid <info@sheldoninst.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <libfdt.h>
-#include <pci.h>
-#include <mpc83xx.h>
-#include <ns16550.h>
-#include <nand.h>
-#include <asm/io.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifndef CONFIG_NAND_SPL
-int checkboard(void)
-{
-	puts("Board: Sheldon Instruments SIMPC8313\n");
-	return 0;
-}
-
-static struct pci_region pci_regions[] = {
-	{
-		bus_start: CONFIG_SYS_PCI1_MEM_BASE,
-		phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
-		size: CONFIG_SYS_PCI1_MEM_SIZE,
-		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
-	},
-	{
-		bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
-		phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
-		size: CONFIG_SYS_PCI1_MMIO_SIZE,
-		flags: PCI_REGION_MEM
-	},
-	{
-		bus_start: CONFIG_SYS_PCI1_IO_BASE,
-		phys_start: CONFIG_SYS_PCI1_IO_PHYS,
-		size: CONFIG_SYS_PCI1_IO_SIZE,
-		flags: PCI_REGION_IO
-	}
-};
-
-void pci_init_board(void)
-{
-	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
-	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
-	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
-	struct pci_region *reg[] = { pci_regions };
-
-	/* Enable all 3 PCI_CLK_OUTPUTs. */
-	clk->occr |= 0xe0000000;
-
-	/*
-	 * Configure PCI Local Access Windows
-	 */
-	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
-	pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
-
-	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
-	pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
-
-	mpc83xx_pci_init(1, reg);
-}
-
-/*
- * Miscellaneous late-boot configurations
- */
-int misc_init_r(void)
-{
-	int rc = 0;
-	immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	fsl_lbc_t *lbus = &immap->im_lbc;
-	u32 *mxmr = &lbus->mamr;	/* Pointer to mamr */
-
-	/* UPM Table Configuration Code */
-	static uint UPMATable[] = {
-		/* Read Single-Beat (RSS) */
-		0x0fff0c00, 0x0fffdc00, 0x0fff0c05, 0xfffffc00,
-		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-		/* Read Burst (RBS) */
-		0x0fff0c00, 0x0ffcdc00, 0x0ffc0c00, 0x0ffc0f0c,
-		0x0ffccf0c, 0x0ffc0f0c, 0x0ffcce0c, 0x3ffc0c05,
-		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-		/* Write Single-Beat (WSS) */
-		0x0ffc0c00, 0x0ffcdc00, 0x0ffc0c05, 0xfffffc00,
-		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-		/* Write Burst (WBS) */
-		0x0ffc0c00, 0x0fffcc0c, 0x0fff0c00, 0x0fffcc00,
-		0x0fff1c00, 0x0fffcf0c, 0x0fff0f0c, 0x0fffcf0c,
-		0x0fff0c0c, 0x0fffcc0c, 0x0fff0c05, 0xfffffc00,
-		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-		/* Refresh Timer (RTS) */
-		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-		/* Exception Condition (EXS) */
-		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01
-	};
-
-	upmconfig(UPMA, UPMATable, sizeof(UPMATable) / sizeof(UPMATable[0]));
-
-	/* Set LUPWAIT to be active low and enabled */
-	out_be32(mxmr, MxMR_UWPL | MxMR_GPL_x4DIS);
-
-	return rc;
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup(blob, bd);
-#ifdef CONFIG_PCI
-	ft_pci_setup(blob, bd);
-#endif
-}
-#endif
-#else /* CONFIG_NAND_SPL */
-void board_init_f(ulong bootflag)
-{
-	NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500),
-				CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
-	puts("NAND boot... ");
-	init_timebase();
-	initdram(0);
-	relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, (gd_t *)gd,
-				  CONFIG_SYS_NAND_U_BOOT_RELOC);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
-	nand_boot();
-}
-
-void putc(char c)
-{
-	if (gd->flags & GD_FLG_SILENT)
-		return;
-
-	if (c == '\n')
-		NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), '\r');
-
-	NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), c);
-}
-#endif
diff --git a/board/ti/am335x/u-boot.lds b/board/ti/am335x/u-boot.lds
index 2c5a0f8a11..78f294af40 100644
--- a/board/ti/am335x/u-boot.lds
+++ b/board/ti/am335x/u-boot.lds
@@ -78,6 +78,8 @@ SECTIONS
 		*(.__rel_dyn_end)
 	}
 
+	.hash : { *(.hash*) }
+
 	.end :
 	{
 		*(.__end)
@@ -118,7 +120,6 @@ SECTIONS
 	.dynbss : { *(.dynbss) }
 	.dynstr : { *(.dynstr*) }
 	.dynamic : { *(.dynamic*) }
-	.hash : { *(.hash*) }
 	.gnu.hash : { *(.gnu.hash) }
 	.plt : { *(.plt*) }
 	.interp : { *(.interp*) }
diff --git a/board/ttcontrol/vision2/imximage_hynix.cfg b/board/ttcontrol/vision2/imximage_hynix.cfg
index 4e6583ac76..c74973edec 100644
--- a/board/ttcontrol/vision2/imximage_hynix.cfg
+++ b/board/ttcontrol/vision2/imximage_hynix.cfg
@@ -124,7 +124,7 @@ DATA 4 0x73fa889c 0x00000000
 /* ESDCTL0: Enable controller */
 DATA 4 0x83fd9000 0x83220000
 
-/* Init DRAM on CS0 /
+/* Init DRAM on CS0 */
 /* ESDSCR: Precharge command */
 DATA 4 0x83fd9014 0x04008008
 /* ESDSCR: Refresh command */
diff --git a/board/zpc1900/Makefile b/board/zpc1900/Makefile
deleted file mode 100644
index e636365777..0000000000
--- a/board/zpc1900/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= zpc1900.o
diff --git a/board/zpc1900/zpc1900.c b/board/zpc1900/zpc1900.c
deleted file mode 100644
index fed4934afd..0000000000
--- a/board/zpc1900/zpc1900.c
+++ /dev/null
@@ -1,288 +0,0 @@
-/*
- * (C) Copyright 2001-2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2003-2005 Arabella Software Ltd.
- * Yuli Barcohen <yuli@arabellasw.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <ioports.h>
-#include <mpc8260.h>
-#include <miiphy.h>
-
-/*
- * I/O Port configuration table
- *
- * if conf is 1, then that port pin will be configured at boot time
- * according to the five values podr/pdir/ppar/psor/pdat for that entry
- */
-
-const iop_conf_t iop_conf_tab[4][32] = {
-
-    /* Port A */
-    {	/*	      conf ppar psor pdir podr pdat */
-	/* PA31 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxENB  */
-	/* PA30 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 TxClav */
-	/* PA29 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxSOC  */
-	/* PA28 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 RxENB  */
-	/* PA27 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxSOC  */
-	/* PA26 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxClav */
-	/* PA25 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[0] */
-	/* PA24 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[1] */
-	/* PA23 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[2] */
-	/* PA22 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[3] */
-	/* PA21 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[4] */
-	/* PA20 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[5] */
-	/* PA19 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[6] */
-	/* PA18 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[7] */
-	/* PA17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[7] */
-	/* PA16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[6] */
-	/* PA15 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[5] */
-	/* PA14 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[4] */
-	/* PA13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[3] */
-	/* PA12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[2] */
-	/* PA11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[1] */
-	/* PA10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[0] */
-	/* PA9  */ {   0,   1,   1,   1,   0,   0   }, /* SMC2 TXD */
-	/* PA8  */ {   0,   1,   1,   0,   0,   0   }, /* SMC2 RXD */
-	/* PA7  */ {   0,   0,   0,   0,   0,   0   }, /* PA7 */
-	/* PA6  */ {   0,   0,   0,   0,   0,   0   }, /* PA6 */
-	/* PA5  */ {   0,   0,   0,   0,   0,   0   }, /* PA5 */
-	/* PA4  */ {   0,   0,   0,   0,   0,   0   }, /* PA4 */
-	/* PA3  */ {   0,   0,   0,   0,   0,   0   }, /* PA3 */
-	/* PA2  */ {   0,   0,   0,   0,   0,   0   }, /* PA2 */
-	/* PA1  */ {   0,   0,   0,   0,   0,   0   }, /* PA1 */
-	/* PA0  */ {   0,   0,   0,   0,   0,   0   }  /* PA0 */
-    },
-
-    /* Port B */
-    {   /*	      conf ppar psor pdir podr pdat */
-	/* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER  */
-	/* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV  */
-	/* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN  */
-	/* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER  */
-	/* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL    */
-	/* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS    */
-	/* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
-	/* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
-	/* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
-	/* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
-	/* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
-	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
-	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
-	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
-	/* PB17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_DIV */
-	/* PB16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_ERR */
-	/* PB15 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_ERR */
-	/* PB14 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_EN  */
-	/* PB13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:COL */
-	/* PB12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:CRS */
-	/* PB11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
-	/* PB10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
-	/* PB9  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
-	/* PB8  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
-	/* PB7  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
-	/* PB6  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
-	/* PB5  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
-	/* PB4  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
-	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
-    },
-
-    /* Port C */
-    {   /*	      conf ppar psor pdir podr pdat */
-	/* PC31 */ {   0,   0,   0,   0,   0,   0   }, /* PC31 */
-	/* PC30 */ {   0,   0,   0,   0,   0,   0   }, /* PC30 */
-	/* PC29 */ {   0,   1,   1,   0,   0,   0   }, /* SCC1 EN CLSN */
-	/* PC28 */ {   0,   0,   0,   0,   0,   0   }, /* PC28 */
-	/* PC27 */ {   0,   0,   0,   0,   0,   0   }, /* PC27 */
-	/* PC26 */ {   0,   0,   0,   0,   0,   0   }, /* PC26 */
-	/* PC25 */ {   0,   0,   0,   0,   0,   0   }, /* PC25 */
-	/* PC24 */ {   0,   0,   0,   0,   0,   0   }, /* PC24 */
-	/* PC23 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN RXCLK */
-	/* PC22 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN TXCLK */
-	/* PC21 */ {   0,   0,   0,   0,   0,   0   }, /* PC21 */
-	/* PC20 */ {   0,   0,   0,   0,   0,   0   }, /* PC20 */
-	/* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII Rx Clock (CLK13) */
-	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII Tx Clock (CLK14) */
-	/* PC17 */ {   0,   0,   0,   0,   0,   0   }, /* PC17 */
-	/* PC16 */ {   0,   0,   0,   0,   0,   0   }, /* PC16 */
-	/* PC15 */ {   0,   0,   0,   0,   0,   0   }, /* PC15 */
-	/* PC14 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN RENA */
-	/* PC13 */ {   0,   0,   0,   0,   0,   0   }, /* PC13 */
-	/* PC12 */ {   0,   0,   0,   0,   0,   0   }, /* PC12 */
-	/* PC11 */ {   0,   0,   0,   0,   0,   0   }, /* PC11 */
-	/* PC10 */ {   1,   0,   0,   1,   0,   0   }, /* LXT972 MDC */
-	/* PC9  */ {   1,   0,   0,   0,   0,   0   }, /* LXT972 MDIO */
-	/* PC8  */ {   0,   0,   0,   0,   0,   0   }, /* PC8 */
-	/* PC7  */ {   0,   0,   0,   0,   0,   0   }, /* PC7 */
-	/* PC6  */ {   0,   0,   0,   0,   0,   0   }, /* PC6 */
-	/* PC5  */ {   0,   0,   0,   0,   0,   0   }, /* PC5 */
-	/* PC4  */ {   0,   0,   0,   0,   0,   0   }, /* PC4 */
-	/* PC3  */ {   0,   0,   0,   0,   0,   0   }, /* PC3 */
-	/* PC2  */ {   0,   0,   0,   0,   0,   0   }, /* PC2 */
-	/* PC1  */ {   0,   0,   0,   0,   0,   0   }, /* PC1 */
-	/* PC0  */ {   0,   0,   0,   0,   0,   0   }, /* PC0 */
-    },
-
-    /* Port D */
-    {   /*	      conf ppar psor pdir podr pdat */
-	/* PD31 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN RxD  */
-	/* PD30 */ {   0,   1,   1,   1,   0,   0   }, /* SCC1 EN TxD  */
-	/* PD29 */ {   0,   1,   0,   1,   0,   0   }, /* SCC1 EN TENA */
-	/* PD28 */ {   0,   0,   0,   0,   0,   0   }, /* PD28 */
-	/* PD27 */ {   0,   0,   0,   0,   0,   0   }, /* PD27 */
-	/* PD26 */ {   0,   0,   0,   0,   0,   0   }, /* PD26 */
-	/* PD25 */ {   0,   0,   0,   0,   0,   0   }, /* PD25 */
-	/* PD24 */ {   0,   0,   0,   0,   0,   0   }, /* PD24 */
-	/* PD23 */ {   0,   0,   0,   0,   0,   0   }, /* PD23 */
-	/* PD22 */ {   0,   0,   0,   0,   0,   0   }, /* PD22 */
-	/* PD21 */ {   0,   0,   0,   0,   0,   0   }, /* PD21 */
-	/* PD20 */ {   0,   0,   0,   0,   0,   0   }, /* PD20 */
-	/* PD19 */ {   0,   0,   0,   0,   0,   0   }, /* PD19 */
-	/* PD18 */ {   0,   0,   0,   0,   0,   0   }, /* PD18 */
-	/* PD17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXPRTY */
-	/* PD16 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXPRTY */
-	/* PD15 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SDA */
-	/* PD14 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SCL */
-	/* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
-	/* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
-	/* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
-	/* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
-	/* PD9  */ {   1,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
-	/* PD8  */ {   1,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
-	/* PD7  */ {   0,   0,   0,   0,   0,   0   }, /* PD7 */
-	/* PD6  */ {   0,   0,   0,   0,   0,   0   }, /* PD6 */
-	/* PD5  */ {   0,   0,   0,   0,   0,   0   }, /* PD5 */
-	/* PD4  */ {   0,   0,   0,   0,   0,   0   }, /* PD4 */
-	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
-	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
-    }
-};
-
-#ifdef CONFIG_SYS_NVRAM_ACCESS_ROUTINE
-void *nvram_read(void *dest, long src, size_t count)
-{
-	return memcpy(dest, (const void *)src, count);
-}
-
-void nvram_write(long dest, const void *src, size_t count)
-{
-	vu_char     *p1 = (vu_char *)(CONFIG_SYS_EEPROM + 0x1555);
-	vu_char     *p2 = (vu_char *)(CONFIG_SYS_EEPROM + 0x0AAA);
-	vu_char     *d = (vu_char *)dest;
-	const uchar *s = (const uchar *)src;
-
-	/* Unprotect the EEPROM */
-	*p1 = 0xAA;
-	*p2 = 0x55;
-	*p1 = 0x80;
-	*p1 = 0xAA;
-	*p2 = 0x55;
-	*p1 = 0x20;
-	udelay(10000);
-
-	/* Write the data to the EEPROM */
-	while (count--) {
-		*d++ = *s++;
-		while (*(d - 1) != *(s - 1))
-			/* wait */;
-	}
-
-	/* Protect the EEPROM */
-	*p1 = 0xAA;
-	*p2 = 0x55;
-	*p1 = 0xA0;
-	udelay(10000);
-}
-#endif /* CONFIG_SYS_NVRAM_ACCESS_ROUTINE */
-
-phys_size_t initdram(int board_type)
-{
-	vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR;
-	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
-	volatile memctl8260_t *memctl = &immap->im_memctl;
-	vu_char *ramaddr;
-	uchar c = 0xFF;
-	long int msize = CONFIG_SYS_SDRAM_SIZE;
-	int i;
-
-	if (bcsr[4] & BCSR_PCI_MODE) { /* PCI mode selected by JP9 */
-		immap->im_clkrst.car_sccr |= SCCR_PCI_MODE;
-		immap->im_siu_conf.sc_siumcr =
-			(immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
-			| SIUMCR_LBPC01;
-	}
-
-#ifndef CONFIG_SYS_RAMBOOT
-	immap->im_siu_conf.sc_ppc_acr  = 0x03;
-	immap->im_siu_conf.sc_ppc_alrh = 0x30126745;
-	immap->im_siu_conf.sc_tescr1   = 0x00004000;
-
-	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
-
-#ifdef CONFIG_SYS_LSDRAM_BASE
-	/*
-	  Initialise local bus SDRAM only if the pins
-	  are configured as local bus pins and not as PCI.
-	*/
-	if ((immap->im_siu_conf.sc_siumcr & SIUMCR_LBPC11) == SIUMCR_LBPC00) {
-		memctl->memc_lsrt  = CONFIG_SYS_LSRT;
-		memctl->memc_or4   = CONFIG_SYS_LSDRAM_OR;
-		memctl->memc_br4   = CONFIG_SYS_LSDRAM_BR;
-		ramaddr = (vu_char *)CONFIG_SYS_LSDRAM_BASE;
-		memctl->memc_lsdmr = CONFIG_SYS_LSDMR | PSDMR_OP_PREA;
-		*ramaddr = c;
-		memctl->memc_lsdmr = CONFIG_SYS_LSDMR | PSDMR_OP_CBRR;
-		for (i = 0; i < 8; i++)
-			*ramaddr = c;
-		memctl->memc_lsdmr = CONFIG_SYS_LSDMR | PSDMR_OP_MRW;
-		*ramaddr = c;
-		memctl->memc_lsdmr = CONFIG_SYS_LSDMR | PSDMR_RFEN;
-	}
-#endif /* CONFIG_SYS_LSDRAM_BASE */
-
-	/* Initialise 60x bus SDRAM */
-	memctl->memc_psrt = CONFIG_SYS_PSRT;
-	memctl->memc_or2  = CONFIG_SYS_PSDRAM_OR;
-	memctl->memc_br2  = CONFIG_SYS_PSDRAM_BR;
-	/*
-	 * The mode data for Mode Register Write command must appear on
-	 * the address lines during a mode-set cycle. It is driven by
-	 * the memory controller, in single PowerQUICC II mode,
-	 * according to PSDMR[CL] and PSDMR[BL] fields. In
-	 * 60x-compatible mode, software must drive the correct value on
-	 * the address lines. BL=0 because for 64-bit port size burst
-	 * length must be 4.
-	 */
-	ramaddr = (vu_char *)(CONFIG_SYS_SDRAM_BASE |
-			      ((CONFIG_SYS_PSDMR & PSDMR_CL_MSK) << 7) | 0x10);
-	memctl->memc_psdmr = CONFIG_SYS_PSDMR | PSDMR_OP_PREA; /* Precharge all banks */
-	*ramaddr = c;
-	memctl->memc_psdmr = CONFIG_SYS_PSDMR | PSDMR_OP_CBRR; /* CBR refresh */
-	for (i = 0; i < 8; i++)
-		*ramaddr = c;
-	memctl->memc_psdmr = CONFIG_SYS_PSDMR | PSDMR_OP_MRW;  /* Mode Register write */
-	*ramaddr = c;
-	memctl->memc_psdmr = CONFIG_SYS_PSDMR | PSDMR_RFEN;    /* Refresh enable */
-	*ramaddr = c;
-#endif /* CONFIG_SYS_RAMBOOT */
-
-	/* Return total 60x bus SDRAM size */
-	return msize * 1024 * 1024;
-}
-
-int checkboard(void)
-{
-	vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR;
-
-	printf("Board: Zephyr ZPC.1900 Rev. %c\n", bcsr[2] + 0x40);
-	return 0;
-}