Merge branch 'master' of git://git.denx.de/u-boot-arm

Conflicts:
	drivers/spi/Makefile

Signed-off-by: Wolfgang Denk <wd@denx.de>

41 files changed, 1400 insertions, 2204 deletions

diff --git a/board/afeb9260/afeb9260.c b/board/afeb9260/afeb9260.c
index a247663bb4..94a65c27a2 100644
--- a/board/afeb9260/afeb9260.c
+++ b/board/afeb9260/afeb9260.c
@@ -81,6 +81,8 @@ static void afeb9260_nand_hw_init(void)
 #ifdef CONFIG_MACB
 static void afeb9260_macb_hw_init(void)
 {
+	unsigned long rstc;
+
 	/* Enable clock */
 	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC);
 
@@ -103,6 +105,8 @@ static void afeb9260_macb_hw_init(void)
 	       pin_to_mask(AT91_PIN_PA28),
 	       pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
 
+	rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL;
+
 	/* Need to reset PHY -> 500ms reset */
 	at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
 				     AT91_RSTC_ERSTL | (0x0D << 8) |
@@ -115,7 +119,7 @@ static void afeb9260_macb_hw_init(void)
 
 	/* Restore NRST value */
 	at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
-				     AT91_RSTC_ERSTL | (0x0 << 8) |
+				     (rstc) |
 				     AT91_RSTC_URSTEN);
 
 	/* Re-enable pull-up */
diff --git a/board/armltd/.gitignore b/board/armltd/.gitignore
deleted file mode 100644
index a3df156632..0000000000
--- a/board/armltd/.gitignore
+++ /dev/null
@@ -1,2 +0,0 @@
-/integratorap/u-boot.lds
-/integratorcp/u-boot.lds
diff --git a/board/armltd/integratorap/Makefile b/board/armltd/integrator/Makefile
index 79f501a3ec..14d64b7e88 100644
--- a/board/armltd/integratorap/Makefile
+++ b/board/armltd/integrator/Makefile
@@ -29,18 +29,21 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	:= integratorap.o flash.o
-SOBJS	:= lowlevel_init.o
+SOBJS-y	:= lowlevel_init.o
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
+COBJS-y	:= integrator.o
+COBJS-$(CONFIG_PCI) += pci.o
+COBJS-y += timer.o
 
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+COBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB):	$(obj).depend $(COBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(COBJS) $(SOBJS)
 
 clean:
-	rm -f $(SOBJS) $(OBJS)
+	rm -f $(SOBJS) $(COBJS)
 
 distclean:	clean
 	rm -f $(LIB) core *.bak $(obj).depend
diff --git a/board/armltd/integratorap/config.mk b/board/armltd/integrator/config.mk
index 25b79b3e79..25b79b3e79 100644
--- a/board/armltd/integratorap/config.mk
+++ b/board/armltd/integrator/config.mk
diff --git a/board/armltd/integrator/integrator.c b/board/armltd/integrator/integrator.c
new file mode 100644
index 0000000000..a46deea448
--- /dev/null
+++ b/board/armltd/integrator/integrator.c
@@ -0,0 +1,135 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * (C) Copyright 2004
+ * ARM Ltd.
+ * Philippe Robin, <philippe.robin@arm.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#ifdef CONFIG_PCI
+#include <netdev.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void peripheral_power_enable (void);
+
+#if defined(CONFIG_SHOW_BOOT_PROGRESS)
+void show_boot_progress(int progress)
+{
+	printf("Boot reached stage %d\n", progress);
+}
+#endif
+
+#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	/* arch number of Integrator Board */
+#ifdef CONFIG_ARCH_CINTEGRATOR
+	gd->bd->bi_arch_number = MACH_TYPE_CINTEGRATOR;
+#else
+	gd->bd->bi_arch_number = MACH_TYPE_INTEGRATOR;
+#endif
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0x00000100;
+
+	gd->flags = 0;
+
+#ifdef CONFIG_CM_REMAP
+extern void cm_remap(void);
+	cm_remap();	/* remaps writeable memory to 0x00000000 */
+#endif
+
+	icache_enable ();
+
+	return 0;
+}
+
+int misc_init_r (void)
+{
+#ifdef CONFIG_PCI
+	pci_init();
+#endif
+	setenv("verify", "n");
+	return (0);
+}
+
+/******************************
+ Routine:
+ Description:
+******************************/
+int dram_init (void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size	 = PHYS_SDRAM_1_SIZE;
+
+#ifdef CONFIG_CM_SPD_DETECT
+	{
+extern void dram_query(void);
+	unsigned long cm_reg_sdram;
+	unsigned long sdram_shift;
+
+	dram_query();	/* Assembler accesses to CM registers */
+			/* Queries the SPD values	      */
+
+	/* Obtain the SDRAM size from the CM SDRAM register */
+
+	cm_reg_sdram = *(volatile ulong *)(CM_BASE + OS_SDRAM);
+	/*   Register	      SDRAM size
+	 *
+	 *   0xXXXXXXbbb000bb	 16 MB
+	 *   0xXXXXXXbbb001bb	 32 MB
+	 *   0xXXXXXXbbb010bb	 64 MB
+	 *   0xXXXXXXbbb011bb	128 MB
+	 *   0xXXXXXXbbb100bb	256 MB
+	 *
+	 */
+	sdram_shift		 = ((cm_reg_sdram & 0x0000001C)/4)%4;
+	gd->bd->bi_dram[0].size	 = 0x01000000 << sdram_shift;
+
+	}
+#endif /* CM_SPD_DETECT */
+
+	return 0;
+}
+
+#ifdef CONFIG_PCI
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
+#endif
diff --git a/board/armltd/integratorap/lowlevel_init.S b/board/armltd/integrator/lowlevel_init.S
index ab9589c95c..ab9589c95c 100644
--- a/board/armltd/integratorap/lowlevel_init.S
+++ b/board/armltd/integrator/lowlevel_init.S
diff --git a/board/armltd/integratorap/integratorap.c b/board/armltd/integrator/pci.c
index 5ececd6495..6ee2a85307 100644
--- a/board/armltd/integratorap/integratorap.c
+++ b/board/armltd/integrator/pci.c
@@ -34,77 +34,13 @@
  */
 
 #include <common.h>
-
-#ifdef CONFIG_PCI
 #include <pci.h>
-#endif
-
-#include <netdev.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void flash__init (void);
-void ether__init (void);
-void peripheral_power_enable (void);
-
-#if defined(CONFIG_SHOW_BOOT_PROGRESS)
-void show_boot_progress(int progress)
-{
-	printf("Boot reached stage %d\n", progress);
-}
-#endif
-
-#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
-
-static inline void delay (unsigned long loops)
-{
-	__asm__ volatile ("1:\n"
-		"subs %0, %1, #1\n"
-		"bne 1b":"=r" (loops):"0" (loops));
-}
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-
-int board_init (void)
-{
-	/* arch number of Integrator Board */
-	gd->bd->bi_arch_number = MACH_TYPE_INTEGRATOR;
-
-	/* adress of boot parameters */
-	gd->bd->bi_boot_params = 0x00000100;
-
-	gd->flags = 0;
-
-#ifdef CONFIG_CM_REMAP
-extern void cm_remap(void);
-	cm_remap();	/* remaps writeable memory to 0x00000000 */
-#endif
-
-	icache_enable ();
-
-	flash__init ();
-	return 0;
-}
-
-
-int misc_init_r (void)
-{
-#ifdef CONFIG_PCI
-	pci_init();
-#endif
-	setenv("verify", "n");
-	return (0);
-}
 
 /*
  * Initialize PCI Devices, report devices found.
  */
-#ifdef CONFIG_PCI
 
 #ifndef CONFIG_PCI_PNP
-
 static struct pci_config_table pci_integrator_config_table[] = {
 	{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
 	  pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
@@ -112,7 +48,7 @@ static struct pci_config_table pci_integrator_config_table[] = {
 				       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
 	{ }
 };
-#endif
+#endif /* CONFIG_PCI_PNP */
 
 /* V3 access routines */
 #define _V3Write16(o,v) (*(volatile unsigned short *)(PCI_V3_BASE + (unsigned int)(o)) = (unsigned short)(v))
@@ -458,199 +394,3 @@ void pci_init_board (void)
 
 	hose->last_busno = pci_hose_scan (hose);
 }
-#endif
-
-/******************************
- Routine:
- Description:
-******************************/
-void flash__init (void)
-{
-}
-/*************************************************************
- Routine:ether__init
- Description: take the Ethernet controller out of reset and wait
-			   for the EEPROM load to complete.
-*************************************************************/
-void ether__init (void)
-{
-}
-
-/******************************
- Routine:
- Description:
-******************************/
-int dram_init (void)
-{
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size	 = PHYS_SDRAM_1_SIZE;
-
-#ifdef CONFIG_CM_SPD_DETECT
-	{
-extern void dram_query(void);
-	unsigned long cm_reg_sdram;
-	unsigned long sdram_shift;
-
-	dram_query();	/* Assembler accesses to CM registers */
-			/* Queries the SPD values	      */
-
-	/* Obtain the SDRAM size from the CM SDRAM register */
-
-	cm_reg_sdram = *(volatile ulong *)(CM_BASE + OS_SDRAM);
-	/*   Register	      SDRAM size
-	 *
-	 *   0xXXXXXXbbb000bb	 16 MB
-	 *   0xXXXXXXbbb001bb	 32 MB
-	 *   0xXXXXXXbbb010bb	 64 MB
-	 *   0xXXXXXXbbb011bb	128 MB
-	 *   0xXXXXXXbbb100bb	256 MB
-	 *
-	 */
-	sdram_shift		 = ((cm_reg_sdram & 0x0000001C)/4)%4;
-	gd->bd->bi_dram[0].size	 = 0x01000000 << sdram_shift;
-
-	}
-#endif /* CM_SPD_DETECT */
-
-	return 0;
-}
-
-/* The Integrator/AP timer1 is clocked at 24MHz
- * can be divided by 16 or 256
- * and is a 16-bit counter
- */
-/* U-Boot expects a 32 bit timer running at CONFIG_SYS_HZ*/
-static ulong timestamp;		/* U-Boot ticks since startup	      */
-static ulong total_count = 0;	/* Total timer count		      */
-static ulong lastdec;		/* Timer reading at last call	      */
-static ulong div_clock	 = 256; /* Divisor applied to the timer clock */
-static ulong div_timer	 = 1;	/* Divisor to convert timer reading
-				 * change to U-Boot ticks
-				 */
-/* CONFIG_SYS_HZ = CONFIG_SYS_HZ_CLOCK/(div_clock * div_timer) */
-
-#define TIMER_LOAD_VAL 0x0000FFFFL
-#define READ_TIMER ((*(volatile ulong *)(CONFIG_SYS_TIMERBASE+4)) & 0x0000FFFFL)
-
-/* all function return values in U-Boot ticks i.e. (1/CONFIG_SYS_HZ) sec
- *  - unless otherwise stated
- */
-
-/* starts a counter
- * - the Integrator/AP timer issues an interrupt
- *   each time it reaches zero
- */
-int timer_init (void)
-{
-	/* Load timer with initial value */
-	*(volatile ulong *)(CONFIG_SYS_TIMERBASE + 0) = TIMER_LOAD_VAL;
-	/* Set timer to be
-	 *	enabled		  1
-	 *	free-running	  0
-	 *	XX		 00
-	 *	divider 256	 10
-	 *	XX		 00
-	 */
-	*(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = 0x00000088;
-	total_count = 0;
-	/* init the timestamp and lastdec value */
-	reset_timer_masked();
-
-	div_timer  = CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ;
-	div_timer /= div_clock;
-
-	return (0);
-}
-
-/*
- * timer without interrupts
- */
-void reset_timer (void)
-{
-	reset_timer_masked ();
-}
-
-ulong get_timer (ulong base_ticks)
-{
-	return get_timer_masked () - base_ticks;
-}
-
-void set_timer (ulong ticks)
-{
-	timestamp = ticks;
-	total_count = ticks * div_timer;
-	reset_timer_masked();
-}
-
-/* delay x useconds */
-void udelay (unsigned long usec)
-{
-	ulong tmo, tmp;
-
-	/* Convert to U-Boot ticks */
-	tmo  = usec * CONFIG_SYS_HZ;
-	tmo /= (1000000L);
-
-	tmp  = get_timer_masked();	/* get current timestamp */
-	tmo += tmp;			/* wake up timestamp	 */
-
-	while (get_timer_masked () < tmo) { /* loop till event */
-		/*NOP*/;
-	}
-}
-
-void reset_timer_masked (void)
-{
-	/* reset time */
-	lastdec	  = READ_TIMER; /* capture current decrementer value   */
-	timestamp = 0;		/* start "advancing" time stamp from 0 */
-}
-
-/* converts the timer reading to U-Boot ticks	       */
-/* the timestamp is the number of ticks since reset    */
-/* This routine does not detect wraps unless called regularly
-   ASSUMES a call at least every 16 seconds to detect every reload */
-ulong get_timer_masked (void)
-{
-	ulong now = READ_TIMER;		/* current count */
-
-	if (now > lastdec) {
-		/* Must have wrapped */
-		total_count += lastdec + TIMER_LOAD_VAL + 1 - now;
-	} else {
-		total_count += lastdec - now;
-	}
-	lastdec	  = now;
-	timestamp = total_count/div_timer;
-
-	return timestamp;
-}
-
-/* waits specified delay value and resets timestamp */
-void udelay_masked (unsigned long usec)
-{
-	udelay(usec);
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
-	return get_timer(0);
-}
-
-/*
- * Return the timebase clock frequency
- * i.e. how often the timer decrements
- */
-ulong get_tbclk (void)
-{
-	return CONFIG_SYS_HZ_CLOCK/div_clock;
-}
-
-int board_eth_init(bd_t *bis)
-{
-	return pci_eth_init(bis);
-}
diff --git a/board/armltd/integrator/split_by_variant.sh b/board/armltd/integrator/split_by_variant.sh
new file mode 100755
index 0000000000..d67bdc234e
--- /dev/null
+++ b/board/armltd/integrator/split_by_variant.sh
@@ -0,0 +1,235 @@
+#!/bin/sh
+
+mkdir -p ${obj}include
+mkdir -p ${obj}board/armltd/integrator
+
+config_file=${obj}include/config.h
+
+if [ "$1" = "ap" ]
+then
+# ---------------------------------------------------------
+# Set the platform defines
+# ---------------------------------------------------------
+echo -n	"/* Integrator configuration implied "	 > ${config_file}
+echo	" by Makefile target */"		>> ${config_file}
+echo -n	"#define CONFIG_INTEGRATOR"		>> ${config_file}
+echo	" /* Integrator board */"		>> ${config_file}
+echo -n	"#define CONFIG_ARCH_INTEGRATOR"	>> ${config_file}
+echo	" 1 /* Integrator/AP	 */"		>> ${config_file}
+# ---------------------------------------------------------
+#	Set the core module defines according to Core Module
+# ---------------------------------------------------------
+cpu="arm_intcm"
+variant="unknown core module"
+
+if [ "$2" = "" ]
+then
+	echo "$0:: No parameters - using arm_intcm"
+else
+	case "$2" in
+	ap7_config)
+	cpu="arm_intcm"
+	variant="unported core module CM7TDMI"
+	;;
+
+	ap966)
+	cpu="arm_intcm"
+	variant="unported core module CM966E-S"
+	;;
+
+	ap922_config)
+	cpu="arm_intcm"
+	variant="unported core module CM922T"
+	;;
+
+	integratorap_config	|	\
+	ap_config)
+	cpu="arm_intcm"
+	variant="unspecified core module"
+	;;
+
+	ap720t_config)
+	cpu="arm720t"
+	echo -n	"#define CONFIG_CM720T"			>> ${config_file}
+	echo	" 1 /* CPU core is ARM720T */ "		>> ${config_file}
+	variant="Core module CM720T"
+	;;
+
+	ap922_XA10_config)
+	cpu="arm_intcm"
+	variant="unported core module CM922T_XA10"
+	echo -n	"#define CONFIG_CM922T_XA10"		>> ${config_file}
+	echo	" 1 /* CPU core is ARM922T_XA10 */"	>> ${config_file}
+	;;
+
+	ap920t_config)
+	cpu="arm920t"
+	variant="Core module CM920T"
+	echo -n	"#define CONFIG_CM920T"			>> ${config_file}
+	echo	" 1 /* CPU core is ARM920T */"		>> ${config_file}
+	;;
+
+	ap926ejs_config)
+	cpu="arm926ejs"
+	variant="Core module CM926EJ-S"
+	echo -n	"#define CONFIG_CM926EJ_S"		>> ${config_file}
+	echo	" 1 /* CPU core is ARM926EJ-S */ "	>> ${config_file}
+	;;
+
+	ap946es_config)
+	cpu="arm946es"
+	variant="Core module CM946E-S"
+	echo -n	"#define CONFIG_CM946E_S"		>> ${config_file}
+	echo	" 1 /* CPU core is ARM946E-S */ "	>> ${config_file}
+	;;
+
+	*)
+	echo "$0:: Unknown core module"
+	variant="unknown core module"
+	cpu="arm_intcm"
+	;;
+
+	esac
+fi
+
+case "$cpu" in
+	arm_intcm)
+	echo "/* Core module undefined/not ported */"	>> ${config_file}
+	echo "#define CONFIG_ARM_INTCM 1"		>> ${config_file}
+	echo -n	"#undef CONFIG_CM_MULTIPLE_SSRAM"	>> ${config_file}
+	echo -n	"	/* CM may not have "		>> ${config_file}
+	echo	"multiple SSRAM mapping */"		>> ${config_file}
+	echo -n	"#undef CONFIG_CM_SPD_DETECT "		>> ${config_file}
+	echo -n	" /* CM may not support SPD "		>> ${config_file}
+	echo	"query */"				>> ${config_file}
+	echo -n	"#undef CONFIG_CM_REMAP	"		>> ${config_file}
+	echo -n	" /* CM may not support "		>> ${config_file}
+	echo	"remapping */"				>> ${config_file}
+	echo -n	"#undef CONFIG_CM_INIT	"		>> ${config_file}
+	echo -n	" /* CM may not have	"		>> ${config_file}
+	echo	"initialization reg */"			>> ${config_file}
+	echo -n	"#undef CONFIG_CM_TCRAM	"		>> ${config_file}
+	echo	" /* CM may not have TCRAM */"		>> ${config_file}
+	echo -n	" /* May not be processor "		>> ${config_file}
+	echo	"without cache support */"		>> ${config_file}
+	echo	"#define CONFIG_SYS_NO_ICACHE 1"	>> ${config_file}
+	echo	"#define CONFIG_SYS_NO_DCACHE 1"	>> ${config_file}
+	;;
+
+	arm720t)
+	echo -n	" /* May not be processor "		>> ${config_file}
+	echo	"without cache support */"		>> ${config_file}
+	echo	"#define CONFIG_SYS_NO_ICACHE 1"	>> ${config_file}
+	echo	"#define CONFIG_SYS_NO_DCACHE 1"	>> ${config_file}
+	;;
+esac
+
+else
+
+# ---------------------------------------------------------
+# Set the platform defines
+# ---------------------------------------------------------
+echo -n "/* Integrator configuration implied "   > ${config_file}
+echo    " by Makefile target */"		>> ${config_file}
+echo -n "#define CONFIG_INTEGRATOR"		>> ${config_file}
+echo	 " /* Integrator board */"		>> ${config_file}
+echo -n "#define CONFIG_ARCH_CINTEGRATOR"	>> ${config_file}
+echo     " 1 /* Integrator/CP   */"		>> ${config_file}
+
+cpu="arm_intcm"
+variant="unknown core module"
+
+if [ "$2" = "" ]
+then
+	echo "$0:: No parameters - using arm_intcm"
+else
+	case "$2" in
+	ap966)
+	cpu="arm_intcm"
+	variant="unported core module CM966E-S"
+	;;
+
+	ap922_config)
+	cpu="arm_intcm"
+	variant="unported core module CM922T"
+	;;
+
+	integratorcp_config	|	\
+	cp_config)
+	cpu="arm_intcm"
+	variant="unspecified core module"
+	;;
+
+	cp922_XA10_config)
+	cpu="arm_intcm"
+	variant="unported core module CM922T_XA10"
+	echo -n "#define CONFIG_CM922T_XA10"		>> ${config_file}
+	echo    " 1 /* CPU core is ARM922T_XA10 */"	>> ${config_file}
+	;;
+
+	cp920t_config)
+	cpu="arm920t"
+	variant="Core module CM920T"
+	echo -n "#define CONFIG_CM920T"			>> ${config_file}
+	echo    " 1 /* CPU core is ARM920T */"		>> ${config_file}
+	;;
+
+	cp926ejs_config)
+	cpu="arm926ejs"
+	variant="Core module CM926EJ-S"
+	echo -n "#define CONFIG_CM926EJ_S"		>> ${config_file}
+	echo    " 1 /* CPU core is ARM926EJ-S */ "	>> ${config_file}
+	;;
+
+
+	cp946es_config)
+	cpu="arm946es"
+	variant="Core module CM946E-S"
+	echo -n "#define CONFIG_CM946E_S"		>> ${config_file}
+	echo    " 1 /* CPU core is ARM946E-S */ "	>> ${config_file}
+	;;
+
+	cp1136_config)
+	cpu="arm1136"
+	variant="Core module CM1136EJF-S"
+	echo -n "#define CONFIG_CM1136EJF_S"		>> ${config_file}
+	echo    " 1 /* CPU core is ARM1136JF-S */ "	>> ${config_file}
+	;;
+
+	*)
+	echo "$0:: Unknown core module"
+	variant="unknown core module"
+	cpu="arm_intcm"
+	;;
+
+	esac
+
+fi
+
+if [ "$cpu" = "arm_intcm" ]
+then
+	echo "/* Core module undefined/not ported */"	>> ${config_file}
+	echo "#define CONFIG_ARM_INTCM 1"		>> ${config_file}
+	echo -n "#undef CONFIG_CM_MULTIPLE_SSRAM"	>> ${config_file}
+	echo -n "  /* CM may not have "			>> ${config_file}
+	echo    "multiple SSRAM mapping */"		>> ${config_file}
+	echo -n "#undef CONFIG_CM_SPD_DETECT "		>> ${config_file}
+	echo -n " /* CM may not support SPD "		>> ${config_file}
+	echo    "query */"				>> ${config_file}
+	echo -n "#undef CONFIG_CM_REMAP  "		>> ${config_file}
+	echo -n " /* CM may not support "		>> ${config_file}
+	echo    "remapping */"				>> ${config_file}
+	echo -n "#undef CONFIG_CM_INIT  "		>> ${config_file}
+	echo -n " /* CM may not have  "			>> ${config_file}
+	echo    "initialization reg */"			>> ${config_file}
+	echo -n "#undef CONFIG_CM_TCRAM  "		>> ${config_file}
+	echo    " /* CM may not have TCRAM */"		>> ${config_file}
+fi
+
+fi # ap
+
+# ---------------------------------------------------------
+# Complete the configuration
+# ---------------------------------------------------------
+$MKCONFIG -a integrator$1 arm $cpu integrator armltd;
+echo "Variant:: $variant with core $cpu"
diff --git a/board/armltd/integratorcp/integratorcp.c b/board/armltd/integrator/timer.c
index 0d3afd8d24..087cf59622 100644
--- a/board/armltd/integratorcp/integratorcp.c
+++ b/board/armltd/integrator/timer.c
@@ -36,109 +36,13 @@
 #include <common.h>
 #include <div64.h>
 
-DECLARE_GLOBAL_DATA_PTR;
-
-void flash__init (void);
-void ether__init (void);
-void peripheral_power_enable (void);
-
-#if defined(CONFIG_SHOW_BOOT_PROGRESS)
-void show_boot_progress(int progress)
-{
-	printf("Boot reached stage %d\n", progress);
-}
-#endif
-
-#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-
-int board_init (void)
-{
-	/* arch number of Integrator Board */
-	gd->bd->bi_arch_number = MACH_TYPE_CINTEGRATOR;
-
-	/* adress of boot parameters */
-	gd->bd->bi_boot_params = 0x00000100;
-
-	gd->flags = 0;
-
-#ifdef CONFIG_CM_REMAP
-extern void cm_remap(void);
-	cm_remap();	/* remaps writeable memory to 0x00000000 */
+#ifdef CONFIG_ARCH_CINTEGRATOR
+#define DIV_CLOCK_INIT	1
+#define TIMER_LOAD_VAL	0xFFFFFFFFL
+#else
+#define DIV_CLOCK_INIT	256
+#define TIMER_LOAD_VAL	0x0000FFFFL
 #endif
-
-	icache_enable ();
-
-	flash__init ();
-	ether__init ();
-	return 0;
-}
-
-
-int misc_init_r (void)
-{
-	setenv("verify", "n");
-	return (0);
-}
-
-/******************************
- Routine:
- Description:
-******************************/
-void flash__init (void)
-{
-}
-/*************************************************************
- Routine:ether__init
- Description: take the Ethernet controller out of reset and wait
-	      for the EEPROM load to complete.
-*************************************************************/
-void ether__init (void)
-{
-}
-
-/******************************
- Routine:
- Description:
-******************************/
-int dram_init (void)
-{
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size	 = PHYS_SDRAM_1_SIZE;
-
-#ifdef CONFIG_CM_SPD_DETECT
-    {
-extern void dram_query(void);
-	unsigned long cm_reg_sdram;
-	unsigned long sdram_shift;
-
-	dram_query();	/* Assembler accesses to CM registers */
-			/* Queries the SPD values	      */
-
-	/* Obtain the SDRAM size from the CM SDRAM register */
-
-	cm_reg_sdram = *(volatile ulong *)(CM_BASE + OS_SDRAM);
-	/*   Register	      SDRAM size
-	 *
-	 *   0xXXXXXXbbb000bb	 16 MB
-	 *   0xXXXXXXbbb001bb	 32 MB
-	 *   0xXXXXXXbbb010bb	 64 MB
-	 *   0xXXXXXXbbb011bb	128 MB
-	 *   0xXXXXXXbbb100bb	256 MB
-	 *
-	 */
-	sdram_shift		 = ((cm_reg_sdram & 0x0000001C)/4)%4;
-	gd->bd->bi_dram[0].size	 = 0x01000000 << sdram_shift;
-
-    }
-#endif /* CM_SPD_DETECT */
-
-	return 0;
-}
-
 /* The Integrator/CP timer1 is clocked at 1MHz
  * can be divided by 16 or 256
  * and can be set up as a 32-bit timer
@@ -147,14 +51,14 @@ extern void dram_query(void);
 /* Keep total timer count to avoid losing decrements < div_timer */
 static unsigned long long total_count = 0;
 static unsigned long long lastdec;	 /* Timer reading at last call	   */
-static unsigned long long div_clock = 1; /* Divisor applied to timer clock */
+/* Divisor applied to timer clock */
+static unsigned long long div_clock = DIV_CLOCK_INIT;
 static unsigned long long div_timer = 1; /* Divisor to convert timer reading
 					  * change to U-Boot ticks
 					  */
 /* CONFIG_SYS_HZ = CONFIG_SYS_HZ_CLOCK/(div_clock * div_timer) */
-static ulong timestamp;		/* U-Boot ticks since startup	      */
+static ulong timestamp;		/* U-Boot ticks since startup */
 
-#define TIMER_LOAD_VAL ((ulong)0xFFFFFFFF)
 #define READ_TIMER (*(volatile ulong *)(CONFIG_SYS_TIMERBASE+4))
 
 /* all function return values in U-Boot ticks i.e. (1/CONFIG_SYS_HZ) sec
@@ -167,22 +71,35 @@ int timer_init (void)
 {
 	/* Load timer with initial value */
 	*(volatile ulong *)(CONFIG_SYS_TIMERBASE + 0) = TIMER_LOAD_VAL;
+#ifdef CONFIG_ARCH_CINTEGRATOR
 	/* Set timer to be
-	 *	enabled		  1
-	 *	periodic	  1
-	 *	no interrupts	  0
-	 *	X		  0
-	 *	divider 1	 00 == less rounding error
-	 *	32 bit		  1
-	 *	wrapping	  0
+	 *	enabled		 1
+	 *	periodic	 1
+	 *	no interrupts	 0
+	 *	X		 0
+	 *	divider 1	00 == less rounding error
+	 *	32 bit		 1
+	 *	wrapping	 0
 	 */
 	*(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = 0x000000C2;
+#else
+	/* Set timer to be
+	 *	enabled		 1
+	 *	free-running	 0
+	 *	XX		00
+	 *	divider 256	10
+	 *	XX		00
+	 */
+	*(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = 0x00000088;
+#endif
+
 	/* init the timestamp */
 	total_count = 0ULL;
 	reset_timer_masked();
 
-	div_timer  = (unsigned long long)(CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ);
-	div_timer /= div_clock;
+	div_timer = CONFIG_SYS_HZ_CLOCK;
+	do_div(div_timer, CONFIG_SYS_HZ);
+	do_div(div_timer, div_clock);
 
 	return (0);
 }
@@ -203,7 +120,7 @@ ulong get_timer (ulong base_ticks)
 void set_timer (ulong ticks)
 {
 	timestamp   = ticks;
-	total_count = (unsigned long long)ticks * div_timer;
+	total_count = ticks * div_timer;
 }
 
 /* delay usec useconds */
@@ -226,7 +143,7 @@ void udelay (unsigned long usec)
 void reset_timer_masked (void)
 {
 	/* capure current decrementer value    */
-	lastdec	  = (unsigned long long)READ_TIMER;
+	lastdec	  = READ_TIMER;
 	/* start "advancing" time stamp from 0 */
 	timestamp = 0L;
 }
@@ -236,7 +153,7 @@ void reset_timer_masked (void)
 ulong get_timer_masked (void)
 {
 	/* get current count */
-	unsigned long long now = (unsigned long long)READ_TIMER;
+	unsigned long long now = READ_TIMER;
 
 	if(now > lastdec) {
 		/* Must have wrapped */
@@ -244,7 +161,7 @@ ulong get_timer_masked (void)
 	} else {
 		total_count += lastdec - now;
 	}
-	lastdec	  = now;
+	lastdec	= now;
 
 	/* Reuse "now" */
 	now = total_count;
@@ -266,7 +183,7 @@ void udelay_masked (unsigned long usec)
  */
 unsigned long long get_ticks(void)
 {
-	return (unsigned long long)get_timer(0);
+	return get_timer(0);
 }
 
 /*
@@ -275,5 +192,9 @@ unsigned long long get_ticks(void)
  */
 ulong get_tbclk (void)
 {
-	return (ulong)(((unsigned long long)CONFIG_SYS_HZ_CLOCK)/div_clock);
+	unsigned long long tmp = CONFIG_SYS_HZ_CLOCK;
+
+	do_div(tmp, div_clock);
+
+	return tmp;
 }
diff --git a/board/armltd/integratorap/flash.c b/board/armltd/integratorap/flash.c
deleted file mode 100644
index 0492be7620..0000000000
--- a/board/armltd/integratorap/flash.c
+++ /dev/null
@@ -1,473 +0,0 @@
-/*
- * (C) Copyright 2001
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2001-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2003
- * Texas Instruments, <www.ti.com>
- * Kshitij Gupta <Kshitij@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <linux/byteorder/swab.h>
-
-#define PHYS_FLASH_SECT_SIZE	0x00020000	/* 256 KB sectors (x2) */
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips    */
-
-/* Board support for 1 or 2 flash devices */
-#undef FLASH_PORT_WIDTH32
-#define FLASH_PORT_WIDTH16
-
-#ifdef FLASH_PORT_WIDTH16
-#define FLASH_PORT_WIDTH		ushort
-#define FLASH_PORT_WIDTHV		vu_short
-#define SWAP(x)			__swab16(x)
-#else
-#define FLASH_PORT_WIDTH		ulong
-#define FLASH_PORT_WIDTHV		vu_long
-#define SWAP(x)			__swab32(x)
-#endif
-
-#define FPW	FLASH_PORT_WIDTH
-#define FPWV	FLASH_PORT_WIDTHV
-
-#define mb() __asm__ __volatile__ ("" : : : "memory")
-
-
-/* Flash Organization Structure */
-typedef struct OrgDef {
-	unsigned int sector_number;
-	unsigned int sector_size;
-} OrgDef;
-
-
-/* Flash Organizations */
-OrgDef OrgIntel_28F256L18T[] = {
-	{4, 32 * 1024},				/* 4 * 32kBytes sectors */
-	{255, 128 * 1024},			/* 255 * 128kBytes sectors */
-};
-
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-unsigned long flash_init (void);
-static ulong flash_get_size (FPW * addr, flash_info_t * info);
-static int write_data (flash_info_t * info, ulong dest, FPW data);
-static void flash_get_offsets (ulong base, flash_info_t * info);
-void inline spin_wheel (void);
-void flash_print_info (flash_info_t * info);
-void flash_unprotect_sectors (FPWV * addr);
-int flash_erase (flash_info_t * info, int s_first, int s_last);
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
-	int i;
-	ulong size = 0;
-	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
-		switch (i) {
-		case 0:
-			flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
-			flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
-			break;
-		default:
-			panic ("configured too many flash banks!\n");
-			break;
-		}
-		size += flash_info[i].size;
-	}
-
-	/* Protect monitor and environment sectors
-	 */
-	flash_protect (FLAG_PROTECT_SET,
-			CONFIG_SYS_FLASH_BASE,
-			CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]);
-
-	return size;
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t * info)
-{
-	int i;
-	OrgDef *pOrgDef;
-
-	pOrgDef = OrgIntel_28F256L18T;
-	if (info->flash_id == FLASH_UNKNOWN) {
-		return;
-	}
-
-	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
-		for (i = 0; i < info->sector_count; i++) {
-			if (i > 255) {
-				info->start[i] = base + (i * 0x8000);
-				info->protect[i] = 0;
-			} else {
-				info->start[i] = base +
-						(i * PHYS_FLASH_SECT_SIZE);
-				info->protect[i] = 0;
-			}
-		}
-	}
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t * info)
-{
-	int i;
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf ("missing or unknown FLASH type\n");
-		return;
-	}
-
-	switch (info->flash_id & FLASH_VENDMASK) {
-	case FLASH_MAN_INTEL:
-		printf ("INTEL ");
-		break;
-	default:
-		printf ("Unknown Vendor ");
-		break;
-	}
-
-	switch (info->flash_id & FLASH_TYPEMASK) {
-	case FLASH_28F256L18T:
-		printf ("FLASH 28F256L18T\n");
-		break;
-	default:
-		printf ("Unknown Chip Type\n");
-		break;
-	}
-
-	printf ("  Size: %ld MB in %d Sectors\n",
-			info->size >> 20, info->sector_count);
-
-	printf ("  Sector Start Addresses:");
-	for (i = 0; i < info->sector_count; ++i) {
-		if ((i % 5) == 0)
-			printf ("\n   ");
-		printf (" %08lX%s",
-			info->start[i], info->protect[i] ? " (RO)" : "     ");
-	}
-	printf ("\n");
-	return;
-}
-
-/*
- * The following code cannot be run from FLASH!
- */
-static ulong flash_get_size (FPW * addr, flash_info_t * info)
-{
-	volatile FPW value;
-
-	/* Write auto select command: read Manufacturer ID */
-	addr[0x5555] = (FPW) 0x00AA00AA;
-	addr[0x2AAA] = (FPW) 0x00550055;
-	addr[0x5555] = (FPW) 0x00900090;
-
-	mb ();
-	value = addr[0];
-
-	switch (value) {
-
-	case (FPW) INTEL_MANUFACT:
-		info->flash_id = FLASH_MAN_INTEL;
-		break;
-
-	default:
-		info->flash_id = FLASH_UNKNOWN;
-		info->sector_count = 0;
-		info->size = 0;
-		addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
-		return (0);		/* no or unknown flash  */
-	}
-
-	mb ();
-	value = addr[1];	/* device ID        */
-	switch (value) {
-
-	case (FPW) (INTEL_ID_28F256L18T):
-		info->flash_id += FLASH_28F256L18T;
-		info->sector_count = 259;
-		info->size = 0x02000000;
-		break;			/* => 32 MB     */
-
-	default:
-		info->flash_id = FLASH_UNKNOWN;
-		break;
-	}
-
-	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
-		printf ("** ERROR: sector count %d > max (%d) **\n",
-				info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
-		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
-	}
-
-	addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
-
-	return (info->size);
-}
-
-
-/* unprotects a sector for write and erase
- * on some intel parts, this unprotects the entire chip, but it
- * wont hurt to call this additional times per sector...
- */
-void flash_unprotect_sectors (FPWV * addr)
-{
-#define PD_FINTEL_WSMS_READY_MASK    0x0080
-
-	*addr = (FPW) 0x00500050;	/* clear status register */
-
-	/* this sends the clear lock bit command */
-	*addr = (FPW) 0x00600060;
-	*addr = (FPW) 0x00D000D0;
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
-	int flag, prot, sect;
-	ulong type, start, last;
-	int rcode = 0;
-
-	if ((s_first < 0) || (s_first > s_last)) {
-		if (info->flash_id == FLASH_UNKNOWN) {
-			printf ("- missing\n");
-		} else {
-			printf ("- no sectors to erase\n");
-		}
-		return 1;
-	}
-
-	type = (info->flash_id & FLASH_VENDMASK);
-	if ((type != FLASH_MAN_INTEL)) {
-		printf ("Can't erase unknown flash type %08lx - aborted\n",
-				info->flash_id);
-		return 1;
-	}
-
-	prot = 0;
-	for (sect = s_first; sect <= s_last; ++sect) {
-		if (info->protect[sect]) {
-			prot++;
-		}
-	}
-
-	if (prot) {
-		printf ("- Warning: %d protected sectors will not be erased!\n",
-				prot);
-	} else {
-		printf ("\n");
-	}
-
-
-	start = get_timer (0);
-	last = start;
-
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts ();
-
-	/* Start erase on unprotected sectors */
-	for (sect = s_first; sect <= s_last; sect++) {
-		if (info->protect[sect] == 0) {	/* not protected */
-			FPWV *addr = (FPWV *) (info->start[sect]);
-			FPW status;
-
-			printf ("Erasing sector %2d ... ", sect);
-
-			flash_unprotect_sectors (addr);
-
-			/* arm simple, non interrupt dependent timer */
-			reset_timer_masked ();
-
-			*addr = (FPW) 0x00500050;/* clear status register */
-			*addr = (FPW) 0x00200020;/* erase setup */
-			*addr = (FPW) 0x00D000D0;/* erase confirm */
-
-			while (((status =
-				*addr) & (FPW) 0x00800080) !=
-				(FPW) 0x00800080) {
-					if (get_timer_masked () >
-					CONFIG_SYS_FLASH_ERASE_TOUT) {
-					printf ("Timeout\n");
-					/* suspend erase     */
-					*addr = (FPW) 0x00B000B0;
-					/* reset to read mode */
-					*addr = (FPW) 0x00FF00FF;
-					rcode = 1;
-					break;
-				}
-			}
-
-			/* clear status register cmd.   */
-			*addr = (FPW) 0x00500050;
-			*addr = (FPW) 0x00FF00FF;/* resest to read mode */
-			printf (" done\n");
-		}
-	}
-	return rcode;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- * 4 - Flash not identified
- */
-
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
-	ulong cp, wp;
-	FPW data;
-	int count, i, l, rc, port_width;
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		return 4;
-	}
-/* get lower word aligned address */
-#ifdef FLASH_PORT_WIDTH16
-	wp = (addr & ~1);
-	port_width = 2;
-#else
-	wp = (addr & ~3);
-	port_width = 4;
-#endif
-
-	/*
-	 * handle unaligned start bytes
-	 */
-	if ((l = addr - wp) != 0) {
-		data = 0;
-		for (i = 0, cp = wp; i < l; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *) cp);
-		}
-		for (; i < port_width && cnt > 0; ++i) {
-			data = (data << 8) | *src++;
-			--cnt;
-			++cp;
-		}
-		for (; cnt == 0 && i < port_width; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *) cp);
-		}
-
-		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
-			return (rc);
-		}
-		wp += port_width;
-	}
-
-	/*
-	 * handle word aligned part
-	 */
-	count = 0;
-	while (cnt >= port_width) {
-		data = 0;
-		for (i = 0; i < port_width; ++i) {
-			data = (data << 8) | *src++;
-		}
-		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
-			return (rc);
-		}
-		wp += port_width;
-		cnt -= port_width;
-		if (count++ > 0x800) {
-			spin_wheel ();
-			count = 0;
-		}
-	}
-
-	if (cnt == 0) {
-		return (0);
-	}
-
-	/*
-	 * handle unaligned tail bytes
-	 */
-	data = 0;
-	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
-		data = (data << 8) | *src++;
-		--cnt;
-	}
-	for (; i < port_width; ++i, ++cp) {
-		data = (data << 8) | (*(uchar *) cp);
-	}
-
-	return (write_data (info, wp, SWAP (data)));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word or halfword to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_data (flash_info_t * info, ulong dest, FPW data)
-{
-	FPWV *addr = (FPWV *) dest;
-	ulong status;
-	int flag;
-
-	/* Check if Flash is (sufficiently) erased */
-	if ((*addr & data) != data) {
-		printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr);
-		return (2);
-	}
-	flash_unprotect_sectors (addr);
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts ();
-	*addr = (FPW) 0x00400040;	/* write setup */
-	*addr = data;
-
-	/* arm simple, non interrupt dependent timer */
-	reset_timer_masked ();
-
-	/* wait while polling the status register */
-	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
-		if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
-			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
-			return (1);
-		}
-	}
-	*addr = (FPW) 0x00FF00FF;	/* restore read mode */
-	return (0);
-}
-
-void inline spin_wheel (void)
-{
-	static int p = 0;
-	static char w[] = "\\/-";
-
-	printf ("\010%c", w[p]);
-	(++p == 3) ? (p = 0) : 0;
-}
diff --git a/board/armltd/integratorap/split_by_variant.sh b/board/armltd/integratorap/split_by_variant.sh
deleted file mode 100755
index 2f86b52108..0000000000
--- a/board/armltd/integratorap/split_by_variant.sh
+++ /dev/null
@@ -1,127 +0,0 @@
-#!/bin/sh
-# ---------------------------------------------------------
-# Set the platform defines
-# ---------------------------------------------------------
-echo -n	"/* Integrator configuration implied "	 > tmp.fil
-echo	" by Makefile target */"		>> tmp.fil
-echo -n	"#define CONFIG_INTEGRATOR"		>> tmp.fil
-echo	" /* Integrator board */"		>> tmp.fil
-echo -n	"#define CONFIG_ARCH_INTEGRATOR"	>> tmp.fil
-echo	" 1 /* Integrator/AP	 */"		>> tmp.fil
-# ---------------------------------------------------------
-#	Set the core module defines according to Core Module
-# ---------------------------------------------------------
-cpu="arm_intcm"
-variant="unknown core module"
-
-if [ "$1" = "" ]
-then
-	echo "$0:: No parameters - using arm_intcm"
-else
-	case "$1" in
-	ap7_config)
-	cpu="arm_intcm"
-	variant="unported core module CM7TDMI"
-	;;
-
-	ap966)
-	cpu="arm_intcm"
-	variant="unported core module CM966E-S"
-	;;
-
-	ap922_config)
-	cpu="arm_intcm"
-	variant="unported core module CM922T"
-	;;
-
-	integratorap_config	|	\
-	ap_config)
-	cpu="arm_intcm"
-	variant="unspecified core module"
-	;;
-
-	ap720t_config)
-	cpu="arm720t"
-	echo -n	"#define CONFIG_CM720T"			>> tmp.fil
-	echo	" 1 /* CPU core is ARM720T */ "		>> tmp.fil
-	variant="Core module CM720T"
-	;;
-
-	ap922_XA10_config)
-	cpu="arm_intcm"
-	variant="unported core module CM922T_XA10"
-	echo -n	"#define CONFIG_CM922T_XA10"		>> tmp.fil
-	echo	" 1 /* CPU core is ARM922T_XA10 */"	>> tmp.fil
-	;;
-
-	ap920t_config)
-	cpu="arm920t"
-	variant="Core module CM920T"
-	echo -n	"#define CONFIG_CM920T"			>> tmp.fil
-	echo	" 1 /* CPU core is ARM920T */"		>> tmp.fil
-	;;
-
-	ap926ejs_config)
-	cpu="arm926ejs"
-	variant="Core module CM926EJ-S"
-	echo -n	"#define CONFIG_CM926EJ_S"		>> tmp.fil
-	echo	" 1 /* CPU core is ARM926EJ-S */ "	>> tmp.fil
-	;;
-
-	ap946es_config)
-	cpu="arm946es"
-	variant="Core module CM946E-S"
-	echo -n	"#define CONFIG_CM946E_S"		>> tmp.fil
-	echo	" 1 /* CPU core is ARM946E-S */ "	>> tmp.fil
-	;;
-
-	*)
-	echo "$0:: Unknown core module"
-	variant="unknown core module"
-	cpu="arm_intcm"
-	;;
-
-	esac
-fi
-
-case "$cpu" in
-	arm_intcm)
-	echo "/* Core module undefined/not ported */"	>> tmp.fil
-	echo "#define CONFIG_ARM_INTCM 1"		>> tmp.fil
-	echo -n	"#undef CONFIG_CM_MULTIPLE_SSRAM"	>> tmp.fil
-	echo -n	"	/* CM may not have "		>> tmp.fil
-	echo	"multiple SSRAM mapping */"		>> tmp.fil
-	echo -n	"#undef CONFIG_CM_SPD_DETECT "		>> tmp.fil
-	echo -n	" /* CM may not support SPD "		>> tmp.fil
-	echo	"query */"				>> tmp.fil
-	echo -n	"#undef CONFIG_CM_REMAP	"		>> tmp.fil
-	echo -n	" /* CM may not support "		>> tmp.fil
-	echo	"remapping */"				>> tmp.fil
-	echo -n	"#undef CONFIG_CM_INIT	"		>> tmp.fil
-	echo -n	" /* CM may not have	"		>> tmp.fil
-	echo	"initialization reg */"			>> tmp.fil
-	echo -n	"#undef CONFIG_CM_TCRAM	"		>> tmp.fil
-	echo	" /* CM may not have TCRAM */"		>> tmp.fil
-	echo -n	" /* May not be processor "		>> tmp.fil
-	echo	"without cache support */"		>> tmp.fil
-	echo	"#define CONFIG_SYS_NO_ICACHE 1"	>> tmp.fil
-	echo	"#define CONFIG_SYS_NO_DCACHE 1"	>> tmp.fil
-	;;
-
-	arm720t)
-	echo -n	" /* May not be processor "		>> tmp.fil
-	echo	"without cache support */"		>> tmp.fil
-	echo	"#define CONFIG_SYS_NO_ICACHE 1"	>> tmp.fil
-	echo	"#define CONFIG_SYS_NO_DCACHE 1"	>> tmp.fil
-	;;
-esac
-
-mkdir -p ${obj}include
-mkdir -p ${obj}board/armltd/integratorap
-mv tmp.fil ${obj}include/config.h
-# ---------------------------------------------------------
-# Complete the configuration
-# ---------------------------------------------------------
-$MKCONFIG -a integratorap arm $cpu integratorap armltd;
-echo "Variant:: $variant with core $cpu"
-
diff --git a/board/armltd/integratorcp/config.mk b/board/armltd/integratorcp/config.mk
deleted file mode 100644
index 25b79b3e79..0000000000
--- a/board/armltd/integratorcp/config.mk
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# image should be loaded at 0x01000000
-#
-
-TEXT_BASE = 0x01000000
diff --git a/board/armltd/integratorcp/flash.c b/board/armltd/integratorcp/flash.c
deleted file mode 100644
index 5059daeec9..0000000000
--- a/board/armltd/integratorcp/flash.c
+++ /dev/null
@@ -1,564 +0,0 @@
-/*
- * (C) Copyright 2004
- * Xiaogeng (Shawn) Jin, Agilent Technologies, xiaogeng_jin@agilent.com
- *
- * (C) Copyright 2001
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2001-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2003
- * Texas Instruments, <www.ti.com>
- * Kshitij Gupta <Kshitij@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <linux/byteorder/swab.h>
-
-#define DEBUG
-
-#define PHYS_FLASH_SECT_SIZE	0x00040000	/* 256 KB sectors (x2) */
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips */
-
-/* Board support for 1 or 2 flash devices */
-#define FLASH_PORT_WIDTH32
-#undef FLASH_PORT_WIDTH16
-
-#ifdef FLASH_PORT_WIDTH16
-#define FLASH_PORT_WIDTH	ushort
-#define FLASH_PORT_WIDTHV	vu_short
-#define SWAP(x)			__swab16(x)
-#else
-#define FLASH_PORT_WIDTH	ulong
-#define FLASH_PORT_WIDTHV	vu_long
-#define SWAP(x)			__swab32(x)
-#endif
-
-#define FPW	FLASH_PORT_WIDTH
-#define FPWV	FLASH_PORT_WIDTHV
-
-#define mb() __asm__ __volatile__ ("" : : : "memory")
-
-
-/* Flash Organization Structure */
-typedef struct OrgDef {
-	unsigned int sector_number;
-	unsigned int sector_size;
-} OrgDef;
-
-
-/* Flash Organizations */
-OrgDef OrgIntel_28F256L18T[] = {
-	{4, 32 * 1024},				/* 4 * 32kBytes sectors */
-	{255, 128 * 1024},			/* 255 * 128kBytes sectors */
-};
-
-/* CP control register base address */
-#define CPCR_BASE		0xCB000000
-#define CPCR_EXTRABANK		0x8
-#define CPCR_FLASHSIZE		0x4
-#define CPCR_FLWREN		0x2
-#define CPCR_FLVPPEN		0x1
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-unsigned long flash_init (void);
-static ulong flash_get_size (FPW * addr, flash_info_t * info);
-static int write_data (flash_info_t * info, ulong dest, FPW data);
-static void flash_get_offsets (ulong base, flash_info_t * info);
-void inline spin_wheel (void);
-void flash_print_info (flash_info_t * info);
-void flash_unprotect_sectors (FPWV * addr);
-int flash_erase (flash_info_t * info, int s_first, int s_last);
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt);
-
-/*-----------------------------------------------------------------------
- */
-unsigned long flash_init (void)
-{
-	int i, nbanks;
-	ulong size = 0;
-	vu_long *cpcr = (vu_long *)CPCR_BASE;
-
-	/* Check if there is an extra bank of flash */
-	if (cpcr[1] & CPCR_EXTRABANK)
-		nbanks = 2;
-	else
-		nbanks = 1;
-
-	if (nbanks > CONFIG_SYS_MAX_FLASH_BANKS)
-		nbanks = CONFIG_SYS_MAX_FLASH_BANKS;
-
-	/* Enable flash write */
-	cpcr[1] |= 3;
-
-	for (i = 0; i < nbanks; i++) {
-		flash_get_size ((FPW *)(CONFIG_SYS_FLASH_BASE + size), &flash_info[i]);
-		flash_get_offsets (CONFIG_SYS_FLASH_BASE + size, &flash_info[i]);
-		size += flash_info[i].size;
-	}
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
-	/* monitor protection */
-	flash_protect (FLAG_PROTECT_SET,
-		       CONFIG_SYS_MONITOR_BASE,
-		       CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]);
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-	/* ENV protection ON */
-	flash_protect(FLAG_PROTECT_SET,
-		      CONFIG_ENV_ADDR,
-		      CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
-		      &flash_info[0]);
-#endif
-
-	/* Protect SIB (0x24800000) and bootMonitor (0x24c00000) */
-	flash_protect (FLAG_PROTECT_SET,
-		       flash_info[0].start[62],
-		       flash_info[0].start[63] + PHYS_FLASH_SECT_SIZE - 1,
-		       &flash_info[0]);
-
-	return size;
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t * info)
-{
-	int i;
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		return;
-	}
-
-	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
-		for (i = 0; i < info->sector_count; i++) {
-			info->start[i] = base +	(i * PHYS_FLASH_SECT_SIZE);
-			info->protect[i] = 0;
-		}
-	}
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t * info)
-{
-	int i;
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf ("missing or unknown FLASH type\n");
-		return;
-	}
-
-	switch (info->flash_id & FLASH_VENDMASK) {
-	case FLASH_MAN_INTEL:
-		printf ("INTEL ");
-		break;
-	default:
-		printf ("Unknown Vendor ");
-		break;
-	}
-
-	/* Integrator CP board uses 28F640J3C or 28F128J3C parts,
-	 * which have the same device id numbers as 28F640J3A or
-	 * 28F128J3A
-	 */
-	switch (info->flash_id & FLASH_TYPEMASK) {
-	case FLASH_28F256L18T:
-		printf ("FLASH 28F256L18T\n");
-		break;
-	case FLASH_28F640J3A:
-		printf ("FLASH 28F640J3C\n");
-		break;
-	case FLASH_28F128J3A:
-		printf ("FLASH 28F128J3C\n");
-		break;
-	default:
-		printf ("Unknown Chip Type\n");
-		break;
-	}
-
-	printf ("  Size: %ld MB in %d Sectors\n",
-			info->size >> 20, info->sector_count);
-
-	printf ("  Sector Start Addresses:");
-	for (i = 0; i < info->sector_count; ++i) {
-		if ((i % 5) == 0)
-			printf ("\n   ");
-		printf (" %08lX%s",
-			info->start[i], info->protect[i] ? " (RO)" : "     ");
-	}
-	printf ("\n");
-	return;
-}
-
-/*
- * The following code cannot be run from FLASH!
- */
-static ulong flash_get_size (FPW * addr, flash_info_t * info)
-{
-	volatile FPW value;
-	vu_long *cpcr = (vu_long *)CPCR_BASE;
-	int nsects;
-
-	/* Check the flash size */
-	if (cpcr[1] & CPCR_FLASHSIZE)
-		nsects = 128;
-	else
-		nsects = 64;
-
-	if (nsects > CONFIG_SYS_MAX_FLASH_SECT)
-		nsects = CONFIG_SYS_MAX_FLASH_SECT;
-
-	/* Write auto select command: read Manufacturer ID */
-	addr[0x5555] = (FPW) 0x00AA00AA;
-	addr[0x2AAA] = (FPW) 0x00550055;
-	addr[0x5555] = (FPW) 0x00900090;
-
-	mb ();
-	value = addr[0];
-
-	switch (value) {
-
-	case (FPW) INTEL_MANUFACT:
-		info->flash_id = FLASH_MAN_INTEL;
-		break;
-
-	default:
-		info->flash_id = FLASH_UNKNOWN;
-		info->sector_count = 0;
-		info->size = 0;
-		addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
-		return (0); /* no or unknown flash */
-	}
-
-	mb ();
-	value = addr[1]; /* device ID */
-	switch (value) {
-
-	case (FPW) (INTEL_ID_28F256L18T):
-		info->flash_id += FLASH_28F256L18T;
-		info->sector_count = 259;
-		info->size = 0x02000000;
-		break;			/* => 32 MB */
-
-	case (FPW) (INTEL_ID_28F640J3A):
-		info->flash_id += FLASH_28F640J3A;
-		info->sector_count = nsects;
-		info->size = nsects * PHYS_FLASH_SECT_SIZE;
-		break;
-
-	case (FPW) (INTEL_ID_28F128J3A):
-		info->flash_id += FLASH_28F128J3A;
-		info->sector_count = nsects;
-		info->size = nsects * PHYS_FLASH_SECT_SIZE;
-		break;
-
-	default:
-		info->flash_id = FLASH_UNKNOWN;
-		break;
-	}
-
-	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
-		printf ("** ERROR: sector count %d > max (%d) **\n",
-				info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
-		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
-	}
-
-	addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
-
-	return (info->size);
-}
-
-
-/* unprotects a sector for write and erase
- * on some intel parts, this unprotects the entire chip, but it
- * wont hurt to call this additional times per sector...
- */
-void flash_unprotect_sectors (FPWV * addr)
-{
-	FPW status;
-
-	*addr = (FPW) 0x00500050;	/* clear status register */
-
-	/* this sends the clear lock bit command */
-	*addr = (FPW) 0x00600060;
-	*addr = (FPW) 0x00D000D0;
-
-	reset_timer_masked();
-	while (((status = *addr) & (FPW)0x00800080) != 0x00800080) {
-		if (get_timer_masked() > CONFIG_SYS_FLASH_ERASE_TOUT) {
-			printf("Timeout");
-			break;
-		}
-	}
-
-	*addr = (FPW) 0x00FF00FF;
-}
-
-
-/*-----------------------------------------------------------------------
- */
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
-	int flag, prot, sect;
-	ulong type;
-	int rcode = 0;
-
-	if ((s_first < 0) || (s_first > s_last)) {
-		if (info->flash_id == FLASH_UNKNOWN) {
-			printf ("- missing\n");
-		} else {
-			printf ("- no sectors to erase\n");
-		}
-		return 1;
-	}
-
-	type = (info->flash_id & FLASH_VENDMASK);
-	if ((type != FLASH_MAN_INTEL)) {
-		printf ("Can't erase unknown flash type %08lx - aborted\n",
-				info->flash_id);
-		return 1;
-	}
-
-	prot = 0;
-	for (sect = s_first; sect <= s_last; ++sect) {
-		if (info->protect[sect]) {
-			prot++;
-		}
-	}
-
-	if (prot) {
-		printf ("- Warning: %d protected sectors will not be erased!\n",
-				prot);
-	} else {
-		printf ("\n");
-	}
-
-	/* Start erase on unprotected sectors */
-	for (sect = s_first; sect <= s_last; sect++) {
-		if (info->protect[sect] == 0) {	/* not protected */
-			FPWV *addr = (FPWV *) (info->start[sect]);
-			FPW status;
-
-			printf ("Erasing sector %2d ... ", sect);
-
-			/* Disable interrupts which might cause a timeout here */
-			flag = disable_interrupts ();
-
-			/* flash_unprotect_sectors (addr); */
-
-			/* arm simple, non interrupt dependent timer */
-			reset_timer_masked ();
-
-			*addr = (FPW) 0x00500050; /* clear status register */
-			*addr = (FPW) 0x00200020; /* erase setup */
-			*addr = (FPW) 0x00D000D0; /* erase confirm */
-			mb();
-
-			udelay(1000); /* Let's wait 1 ms */
-
-			/* re-enable interrupts if necessary */
-			if (flag)
-				enable_interrupts();
-
-			while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
-				if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) {
-					*addr = (FPW)0x00700070;
-					status = *addr;
-					if ((status & (FPW) 0x00400040) == (FPW) 0x00400040) {
-						/* erase suspended? Resume it */
-						reset_timer_masked();
-						*addr = (FPW) 0x00D000D0;
-					} else {
-#ifdef DEBUG
-						printf ("Timeout,0x%08lx\n", status);
-#else
-						printf("Timeout\n");
-#endif
-
-						*addr = (FPW) 0x00500050;
-						*addr = (FPW) 0x00FF00FF; /* reset to read mode */
-						rcode = 1;
-						break;
-					}
-				}
-			}
-
-			*addr = (FPW) 0x00FF00FF; /* resest to read mode */
-			printf (" done\n");
-		}
-	}
-
-	return rcode;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- * 4 - Flash not identified
- */
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
-	ulong cp, wp;
-	FPW data;
-	int count, i, l, rc, port_width;
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		return 4;
-	}
-/* get lower word aligned address */
-#ifdef FLASH_PORT_WIDTH16
-	wp = (addr & ~1);
-	port_width = 2;
-#else
-	wp = (addr & ~3);
-	port_width = 4;
-#endif
-
-	/*
-	 * handle unaligned start bytes
-	 */
-	if ((l = addr - wp) != 0) {
-		data = 0;
-		for (i = 0, cp = wp; i < l; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *) cp);
-		}
-		for (; i < port_width && cnt > 0; ++i) {
-			data = (data << 8) | *src++;
-			--cnt;
-			++cp;
-		}
-		for (; cnt == 0 && i < port_width; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *) cp);
-		}
-
-		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
-			return (rc);
-		}
-		wp += port_width;
-	}
-
-	/*
-	 * handle word aligned part
-	 */
-	count = 0;
-	while (cnt >= port_width) {
-		data = 0;
-		for (i = 0; i < port_width; ++i) {
-			data = (data << 8) | *src++;
-		}
-		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
-			return (rc);
-		}
-		wp += port_width;
-		cnt -= port_width;
-		if (count++ > 0x800) {
-			spin_wheel ();
-			count = 0;
-		}
-	}
-
-	if (cnt == 0) {
-		return (0);
-	}
-
-	/*
-	 * handle unaligned tail bytes
-	 */
-	data = 0;
-	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
-		data = (data << 8) | *src++;
-		--cnt;
-	}
-	for (; i < port_width; ++i, ++cp) {
-		data = (data << 8) | (*(uchar *) cp);
-	}
-
-	return (write_data (info, wp, SWAP (data)));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word or halfword to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_data (flash_info_t * info, ulong dest, FPW data)
-{
-	FPWV *addr = (FPWV *) dest;
-	ulong status;
-	int flag;
-
-	/* Check if Flash is (sufficiently) erased */
-	if ((*addr & data) != data) {
-		printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr);
-		return (2);
-	}
-
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts ();
-
-	/* flash_unprotect_sectors (addr); */
-
-	*addr = (FPW) 0x00400040;	/* write setup */
-	*addr = data;
-
-	mb();
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts();
-
-	/* arm simple, non interrupt dependent timer */
-	reset_timer_masked ();
-
-	/* wait while polling the status register */
-	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
-		if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
-#ifdef DEBUG
-			*addr = (FPW) 0x00700070;
-			status = *addr;
-			printf("## status=0x%08lx, addr=0x%p\n", status, addr);
-#endif
-			*addr = (FPW) 0x00500050; /* clear status register cmd */
-			*addr = (FPW) 0x00FF00FF; /* restore read mode */
-			return (1);
-		}
-	}
-
-	*addr = (FPW) 0x00FF00FF; /* restore read mode */
-	return (0);
-}
-
-void inline spin_wheel (void)
-{
-	static int p = 0;
-	static char w[] = "\\/-";
-
-	printf ("\010%c", w[p]);
-	(++p == 3) ? (p = 0) : 0;
-}
diff --git a/board/armltd/integratorcp/lowlevel_init.S b/board/armltd/integratorcp/lowlevel_init.S
deleted file mode 100644
index 18f7d2eaeb..0000000000
--- a/board/armltd/integratorcp/lowlevel_init.S
+++ /dev/null
@@ -1,214 +0,0 @@
-/*
- * Board specific setup info
- *
- * (C) Copyright 2003, ARM Ltd.
- * Philippe Robin, <philippe.robin@arm.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-
-/* Reset using CM control register */
-.global reset_cpu
-reset_cpu:
-	mov	r0, #CM_BASE
-	ldr	r1,[r0,#OS_CTRL]
-	orr	r1,r1,#CMMASK_RESET
-	str	r1,[r0,#OS_CTRL]
-
-reset_failed:
-	b	reset_failed
-
-/* Set up the platform, once the cpu has been initialized */
-.globl lowlevel_init
-lowlevel_init:
-	/* If U-Boot has been run after the ARM boot monitor
-	 * then all the necessary actions have been done
-	 * otherwise we are running from user flash mapped to 0x00000000
-	 * --- DO NOT REMAP BEFORE THE CODE HAS BEEN RELOCATED --
-	 * Changes to the (possibly soft) reset defaults of the processor
-	 * itself should be performed in cpu/arm<>/start.S
-	 * This function affects only the core module or board settings
-	 */
-
-#ifdef CONFIG_CM_INIT
-	/* CM has an initialization register
-	 * - bits in it are wired into test-chip pins to force
-	 *   reset defaults
-	 * - may need to change its contents for U-Boot
-	 */
-
-	/* set the desired CM specific value */
-	mov	r2,#CMMASK_LOWVEC	/* Vectors at 0x00000000 for all */
-
-#if defined (CONFIG_CM10200E) || defined (CONFIG_CM10220E)
-	orr	r2,r2,#CMMASK_INIT_102
-#else
-
-#if	!defined (CONFIG_CM920T) && !defined (CONFIG_CM920T_ETM) && \
-	!defined (CONFIG_CM940T)
-	/* CMxx6 code	*/
-
-#ifdef	CONFIG_CM_MULTIPLE_SSRAM
-	/* set simple mapping			*/
-	and	r2,r2,#CMMASK_MAP_SIMPLE
-#endif /* #ifdef CONFIG_CM_MULTIPLE_SSRAM	*/
-
-#ifdef	CONFIG_CM_TCRAM
-	/* disable TCRAM			*/
-	and	r2,r2,#CMMASK_TCRAM_DISABLE
-#endif /* #ifdef CONFIG_CM_TCRAM		*/
-
-#if defined (CONFIG_CM926EJ_S) || defined (CONFIG_CM1026EJ_S) || \
-			defined (CONFIG_CM1136JF_S)
-
-	and	r2,r2,#CMMASK_LE
-
-#endif /* cpu with little endian initialization */
-
-	orr	r2,r2,#CMMASK_CMxx6_COMMON
-
-#endif /* CMxx6 code */
-
-#endif /* ARM102xxE value */
-
-	/* read CM_INIT		 */
-	mov	r0, #CM_BASE
-	ldr	r1, [r0, #OS_INIT]
-	/* check against desired bit setting */
-	and	r3,r1,r2
-	cmp	r3,r2
-	beq	init_reg_OK
-
-	/* lock for change */
-	mov	r3, #CMVAL_LOCK1
-	and	r3, r3, #CMVAL_LOCK2
-	str	r3, [r0, #OS_LOCK]
-	/* set desired value */
-	orr	r1,r1,r2
-	/* write & relock CM_INIT */
-	str	r1, [r0, #OS_INIT]
-	mov	r1, #CMVAL_UNLOCK
-	str	r1, [r0, #OS_LOCK]
-
-	/* soft reset so new values used */
-	b	reset_cpu
-
-init_reg_OK:
-
-#endif /* CONFIG_CM_INIT */
-
-	mov	pc, lr
-
-#ifdef	CONFIG_CM_SPD_DETECT
-	/* Fast memory is available for the DRAM data
-	 * - ensure it has been transferred, then summarize the data
-	 *	 into a CM register
-	 */
-.globl dram_query
-dram_query:
-	stmfd	r13!,{r4-r6,lr}
-	/* set up SDRAM info					*/
-	/* - based on example code from the CM User Guide */
-	mov	r0, #CM_BASE
-
-readspdbit:
-	ldr	r1, [r0, #OS_SDRAM]	/* read the SDRAM register */
-	and	r1, r1, #0x20		/* mask SPD bit (5)		 */
-	cmp	r1, #0x20		/* test if set			 */
-	bne	readspdbit
-
-setupsdram:
-	add	r0, r0, #OS_SPD		/* address the copy of the SDP data	*/
-	ldrb	r1, [r0, #3]		/* number of row address lines		*/
-	ldrb	r2, [r0, #4]		/* number of column address lines	*/
-	ldrb	r3, [r0, #5]		/* number of banks			*/
-	ldrb	r4, [r0, #31]		/* module bank density			*/
-	mul	r5, r4, r3		/* size of SDRAM (MB divided by 4)	*/
-	mov	r5, r5, ASL#2		/* size in MB				*/
-	mov	r0, #CM_BASE		/* reload for later code		*/
-	cmp	r5, #0x10		/* is it 16MB?				*/
-	bne	not16
-	mov	r6, #0x2		/* store size and CAS latency of 2	*/
-	b	writesize
-
-not16:
-	cmp	r5, #0x20		/* is it  32MB? */
-	bne	not32
-	mov	r6, #0x6
-	b	writesize
-
-not32:
-	cmp	r5, #0x40		/* is it  64MB? */
-	bne	not64
-	mov	r6, #0xa
-	b	writesize
-
-not64:
-	cmp	r5, #0x80		/* is it 128MB? */
-	bne	not128
-	mov	r6, #0xe
-	b	writesize
-
-not128:
-	/* if it is none of these sizes then it is either 256MB, or
-	 * there is no SDRAM fitted so default to 256MB
-	 */
-	mov	r6, #0x12
-
-writesize:
-	mov	r1, r1, ASL#8		/* row addr lines from SDRAM reg */
-	orr	r2, r1, r2, ASL#12	/* OR in column address lines	 */
-	orr	r3, r2, r3, ASL#16	/* OR in number of banks	 */
-	orr	r6, r6, r3		/* OR in size and CAS latency	 */
-	str	r6, [r0, #OS_SDRAM]	/* store SDRAM parameters	 */
-
-#endif /* #ifdef CONFIG_CM_SPD_DETECT */
-
-	ldmfd	r13!,{r4-r6,pc}			/* back to caller */
-
-#ifdef	CONFIG_CM_REMAP
-	/* CM remap bit is operational
-	 * - use it to map writeable memory at 0x00000000, in place of flash
-	 */
-.globl cm_remap
-cm_remap:
-	stmfd	r13!,{r4-r10,lr}
-
-	mov	r0, #CM_BASE
-	ldr	r1, [r0, #OS_CTRL]
-	orr	r1, r1, #CMMASK_REMAP	/* set remap and led bits */
-	str	r1, [r0, #OS_CTRL]
-
-	/* Now 0x00000000 is writeable, replace the vectors	*/
-	ldr	r0, =_start	/* r0 <- start of vectors	*/
-	ldr	r2, =_armboot_start	/* r2 <- past vectors	*/
-	sub	r1,r1,r1		/* destination 0x00000000	*/
-
-copy_vec:
-	ldmia	r0!, {r3-r10}		/* copy from source address [r0]	*/
-	stmia	r1!, {r3-r10}		/* copy to	 target address [r1]	*/
-	cmp	r0, r2			/* until source end address [r2]	*/
-	ble	copy_vec
-
-	ldmfd	r13!,{r4-r10,pc}	/* back to caller			*/
-
-#endif /* #ifdef CONFIG_CM_REMAP */
diff --git a/board/armltd/integratorcp/split_by_variant.sh b/board/armltd/integratorcp/split_by_variant.sh
deleted file mode 100755
index 13effef798..0000000000
--- a/board/armltd/integratorcp/split_by_variant.sh
+++ /dev/null
@@ -1,110 +0,0 @@
-#!/bin/sh
-# ---------------------------------------------------------
-# Set the platform defines
-# ---------------------------------------------------------
-echo -n "/* Integrator configuration implied "   > tmp.fil
-echo    " by Makefile target */"		>> tmp.fil
-echo -n "#define CONFIG_INTEGRATOR"		>> tmp.fil
-echo	 " /* Integrator board */"		>> tmp.fil
-echo -n "#define CONFIG_ARCH_CINTEGRATOR"	>> tmp.fil
-echo     " 1 /* Integrator/CP   */"		>> tmp.fil
-
-cpu="arm_intcm"
-variant="unknown core module"
-
-if [ "$1" = "" ]
-then
-	echo "$0:: No parameters - using arm_intcm"
-else
-	case "$1" in
-	ap966)
-	cpu="arm_intcm"
-	variant="unported core module CM966E-S"
-	;;
-
-	ap922_config)
-	cpu="arm_intcm"
-	variant="unported core module CM922T"
-	;;
-
-	integratorcp_config	|	\
-	cp_config)
-	cpu="arm_intcm"
-	variant="unspecified core module"
-	;;
-
-	cp922_XA10_config)
-	cpu="arm_intcm"
-	variant="unported core module CM922T_XA10"
-	echo -n "#define CONFIG_CM922T_XA10"		>> tmp.fil
-	echo    " 1 /* CPU core is ARM922T_XA10 */"	>> tmp.fil
-	;;
-
-	cp920t_config)
-	cpu="arm920t"
-	variant="Core module CM920T"
-	echo -n "#define CONFIG_CM920T"			>> tmp.fil
-	echo    " 1 /* CPU core is ARM920T */"		>> tmp.fil
-	;;
-
-	cp926ejs_config)
-	cpu="arm926ejs"
-	variant="Core module CM926EJ-S"
-	echo -n "#define CONFIG_CM926EJ_S"		>> tmp.fil
-	echo    " 1 /* CPU core is ARM926EJ-S */ "	>> tmp.fil
-	;;
-
-
-	cp946es_config)
-	cpu="arm946es"
-	variant="Core module CM946E-S"
-	echo -n "#define CONFIG_CM946E_S"		>> tmp.fil
-	echo    " 1 /* CPU core is ARM946E-S */ "	>> tmp.fil
-	;;
-
-	cp1136_config)
-	cpu="arm1136"
-	variant="Core module CM1136EJF-S"
-	echo -n "#define CONFIG_CM1136EJF_S"		>> tmp.fil
-	echo    " 1 /* CPU core is ARM1136JF-S */ "	>> tmp.fil
-	;;
-
-	*)
-	echo "$0:: Unknown core module"
-	variant="unknown core module"
-	cpu="arm_intcm"
-	;;
-
-	esac
-
-fi
-
-if [ "$cpu" = "arm_intcm" ]
-then
-	echo "/* Core module undefined/not ported */"	>> tmp.fil
-	echo "#define CONFIG_ARM_INTCM 1"		>> tmp.fil
-	echo -n "#undef CONFIG_CM_MULTIPLE_SSRAM"	>> tmp.fil
-	echo -n "  /* CM may not have "			>> tmp.fil
-	echo    "multiple SSRAM mapping */"		>> tmp.fil
-	echo -n "#undef CONFIG_CM_SPD_DETECT "		>> tmp.fil
-	echo -n " /* CM may not support SPD "		>> tmp.fil
-	echo    "query */"				>> tmp.fil
-	echo -n "#undef CONFIG_CM_REMAP  "		>> tmp.fil
-	echo -n " /* CM may not support "		>> tmp.fil
-	echo    "remapping */"				>> tmp.fil
-	echo -n "#undef CONFIG_CM_INIT  "		>> tmp.fil
-	echo -n " /* CM may not have  "			>> tmp.fil
-	echo    "initialization reg */"			>> tmp.fil
-	echo -n "#undef CONFIG_CM_TCRAM  "		>> tmp.fil
-	echo    " /* CM may not have TCRAM */"		>> tmp.fil
-fi
-
-mkdir -p ${obj}include
-mkdir -p ${obj}board/armltd/integratorcp
-mv tmp.fil ${obj}include/config.h
-# ---------------------------------------------------------
-# Complete the configuration
-# ---------------------------------------------------------
-$MKCONFIG -a integratorcp arm $cpu integratorcp armltd;
-echo "Variant:: $variant with core $cpu"
-
diff --git a/board/armltd/versatile/versatile.c b/board/armltd/versatile/versatile.c
index 0f35caa9be..197bc896ac 100644
--- a/board/armltd/versatile/versatile.c
+++ b/board/armltd/versatile/versatile.c
@@ -46,13 +46,6 @@ void show_boot_progress(int progress)
 
 #define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
 
-static inline void delay (unsigned long loops)
-{
-	__asm__ volatile ("1:\n"
-		"subs %0, %1, #1\n"
-		"bne 1b":"=r" (loops):"0" (loops));
-}
-
 /*
  * Miscellaneous platform dependent initialisations
  */
diff --git a/board/atmel/at91sam9260ek/at91sam9260ek.c b/board/atmel/at91sam9260ek/at91sam9260ek.c
index 6bd3b44f06..c10ad72534 100644
--- a/board/atmel/at91sam9260ek/at91sam9260ek.c
+++ b/board/atmel/at91sam9260ek/at91sam9260ek.c
@@ -86,6 +86,8 @@ static void at91sam9260ek_nand_hw_init(void)
 #ifdef CONFIG_MACB
 static void at91sam9260ek_macb_hw_init(void)
 {
+	unsigned long rstc;
+
 	/* Enable clock */
 	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC);
 
@@ -108,6 +110,8 @@ static void at91sam9260ek_macb_hw_init(void)
 	       pin_to_mask(AT91_PIN_PA28),
 	       pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
 
+	rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL;
+
 	/* Need to reset PHY -> 500ms reset */
 	at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
 				     (AT91_RSTC_ERSTL & (0x0D << 8)) |
@@ -120,7 +124,7 @@ static void at91sam9260ek_macb_hw_init(void)
 
 	/* Restore NRST value */
 	at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
-				     (AT91_RSTC_ERSTL & (0x0 << 8)) |
+				     (rstc) |
 				     AT91_RSTC_URSTEN);
 
 	/* Re-enable pull-up */
diff --git a/board/atmel/at91sam9263ek/Makefile b/board/atmel/at91sam9263ek/Makefile
index 013ed215f9..79ec45fd9f 100644
--- a/board/atmel/at91sam9263ek/Makefile
+++ b/board/atmel/at91sam9263ek/Makefile
@@ -33,9 +33,9 @@ COBJS-y += at91sam9263ek.o
 COBJS-y += led.o
 COBJS-$(CONFIG_HAS_DATAFLASH) += partition.o
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS-y))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
 
 $(LIB):	$(obj).depend $(OBJS) $(SOBJS)
 	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
diff --git a/board/atmel/at91sam9263ek/at91sam9263ek.c b/board/atmel/at91sam9263ek/at91sam9263ek.c
index 57d5c953f7..0b7065b715 100644
--- a/board/atmel/at91sam9263ek/at91sam9263ek.c
+++ b/board/atmel/at91sam9263ek/at91sam9263ek.c
@@ -91,6 +91,8 @@ static void at91sam9263ek_nand_hw_init(void)
 #ifdef CONFIG_MACB
 static void at91sam9263ek_macb_hw_init(void)
 {
+	unsigned long rstc;
+
 	/* Enable clock */
 	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC);
 
@@ -108,6 +110,8 @@ static void at91sam9263ek_macb_hw_init(void)
 	       pin_to_mask(AT91_PIN_PE26),
 	       pin_to_controller(AT91_PIN_PE0) + PIO_PUDR);
 
+	rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL;
+
 	/* Need to reset PHY -> 500ms reset */
 	at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
 				     (AT91_RSTC_ERSTL & (0x0D << 8)) |
@@ -120,7 +124,7 @@ static void at91sam9263ek_macb_hw_init(void)
 
 	/* Restore NRST value */
 	at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
-				     (AT91_RSTC_ERSTL & (0x0 << 8)) |
+				     (rstc) |
 				     AT91_RSTC_URSTEN);
 
 	/* Re-enable pull-up */
@@ -196,9 +200,16 @@ static void at91sam9263ek_lcd_hw_init(void)
 #include <nand.h>
 #include <version.h>
 
+#ifndef CONFIG_SYS_NO_FLASH
+extern flash_info_t flash_info[];
+#endif
+
 void lcd_show_board_info(void)
 {
 	ulong dram_size, nand_size;
+#ifndef CONFIG_SYS_NO_FLASH
+	ulong flash_size;
+#endif
 	int i;
 	char temp[32];
 
@@ -215,9 +226,19 @@ void lcd_show_board_info(void)
 	nand_size = 0;
 	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
 		nand_size += nand_info[i].size;
-	lcd_printf ("  %ld MB SDRAM, %ld MB NAND\n",
+#ifndef CONFIG_SYS_NO_FLASH
+	flash_size = 0;
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
+		flash_size += flash_info[i].size;
+#endif
+	lcd_printf ("  %ld MB SDRAM, %ld MB NAND",
 		dram_size >> 20,
 		nand_size >> 20 );
+#ifndef CONFIG_SYS_NO_FLASH
+	lcd_printf (",\n  %ld MB NOR",
+		flash_size >> 20);
+#endif
+	lcd_puts ("\n");
 }
 #endif /* CONFIG_LCD_INFO */
 #endif
diff --git a/board/esd/meesc/Makefile b/board/esd/meesc/Makefile
new file mode 100644
index 0000000000..2dd6b25c94
--- /dev/null
+++ b/board/esd/meesc/Makefile
@@ -0,0 +1,55 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian.pop@leadtechdesign.com>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS-y	+= $(BOARD).o
+COBJS-$(CONFIG_HAS_DATAFLASH) += partition.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/esd/meesc/config.mk b/board/esd/meesc/config.mk
new file mode 100644
index 0000000000..9ce161e55f
--- /dev/null
+++ b/board/esd/meesc/config.mk
@@ -0,0 +1 @@
+TEXT_BASE = 0x21f00000
diff --git a/board/esd/meesc/meesc.c b/board/esd/meesc/meesc.c
new file mode 100644
index 0000000000..636d0ed5f2
--- /dev/null
+++ b/board/esd/meesc/meesc.c
@@ -0,0 +1,198 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * (C) Copyright 2009
+ * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
+ * esd electronic system design gmbh <www.esd.eu>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/at91sam9263.h>
+#include <asm/arch/at91sam9_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/io.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+static int hw_rev = -1;	/* hardware revision */
+
+int get_hw_rev(void)
+{
+	if (hw_rev >= 0)
+		return hw_rev;
+
+	hw_rev = at91_get_gpio_value(AT91_PIN_PB19);
+	hw_rev |= at91_get_gpio_value(AT91_PIN_PB20) << 1;
+	hw_rev |= at91_get_gpio_value(AT91_PIN_PB21) << 2;
+	hw_rev |= at91_get_gpio_value(AT91_PIN_PB22) << 3;
+
+	if (hw_rev == 15)
+		hw_rev = 0;
+
+	return hw_rev;
+}
+
+#ifdef CONFIG_CMD_NAND
+static void meesc_nand_hw_init(void)
+{
+	unsigned long csa;
+
+	/* Enable CS3 */
+	csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
+	at91_sys_write(AT91_MATRIX_EBI0CSA,
+		csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+	at91_sys_write(AT91_SMC_SETUP(3),
+		AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
+		AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
+	at91_sys_write(AT91_SMC_PULSE(3),
+		AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
+		AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
+	at91_sys_write(AT91_SMC_CYCLE(3),
+		AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
+	at91_sys_write(AT91_SMC_MODE(3),
+		AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
+		AT91_SMC_EXNWMODE_DISABLE |
+#ifdef CONFIG_SYS_NAND_DBW_16
+		AT91_SMC_DBW_16 |
+#else /* CONFIG_SYS_NAND_DBW_8 */
+		AT91_SMC_DBW_8 |
+#endif
+		AT91_SMC_TDF_(2));
+
+	/* Configure RDY/BSY */
+	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+
+	/* Enable NandFlash */
+	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+}
+#endif /* CONFIG_CMD_NAND */
+
+#ifdef CONFIG_MACB
+static void meesc_macb_hw_init(void)
+{
+	/* Enable clock */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC);
+	at91_macb_hw_init();
+}
+#endif
+
+/*
+ * Static memory controller initialization to enable Beckhoff ET1100 EtherCAT
+ * controller debugging
+ * The ET1100 is located at physical address 0x70000000
+ * Its process memory is located at physical address 0x70001000
+ */
+static void meesc_ethercat_hw_init(void)
+{
+	/* Configure SMC EBI1_CS0 for EtherCAT */
+	at91_sys_write(AT91_SMC1_SETUP(0),
+		AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) |
+		AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
+	at91_sys_write(AT91_SMC1_PULSE(0),
+		AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(9) |
+		AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(9));
+	at91_sys_write(AT91_SMC1_CYCLE(0),
+		AT91_SMC_NWECYCLE_(10) | AT91_SMC_NRDCYCLE_(5));
+	/* Configure behavior at external wait signal, byte-select mode, 16 bit
+	data bus width, none data float wait states and TDF optimization */
+	at91_sys_write(AT91_SMC1_MODE(0),
+		AT91_SMC_READMODE | AT91_SMC_EXNWMODE_READY |
+		AT91_SMC_BAT_SELECT | AT91_SMC_DBW_16 | AT91_SMC_TDF_(0) |
+		AT91_SMC_TDFMODE);
+
+	/* Configure RDY/BSY */
+	at91_set_B_periph(AT91_PIN_PE20, 0);	/* EBI1_NWAIT */
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = get_ram_size((long *) PHYS_SDRAM, (1 << 27));
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_MACB
+	rc = macb_eth_initialize(0, (void *)AT91SAM9263_BASE_EMAC, 0x00);
+#endif
+	return rc;
+}
+
+int checkboard(void)
+{
+	char str[32];
+
+	puts("Board: esd CAN-EtherCAT Gateway");
+	if (getenv_r("serial#", str, sizeof(str)) > 0) {
+		puts(", serial# ");
+		puts(str);
+	}
+	printf("\nHardware-revision: 1.%d\n", get_hw_rev());
+	printf("Mach-type: %lu\n", gd->bd->bi_arch_number);
+	return 0;
+}
+
+int board_init(void)
+{
+	/* Peripheral Clock Enable Register */
+	at91_sys_write(AT91_PMC_PCER,	1 << AT91SAM9263_ID_PIOA |
+					1 << AT91SAM9263_ID_PIOB |
+					1 << AT91SAM9263_ID_PIOCDE);
+
+	/* arch number of MEESC-Board */
+	gd->bd->bi_arch_number = MACH_TYPE_MEESC;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	at91_serial_hw_init();
+#ifdef CONFIG_CMD_NAND
+	meesc_nand_hw_init();
+#endif
+	meesc_ethercat_hw_init();
+#ifdef CONFIG_HAS_DATAFLASH
+	at91_spi0_hw_init(1 << 0);
+#endif
+#ifdef CONFIG_MACB
+	meesc_macb_hw_init();
+#endif
+#ifdef CONFIG_AT91_CAN
+	at91_can_hw_init();
+#endif
+	return 0;
+}
diff --git a/board/esd/meesc/partition.c b/board/esd/meesc/partition.c
new file mode 100644
index 0000000000..df0e1db34f
--- /dev/null
+++ b/board/esd/meesc/partition.c
@@ -0,0 +1,37 @@
+/*
+ * (C) Copyright 2008
+ * Ulf Samuelsson <ulf@atmel.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#include <common.h>
+#include <config.h>
+#include <asm/hardware.h>
+#include <dataflash.h>
+
+AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
+
+struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
+	{CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0},	/* Logical adress, CS */
+};
+
+/* define the area offsets */
+dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
+	{0x00000000, 0x000041FF, FLAG_PROTECT_SET,   0, "Bootstrap"},
+	{0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
+	{0x00008400, 0x00041FFF, FLAG_PROTECT_SET,   0, "U-Boot"},
+};
diff --git a/board/armltd/integratorcp/Makefile b/board/freescale/mx31pdk/Makefile
index 92a1a07b03..d5d8f0475d 100644
--- a/board/armltd/integratorcp/Makefile
+++ b/board/freescale/mx31pdk/Makefile
@@ -1,4 +1,6 @@
 #
+# (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com>
+#
 # (C) Copyright 2000-2006
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
@@ -25,8 +27,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	:= integratorcp.o flash.o
-SOBJS	:= lowlevel_init.o
+COBJS	:= mx31pdk.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
diff --git a/board/freescale/mx31pdk/config.mk b/board/freescale/mx31pdk/config.mk
new file mode 100644
index 0000000000..dcaa09ff83
--- /dev/null
+++ b/board/freescale/mx31pdk/config.mk
@@ -0,0 +1,5 @@
+ifdef CONFIG_NAND_SPL
+TEXT_BASE = 0x87ec0000
+else
+TEXT_BASE = 0x87f00000
+endif
diff --git a/board/freescale/mx31pdk/lowlevel_init.S b/board/freescale/mx31pdk/lowlevel_init.S
new file mode 100644
index 0000000000..cd0503ec3a
--- /dev/null
+++ b/board/freescale/mx31pdk/lowlevel_init.S
@@ -0,0 +1,93 @@
+/*
+ * (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/mx31-regs.h>
+#include <asm/macro.h>
+
+.globl lowlevel_init
+lowlevel_init:
+	/* Also setup the Peripheral Port Remap register inside the core */
+	ldr	r0, =ARM_PPMRR      /* start from AIPS 2GB region */
+	mcr	p15, 0, r0, c15, c2, 4
+
+	write32	IPU_CONF, IPU_CONF_DI_EN
+	write32	CCM_CCMR, CCM_CCMR_SETUP
+
+	wait_timer	0x40000
+
+	write32	CCM_CCMR, CCM_CCMR_SETUP | CCMR_MPE
+	write32	CCM_CCMR, (CCM_CCMR_SETUP | CCMR_MPE) & ~CCMR_MDS
+
+	/* Set up clock to 532MHz */
+	write32	CCM_PDR0, CCM_PDR0_SETUP_532MHZ
+	write32	CCM_MPCTL, CCM_MPCTL_SETUP_532MHZ
+
+	write32	CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1)
+
+	/* Set up MX31 DDR pins */
+	write32	IOMUXC_SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B, 0
+	write32	IOMUXC_SW_PAD_CTL_CAS_SDWE_SDCKE0, 0
+	write32	IOMUXC_SW_PAD_CTL_BCLK_RW_RAS, 0
+	write32	IOMUXC_SW_PAD_CTL_CS2_CS3_CS4, 0x1000
+	write32	IOMUXC_SW_PAD_CTL_DQM3_EB0_EB1, 0
+	write32	IOMUXC_SW_PAD_CTL_DQM0_DQM1_DQM2, 0
+	write32	IOMUXC_SW_PAD_CTL_SD29_SD30_SD31, 0
+	write32	IOMUXC_SW_PAD_CTL_SD26_SD27_SD28, 0
+	write32	IOMUXC_SW_PAD_CTL_SD23_SD24_SD25, 0
+	write32	IOMUXC_SW_PAD_CTL_SD20_SD21_SD22, 0
+	write32	IOMUXC_SW_PAD_CTL_SD17_SD18_SD19, 0
+	write32	IOMUXC_SW_PAD_CTL_SD14_SD15_SD16, 0
+	write32	IOMUXC_SW_PAD_CTL_SD11_SD12_SD13, 0
+	write32	IOMUXC_SW_PAD_CTL_SD8_SD9_SD10, 0
+	write32	IOMUXC_SW_PAD_CTL_SD5_SD6_SD7, 0
+	write32	IOMUXC_SW_PAD_CTL_SD2_SD3_SD4, 0
+	write32	IOMUXC_SW_PAD_CTL_SDBA0_SD0_SD1, 0
+	write32	IOMUXC_SW_PAD_CTL_A24_A25_SDBA1, 0
+	write32	IOMUXC_SW_PAD_CTL_A21_A22_A23, 0
+	write32	IOMUXC_SW_PAD_CTL_A18_A19_A20, 0
+	write32	IOMUXC_SW_PAD_CTL_A15_A16_A17, 0
+	write32	IOMUXC_SW_PAD_CTL_A12_A13_A14, 0
+	write32	IOMUXC_SW_PAD_CTL_A10_MA10_A11, 0
+	write32	IOMUXC_SW_PAD_CTL_A7_A8_A9, 0
+	write32	IOMUXC_SW_PAD_CTL_A4_A5_A6, 0
+	write32	IOMUXC_SW_PAD_CTL_A1_A2_A3, 0
+	write32	IOMUXC_SW_PAD_CTL_VPG0_VPG1_A0, 0
+
+	/* Set up MX31 DDR Memory Controller */
+	write32	WEIM_ESDMISC, ESDMISC_MDDR_SETUP
+	write32	WEIM_ESDCFG0, ESDCFG0_MDDR_SETUP
+
+	/* Perform DDR init sequence */
+	write32	WEIM_ESDCTL0, ESDCTL_PRECHARGE
+	write32	CSD0_BASE | 0x0f00, 0x12344321
+	write32	WEIM_ESDCTL0, ESDCTL_AUTOREFRESH
+	write32	CSD0_BASE, 0x12344321
+	write32	CSD0_BASE, 0x12344321
+	write32	WEIM_ESDCTL0, ESDCTL_LOADMODEREG
+	write8	CSD0_BASE | 0x00000033, 0xda
+	write8	CSD0_BASE | 0x01000000, 0xff
+	write32	WEIM_ESDCTL0, ESDCTL_RW
+	write32	CSD0_BASE, 0xDEADBEEF
+	write32	WEIM_ESDMISC, ESDMISC_MDDR_RESET_DL
+
+	mov	pc, lr
diff --git a/board/freescale/mx31pdk/mx31pdk.c b/board/freescale/mx31pdk/mx31pdk.c
new file mode 100644
index 0000000000..6b60c17dca
--- /dev/null
+++ b/board/freescale/mx31pdk/mx31pdk.c
@@ -0,0 +1,63 @@
+/*
+ *
+ * (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com>
+ *
+ * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <asm/arch/mx31.h>
+#include <asm/arch/mx31-regs.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* CS5: CPLD incl. network controller */
+	__REG(CSCR_U(5)) = 0x0000d843;
+	__REG(CSCR_L(5)) = 0x22252521;
+	__REG(CSCR_A(5)) = 0x22220a00;
+
+	/* Setup UART1 and SPI2 pins */
+	mx31_uart1_hw_init();
+	mx31_spi2_hw_init();
+
+	gd->bd->bi_arch_number = MACH_TYPE_MX31_3DS; /* board id for linux */
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	printf("Board: i.MX31 MAX PDK (3DS)\n");
+	return 0;
+}
diff --git a/board/omap3/evm/evm.c b/board/omap3/evm/evm.c
index c008c2e4aa..5fd5efad9c 100644
--- a/board/omap3/evm/evm.c
+++ b/board/omap3/evm/evm.c
@@ -92,17 +92,17 @@ void set_muxconf_regs(void)
 static void setup_net_chip(void)
 {
 	gpio_t *gpio3_base = (gpio_t *)OMAP34XX_GPIO3_BASE;
-	gpmc_csx_t *gpmc_cs6_base = (gpmc_csx_t *)GPMC_CONFIG_CS6_BASE;
+	gpmc_csx_t *gpmc_cs5_base = (gpmc_csx_t *)GPMC_CONFIG_CS5_BASE;
 	ctrl_t *ctrl_base = (ctrl_t *)OMAP34XX_CTRL_BASE;
 
 	/* Configure GPMC registers */
-	writel(NET_GPMC_CONFIG1, &gpmc_cs6_base->config1);
-	writel(NET_GPMC_CONFIG2, &gpmc_cs6_base->config2);
-	writel(NET_GPMC_CONFIG3, &gpmc_cs6_base->config3);
-	writel(NET_GPMC_CONFIG4, &gpmc_cs6_base->config4);
-	writel(NET_GPMC_CONFIG5, &gpmc_cs6_base->config5);
-	writel(NET_GPMC_CONFIG6, &gpmc_cs6_base->config6);
-	writel(NET_GPMC_CONFIG7, &gpmc_cs6_base->config7);
+	writel(NET_GPMC_CONFIG1, &gpmc_cs5_base->config1);
+	writel(NET_GPMC_CONFIG2, &gpmc_cs5_base->config2);
+	writel(NET_GPMC_CONFIG3, &gpmc_cs5_base->config3);
+	writel(NET_GPMC_CONFIG4, &gpmc_cs5_base->config4);
+	writel(NET_GPMC_CONFIG5, &gpmc_cs5_base->config5);
+	writel(NET_GPMC_CONFIG6, &gpmc_cs5_base->config6);
+	writel(NET_GPMC_CONFIG7, &gpmc_cs5_base->config7);
 
 	/* Enable off mode for NWE in PADCONF_GPMC_NWE register */
 	writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
diff --git a/board/ronetix/pm9261/Makefile b/board/ronetix/pm9261/Makefile
new file mode 100644
index 0000000000..2e065a2bc9
--- /dev/null
+++ b/board/ronetix/pm9261/Makefile
@@ -0,0 +1,57 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian.pop@leadtechdesign.com>
+# Lead Tech Design <www.leadtechdesign.com>
+# Ilko Iliev <www.ronetix.at>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS-y += $(BOARD).o
+COBJS-y += led.o
+COBJS-$(CONFIG_HAS_DATAFLASH) += partition.o
+
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y) $(SOBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/ronetix/pm9261/config.mk b/board/ronetix/pm9261/config.mk
new file mode 100644
index 0000000000..71854192f8
--- /dev/null
+++ b/board/ronetix/pm9261/config.mk
@@ -0,0 +1 @@
+TEXT_BASE = 0x23f00000
\ No newline at end of file
diff --git a/board/ronetix/pm9261/led.c b/board/ronetix/pm9261/led.c
new file mode 100644
index 0000000000..396c3e7340
--- /dev/null
+++ b/board/ronetix/pm9261/led.c
@@ -0,0 +1,44 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ * Ilko Iliev <www.ronetix.at>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/at91sam9261.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/io.h>
+
+void coloured_LED_init(void)
+{
+	/* Enable clock */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOC);
+
+	at91_set_gpio_output(CONFIG_RED_LED, 1);
+	at91_set_gpio_output(CONFIG_GREEN_LED, 1);
+	at91_set_gpio_output(CONFIG_YELLOW_LED, 1);
+
+	at91_set_gpio_value(CONFIG_RED_LED, 0);
+	at91_set_gpio_value(CONFIG_GREEN_LED, 1);
+	at91_set_gpio_value(CONFIG_YELLOW_LED, 1);
+}
diff --git a/board/ronetix/pm9261/partition.c b/board/ronetix/pm9261/partition.c
new file mode 100644
index 0000000000..cc6cbef1fc
--- /dev/null
+++ b/board/ronetix/pm9261/partition.c
@@ -0,0 +1,47 @@
+/*
+ * (C) Copyright 2008
+ * Ulf Samuelsson <ulf@atmel.com>
+ * Ilko Iliev <www.ronetix.at>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#include <common.h>
+#include <config.h>
+#include <asm/hardware.h>
+#include <dataflash.h>
+
+AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
+
+struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
+	{CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0},	/* Logical adress, CS */
+};
+
+/*define the area offsets*/
+#ifdef CONFIG_SYS_USE_DATAFLASH
+dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
+	{0x00000000, 0x000041FF, FLAG_PROTECT_SET,   0, "Bootstrap"},
+	{0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
+	{0x00008400, 0x00041FFF, FLAG_PROTECT_SET,   0, "U-Boot"},
+	{0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0,	"Kernel"},
+	{0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0,	"FS"},
+};
+#else
+dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
+	{0x00000000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, ""},
+};
+
+#endif
diff --git a/board/ronetix/pm9261/pm9261.c b/board/ronetix/pm9261/pm9261.c
new file mode 100644
index 0000000000..46948546ae
--- /dev/null
+++ b/board/ronetix/pm9261/pm9261.c
@@ -0,0 +1,288 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
+ * Copyright (C) 2009 Jean-Christopher PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/sizes.h>
+#include <asm/arch/at91sam9261.h>
+#include <asm/arch/at91sam9261_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/io.h>
+#include <asm/arch/hardware.h>
+#include <lcd.h>
+#include <atmel_lcdc.h>
+#include <dataflash.h>
+#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000)
+#include <net.h>
+#endif
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+#ifdef CONFIG_CMD_NAND
+static void pm9261_nand_hw_init(void)
+{
+	unsigned long csa;
+
+	/* Enable CS3 */
+	csa = at91_sys_read(AT91_MATRIX_EBICSA);
+	at91_sys_write(AT91_MATRIX_EBICSA,
+		       csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+	at91_sys_write(AT91_SMC_SETUP(3),
+		       AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
+		       AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
+	at91_sys_write(AT91_SMC_PULSE(3),
+		       AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
+		       AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
+	at91_sys_write(AT91_SMC_CYCLE(3),
+		       AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
+	at91_sys_write(AT91_SMC_MODE(3),
+		       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
+		       AT91_SMC_EXNWMODE_DISABLE |
+#ifdef CONFIG_SYS_NAND_DBW_16
+		       AT91_SMC_DBW_16 |
+#else /* CONFIG_SYS_NAND_DBW_8 */
+		       AT91_SMC_DBW_8 |
+#endif
+		       AT91_SMC_TDF_(2));
+
+	/* Configure RDY/BSY */
+	at91_set_gpio_input(AT91_PIN_PA16, 1);
+
+	/* Enable NandFlash */
+	at91_set_gpio_output(AT91_PIN_PC14, 1);
+
+	at91_set_A_periph(AT91_PIN_PC0, 0);	/* NANDOE */
+	at91_set_A_periph(AT91_PIN_PC1, 0);	/* NANDWE */
+}
+#endif
+
+
+#ifdef CONFIG_DRIVER_DM9000
+static void pm9261_dm9000_hw_init(void)
+{
+	/* Configure SMC CS2 for DM9000 */
+	at91_sys_write(AT91_SMC_SETUP(2),
+		       AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) |
+		       AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0));
+	at91_sys_write(AT91_SMC_PULSE(2),
+		       AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(8) |
+		       AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(8));
+	at91_sys_write(AT91_SMC_CYCLE(2),
+		       AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16));
+	at91_sys_write(AT91_SMC_MODE(2),
+		       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
+		       AT91_SMC_EXNWMODE_DISABLE |
+		       AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16 |
+		       AT91_SMC_TDF_(1));
+
+	/* Configure Interrupt pin as input, no pull-up */
+	at91_set_gpio_input(AT91_PIN_PA24, 0);
+}
+#endif
+
+#ifdef CONFIG_LCD
+vidinfo_t panel_info = {
+	vl_col:		240,
+	vl_row:		320,
+	vl_clk:		4965000,
+	vl_sync:	ATMEL_LCDC_INVLINE_INVERTED |
+			ATMEL_LCDC_INVFRAME_INVERTED,
+	vl_bpix:	3,
+	vl_tft:		1,
+	vl_hsync_len:	5,
+	vl_left_margin:	1,
+	vl_right_margin:33,
+	vl_vsync_len:	1,
+	vl_upper_margin:1,
+	vl_lower_margin:0,
+	mmio:		AT91SAM9261_LCDC_BASE,
+};
+
+void lcd_enable(void)
+{
+	at91_set_gpio_value(AT91_PIN_PA22, 0);  /* power up */
+}
+
+void lcd_disable(void)
+{
+	at91_set_gpio_value(AT91_PIN_PA22, 1);  /* power down */
+}
+
+static void pm9261_lcd_hw_init(void)
+{
+	at91_set_A_periph(AT91_PIN_PB1, 0);	/* LCDHSYNC */
+	at91_set_A_periph(AT91_PIN_PB2, 0);	/* LCDDOTCK */
+	at91_set_A_periph(AT91_PIN_PB3, 0);	/* LCDDEN */
+	at91_set_A_periph(AT91_PIN_PB4, 0);	/* LCDCC */
+	at91_set_A_periph(AT91_PIN_PB7, 0);	/* LCDD2 */
+	at91_set_A_periph(AT91_PIN_PB8, 0);	/* LCDD3 */
+	at91_set_A_periph(AT91_PIN_PB9, 0);	/* LCDD4 */
+	at91_set_A_periph(AT91_PIN_PB10, 0);	/* LCDD5 */
+	at91_set_A_periph(AT91_PIN_PB11, 0);	/* LCDD6 */
+	at91_set_A_periph(AT91_PIN_PB12, 0);	/* LCDD7 */
+	at91_set_A_periph(AT91_PIN_PB15, 0);	/* LCDD10 */
+	at91_set_A_periph(AT91_PIN_PB16, 0);	/* LCDD11 */
+	at91_set_A_periph(AT91_PIN_PB17, 0);	/* LCDD12 */
+	at91_set_A_periph(AT91_PIN_PB18, 0);	/* LCDD13 */
+	at91_set_A_periph(AT91_PIN_PB19, 0);	/* LCDD14 */
+	at91_set_A_periph(AT91_PIN_PB20, 0);	/* LCDD15 */
+	at91_set_B_periph(AT91_PIN_PB23, 0);	/* LCDD18 */
+	at91_set_B_periph(AT91_PIN_PB24, 0);	/* LCDD19 */
+	at91_set_B_periph(AT91_PIN_PB25, 0);	/* LCDD20 */
+	at91_set_B_periph(AT91_PIN_PB26, 0);	/* LCDD21 */
+	at91_set_B_periph(AT91_PIN_PB27, 0);	/* LCDD22 */
+	at91_set_B_periph(AT91_PIN_PB28, 0);	/* LCDD23 */
+
+	at91_sys_write(AT91_PMC_SCER, AT91_PMC_HCK1);
+
+	gd->fb_base = AT91SAM9261_SRAM_BASE;
+}
+
+#ifdef CONFIG_LCD_INFO
+#include <nand.h>
+#include <version.h>
+
+extern flash_info_t flash_info[];
+
+void lcd_show_board_info(void)
+{
+	ulong dram_size, nand_size, flash_size, dataflash_size;
+	int i;
+	char temp[32];
+
+	lcd_printf ("%s\n", U_BOOT_VERSION);
+	lcd_printf ("(C) 2009 Ronetix GmbH\n");
+	lcd_printf ("support@ronetix.at\n");
+	lcd_printf ("%s CPU at %s MHz",
+		AT91_CPU_NAME,
+		strmhz(temp, get_cpu_clk_rate()));
+
+	dram_size = 0;
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+		dram_size += gd->bd->bi_dram[i].size;
+
+	nand_size = 0;
+	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
+		nand_size += nand_info[i].size;
+
+	flash_size = 0;
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
+		flash_size += flash_info[i].size;
+
+	dataflash_size = 0;
+	for (i = 0; i < CONFIG_SYS_MAX_DATAFLASH_BANKS; i++)
+		dataflash_size += (unsigned int) dataflash_info[i].Device.pages_number *
+				dataflash_info[i].Device.pages_size;
+
+	lcd_printf ("%ld MB SDRAM, %ld MB NAND\n%ld MB NOR Flash\n"
+			"%ld MB DataFlash\n",
+		dram_size >> 20,
+		nand_size >> 20,
+		flash_size >> 20,
+		dataflash_size >> 20);
+}
+#endif /* CONFIG_LCD_INFO */
+
+#endif /* CONFIG_LCD */
+
+int board_init(void)
+{
+	/* Enable Ctrlc */
+	console_init_f();
+
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOA);
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOC);
+
+	/* arch number of PM9261-Board */
+	gd->bd->bi_arch_number = MACH_TYPE_PM9261;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	at91_serial_hw_init();
+#ifdef CONFIG_CMD_NAND
+	pm9261_nand_hw_init();
+#endif
+#ifdef CONFIG_HAS_DATAFLASH
+	at91_spi0_hw_init(1 << 0);
+#endif
+#ifdef CONFIG_DRIVER_DM9000
+	pm9261_dm9000_hw_init();
+#endif
+#ifdef CONFIG_LCD
+	pm9261_lcd_hw_init();
+#endif
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+	return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+void reset_phy(void)
+{
+#ifdef CONFIG_DRIVER_DM9000
+	/*
+	 * Initialize ethernet HW addr prior to starting Linux,
+	 * needed for nfsroot
+	 */
+	eth_init(gd->bd);
+#endif
+}
+#endif
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard (void)
+{
+	char buf[32];
+
+	printf ("Board : Ronetix PM9261\n");
+	printf ("Crystal frequency: %8s MHz\n",
+					strmhz(buf, get_main_clk_rate()));
+	printf ("CPU clock        : %8s MHz\n",
+					strmhz(buf, get_cpu_clk_rate()));
+	printf ("Master clock     : %8s MHz\n",
+					strmhz(buf, get_mck_clk_rate()));
+
+	return 0;
+}
+#endif
diff --git a/board/ronetix/pm9263/Makefile b/board/ronetix/pm9263/Makefile
index 270abd801f..ebc2adfa3d 100644
--- a/board/ronetix/pm9263/Makefile
+++ b/board/ronetix/pm9263/Makefile
@@ -34,10 +34,6 @@ COBJS-y += pm9263.o
 COBJS-y += led.o
 COBJS-$(CONFIG_HAS_DATAFLASH) += partition.o
 
-ifndef CONFIG_SKIP_LOWLEVEL_INIT
-SOBJS-y	:= lowlevel_init.o
-endif
-
 SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS-y) $(SOBJS-y))
 SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
diff --git a/board/ronetix/pm9263/lowlevel_init.S b/board/ronetix/pm9263/lowlevel_init.S
deleted file mode 100644
index c048c91096..0000000000
--- a/board/ronetix/pm9263/lowlevel_init.S
+++ /dev/null
@@ -1,279 +0,0 @@
-/*
- * Memory Setup stuff - taken from blob memsetup.S
- *
- * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
- *		       Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
- *
- * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
- * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_pio.h>
-#include <asm/arch/at91_rstc.h>
-#include <asm/arch/at91_wdt.h>
-#include <asm/arch/at91sam9_sdramc.h>
-#include <asm/arch/at91sam9_smc.h>
-#include <asm/arch/at91sam9263_matrix.h>
-
-_TEXT_BASE:
-	.word	TEXT_BASE
-
-.globl lowlevel_init
-.type lowlevel_init,function
-lowlevel_init:
-
-	mov	r5, pc		/* r5 = POS1 + 4 current */
-POS1:
-	ldr	r0, =POS1	/* r0 = POS1 compile */
-	ldr	r2, _TEXT_BASE
-	sub	r0, r0, r2	/* r0 = POS1-_TEXT_BASE (POS1 relative) */
-	sub	r5, r5, r0	/* r0 = TEXT_BASE-1 */
-	sub	r5, r5, #4	/* r1 = text base - current */
-
-	/* memory control configuration 1 */
-	ldr	r0, =SMRDATA
-	ldr	r2, =SMRDATA1
-	ldr	r1, _TEXT_BASE
-	sub	r0, r0, r1
-	sub	r2, r2, r1
-	add	r0, r0, r5
-	add	r2, r2, r5
-0:
-	/* the address */
-	ldr	r1, [r0], #4
-	/* the value */
-	ldr	r3, [r0], #4
-	str	r3, [r1]
-	cmp	r2, r0
-	bne	0b
-
-/* ----------------------------------------------------------------------------
- * PMC Init Step 1.
- * ----------------------------------------------------------------------------
- * - Check if the PLL is already initialized
- * ----------------------------------------------------------------------------
- */
-	ldr	r1, =(AT91_BASE_SYS + AT91_PMC_MCKR)
-	ldr	r0, [r1]
-	and	r0, r0, #3
-	cmp	r0, #0
-	bne	PLL_setup_end
-
-/* ---------------------------------------------------------------------------
- * - Enable the Main Oscillator
- * ---------------------------------------------------------------------------
- */
-	ldr	r1, =(AT91_BASE_SYS + AT91_CKGR_MOR)
-	ldr	r2, =(AT91_BASE_SYS + AT91_PMC_SR)
-	ldr	r0, =0x0000FF01
-	str	r0, [r1]	/* Enable main oscillator, OSCOUNT = 0xFF */
-
-	/* Reading the PMC Status to detect when the Main Oscillator is enabled */
-	mov	r4, #AT91_PMC_MOSCS
-MOSCS_Loop:
-	ldr	r3, [r2]
-	and	r3, r4, r3
-	cmp	r3, #AT91_PMC_MOSCS
-	bne	MOSCS_Loop
-
-/* ----------------------------------------------------------------------------
- * PMC Init Step 2.
- * ----------------------------------------------------------------------------
- * Setup PLLA
- * ----------------------------------------------------------------------------
- */
-	ldr	r1, =(AT91_BASE_SYS + AT91_CKGR_PLLAR)
-	ldr	r0, =CONFIG_SYS_PLLAR_VAL
-	str	r0, [r1]
-
-	/* Reading the PMC Status register to detect when the PLLA is locked */
-	mov	r4, #AT91_PMC_LOCKA
-MOSCS_Loop1:
-	ldr	r3, [r2]
-	and	r3, r4, r3
-	cmp	r3, #AT91_PMC_LOCKA
-	bne	MOSCS_Loop1
-
-/* ----------------------------------------------------------------------------
- * PMC Init Step 3.
- * ----------------------------------------------------------------------------
- * - Switch on the Main Oscillator 18.432 MHz
- * ----------------------------------------------------------------------------
- */
-	ldr	r1, =(AT91_BASE_SYS + AT91_PMC_MCKR)
-
-	/* -Master Clock Controller register PMC_MCKR */
-	ldr	r0, =CONFIG_SYS_MCKR1_VAL
-	str	r0, [r1]
-
-	/* Reading the PMC Status to detect when the Master clock is ready */
-	mov	r4, #AT91_PMC_MCKRDY
-MCKRDY_Loop:
-	ldr	r3, [r2]
-	and	r3, r4, r3
-	cmp	r3, #AT91_PMC_MCKRDY
-	bne	MCKRDY_Loop
-
-	ldr	r0, =CONFIG_SYS_MCKR2_VAL
-	str	r0, [r1]
-
-	/* Reading the PMC Status to detect when the Master clock is ready */
-	mov	r4, #AT91_PMC_MCKRDY
-MCKRDY_Loop1:
-	ldr	r3, [r2]
-	and	r3, r4, r3
-	cmp	r3, #AT91_PMC_MCKRDY
-	bne	MCKRDY_Loop1
-
-PLL_setup_end:
-
-/* ----------------------------------------------------------------------------
- * - memory control configuration 2
- * ----------------------------------------------------------------------------
- */
-	ldr	r0, =(AT91_BASE_SYS + AT91_SDRAMC_TR)
-	ldr	r1, [r0]
-	cmp	r1, #0
-	bne	SDRAM_setup_end
-
-	ldr	r0, =SMRDATA1
-	ldr	r2, =SMRDATA2
-	ldr	r1, _TEXT_BASE
-	sub	r0, r0, r1
-	sub	r2, r2, r1
-	add	r0, r0, r5
-	add	r2, r2, r5
-
-2:
-	/* the address */
-	ldr	r1, [r0], #4
-	/* the value */
-	ldr	r3, [r0], #4
-	str	r3, [r1]
-	cmp	r2, r0
-	bne	2b
-
-SDRAM_setup_end:
-	/* everything is fine now */
-	mov	pc, lr
-
-	.ltorg
-
-SMRDATA:
-	.word (AT91_BASE_SYS + AT91_WDT_MR)
-	.word CONFIG_SYS_WDTC_WDMR_VAL
-
-	.word (AT91_BASE_SYS + AT91_PIOD + PIO_PDR)
-	.word CONFIG_SYS_PIOD_PDR_VAL1
-	.word (AT91_BASE_SYS + AT91_PIOD + PIO_PUDR)
-	.word CONFIG_SYS_PIOD_PPUDR_VAL
-	.word (AT91_BASE_SYS + AT91_PIOD + PIO_ASR)
-	.word CONFIG_SYS_PIOD_PPUDR_VAL
-
-	.word (AT91_BASE_SYS + AT91_MATRIX_EBI0CSA)
-	.word CONFIG_SYS_MATRIX_EBI0CSA_VAL
-	.word (AT91_BASE_SYS + AT91_MATRIX_EBI1CSA)
-	.word CONFIG_SYS_MATRIX_EBI1CSA_VAL
-
-	/* flash */
-	.word (AT91_BASE_SYS + AT91_SMC_MODE(0))
-	.word CONFIG_SYS_SMC0_CTRL0_VAL
-
-	.word (AT91_BASE_SYS + AT91_SMC_CYCLE(0))
-	.word CONFIG_SYS_SMC0_CYCLE0_VAL
-
-	.word (AT91_BASE_SYS + AT91_SMC_PULSE(0))
-	.word CONFIG_SYS_SMC0_PULSE0_VAL
-
-	.word (AT91_BASE_SYS + AT91_SMC_SETUP(0))
-	.word CONFIG_SYS_SMC0_SETUP0_VAL
-
-	/* PSRAM */
-	.word (AT91_BASE_SYS + AT91_SMC1_MODE(0))
-	.word CONFIG_SYS_SMC1_CTRL0_VAL
-
-	.word (AT91_BASE_SYS + AT91_SMC1_CYCLE(0))
-	.word CONFIG_SYS_SMC1_CYCLE0_VAL
-
-	.word (AT91_BASE_SYS + AT91_SMC1_PULSE(0))
-	.word CONFIG_SYS_SMC1_PULSE0_VAL
-
-	.word (AT91_BASE_SYS + AT91_SMC1_SETUP(0))
-	.word CONFIG_SYS_SMC1_SETUP0_VAL
-
-SMRDATA1:
-	.word (AT91_BASE_SYS + AT91_SDRAMC_MR)
-	.word CONFIG_SYS_SDRC_MR_VAL1
-	.word (AT91_BASE_SYS + AT91_SDRAMC_TR)
-	.word CONFIG_SYS_SDRC_TR_VAL1
-	.word (AT91_BASE_SYS + AT91_SDRAMC_CR)
-	.word CONFIG_SYS_SDRC_CR_VAL
-	.word (AT91_BASE_SYS + AT91_SDRAMC_MDR)
-	.word CONFIG_SYS_SDRC_MDR_VAL
-	.word (AT91_BASE_SYS + AT91_SDRAMC_MR)
-	.word CONFIG_SYS_SDRC_MR_VAL2
-	.word AT91_SDRAM_BASE
-	.word CONFIG_SYS_SDRAM_VAL1
-	.word (AT91_BASE_SYS + AT91_SDRAMC_MR)
-	.word CONFIG_SYS_SDRC_MR_VAL3
-	.word AT91_SDRAM_BASE
-	.word CONFIG_SYS_SDRAM_VAL2
-	.word AT91_SDRAM_BASE
-	.word CONFIG_SYS_SDRAM_VAL3
-	.word AT91_SDRAM_BASE
-	.word CONFIG_SYS_SDRAM_VAL4
-	.word AT91_SDRAM_BASE
-	.word CONFIG_SYS_SDRAM_VAL5
-	.word AT91_SDRAM_BASE
-	.word CONFIG_SYS_SDRAM_VAL6
-	.word AT91_SDRAM_BASE
-	.word CONFIG_SYS_SDRAM_VAL7
-	.word AT91_SDRAM_BASE
-	.word CONFIG_SYS_SDRAM_VAL8
-	.word AT91_SDRAM_BASE
-	.word CONFIG_SYS_SDRAM_VAL9
-	.word (AT91_BASE_SYS + AT91_SDRAMC_MR)
-	.word CONFIG_SYS_SDRC_MR_VAL4
-	.word AT91_SDRAM_BASE
-	.word CONFIG_SYS_SDRAM_VAL10
-	.word (AT91_BASE_SYS + AT91_SDRAMC_MR)
-	.word CONFIG_SYS_SDRC_MR_VAL5
-	.word AT91_SDRAM_BASE
-	.word CONFIG_SYS_SDRAM_VAL11
-	.word (AT91_BASE_SYS + AT91_SDRAMC_TR)
-	.word CONFIG_SYS_SDRC_TR_VAL2
-	.word AT91_SDRAM_BASE
-	.word CONFIG_SYS_SDRAM_VAL12
-	/* User reset enable*/
-	.word (AT91_BASE_SYS + AT91_RSTC_MR)
-	.word CONFIG_SYS_RSTC_RMR_VAL
-#ifdef CONFIG_SYS_MATRIX_MCFG_REMAP
-	/* MATRIX_MCFG - REMAP all masters */
-	.word (AT91_BASE_SYS + AT91_MATRIX_MCFG0)
-	.word 0x1FF
-#endif
-
-SMRDATA2:
-	.word 0
diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c
index d2598a0680..29555f8db3 100644
--- a/board/ronetix/pm9263/pm9263.c
+++ b/board/ronetix/pm9263/pm9263.c
@@ -165,6 +165,27 @@ void lcd_disable(void)
 static int pm9263_lcd_hw_psram_init(void)
 {
 	volatile uint16_t x;
+	unsigned long csa;
+
+	/* Enable CS3  3.3v, no pull-ups */
+	csa = at91_sys_read(AT91_MATRIX_EBI1CSA);
+	at91_sys_write(AT91_MATRIX_EBI1CSA,
+		       csa | AT91_MATRIX_EBI1_DBPUC |
+		       AT91_MATRIX_EBI1_VDDIOMSEL_3_3V);
+
+	/* Configure SMC1 CS0 for PSRAM - 16-bit */
+	at91_sys_write(AT91_SMC1_SETUP(0),
+		       AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) |
+		       AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
+	at91_sys_write(AT91_SMC1_PULSE(0),
+		       AT91_SMC_NWEPULSE_(7) | AT91_SMC_NCS_WRPULSE_(7) |
+		       AT91_SMC_NRDPULSE_(2) | AT91_SMC_NCS_RDPULSE_(7));
+	at91_sys_write(AT91_SMC1_CYCLE(0),
+		       AT91_SMC_NWECYCLE_(8) | AT91_SMC_NRDCYCLE_(8));
+	at91_sys_write(AT91_SMC1_MODE(0),
+		       AT91_SMC_DBW_16 |
+		       AT91_SMC_PMEN |
+		       AT91_SMC_PS_32);
 
 	/* setup PB29 as output */
 	at91_set_gpio_output(PSRAM_CRE_PIN, 1);
@@ -218,7 +239,7 @@ static int pm9263_lcd_hw_psram_init(void)
 	at91_sys_write( AT91_MATRIX_SCFG5, AT91_MATRIX_ARBT_FIXED_PRIORITY |
 				(AT91_MATRIX_FIXED_DEFMSTR & (5 << 18)) |
 				AT91_MATRIX_DEFMSTR_TYPE_FIXED |
-				(AT91_MATRIX_SLOT_CYCLE & (0x80 << 0)));
+				(AT91_MATRIX_SLOT_CYCLE & (0xFF << 0)));
 
 	return 0;
 }
diff --git a/board/st/nmdk8815/Makefile b/board/st/nhk8815/Makefile
index be9a424205..b37fe534ac 100644
--- a/board/st/nmdk8815/Makefile
+++ b/board/st/nhk8815/Makefile
@@ -29,7 +29,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	:= nmdk8815.o
+COBJS	:= nhk8815.o
 SOBJS	:= platform.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
diff --git a/board/st/nmdk8815/config.mk b/board/st/nhk8815/config.mk
index 590393bd64..590393bd64 100644
--- a/board/st/nmdk8815/config.mk
+++ b/board/st/nhk8815/config.mk
diff --git a/board/st/nmdk8815/nmdk8815.c b/board/st/nhk8815/nhk8815.c
index edf46262f5..085a5e0a42 100644
--- a/board/st/nmdk8815/nmdk8815.c
+++ b/board/st/nhk8815/nhk8815.c
@@ -53,6 +53,10 @@ int board_init(void)
 	writel(0x0000305b, REG_FSMC_BCR1);
 	writel(0x00033f33, REG_FSMC_BTR1);
 
+	/* Set up SMCS0 for OneNand: sram-like once again */
+	writel(0x000030db, NOMADIK_FSMC_BASE + 0x00); /* FSMC_BCR0 */
+	writel(0x02100551, NOMADIK_FSMC_BASE + 0x04); /* FSMC_BTR0 */
+
 	icache_enable();
 	return 0;
 }
diff --git a/board/st/nmdk8815/platform.S b/board/st/nhk8815/platform.S
index 2a67110231..2a67110231 100644
--- a/board/st/nmdk8815/platform.S
+++ b/board/st/nhk8815/platform.S
diff --git a/board/trizepsiv/conxs.c b/board/trizepsiv/conxs.c
index 5c0eb41d4b..8c1145629f 100644
--- a/board/trizepsiv/conxs.c
+++ b/board/trizepsiv/conxs.c
@@ -44,13 +44,18 @@ extern struct serial_device serial_ffuart_device;
 extern struct serial_device serial_btuart_device;
 extern struct serial_device serial_stuart_device;
 
+#if CONFIG_POLARIS
+#define BOOT_CONSOLE	"serial_stuart"
+#else
+#define BOOT_CONSOLE	"serial_ffuart"
+#endif
 /* ------------------------------------------------------------------------- */
 
 /*
  * Miscelaneous platform dependent initialisations
  */
 
-void usb_board_init(void)
+int usb_board_init(void)
 {
 	UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
 		~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE);
@@ -71,6 +76,8 @@ void usb_board_init(void)
 
 	/* Set port power control mask bits, only 3 ports. */
 	UHCRHDB |= (0x7<<17);
+
+	return 0;
 }
 
 void usb_board_init_fail(void)
@@ -89,7 +96,6 @@ void usb_board_stop(void)
 
 	CKEN &= ~CKEN10_USBHOST;
 
-	puts("Called USB STOP\n");
 	return;
 }
 
@@ -112,17 +118,14 @@ int board_late_init(void)
 #if defined(CONFIG_SERIAL_MULTI)
 	char *console=getenv("boot_console");
 
-	if ((strcmp(console,"serial_btuart") == 0) ||
-		(strcmp(console,"serial_stuart") == 0) ||
-		(strcmp(console,"serial_ffuart") == 0)) {
-			setenv("stdout",console);
-			setenv("stdin", console);
-			setenv("stderr",console);
-	} else {
-		setenv("stdout", "serial");
-		setenv("stdin", "serial");
-		setenv("stderr", "serial");
+	if ((console == NULL) || (strcmp(console,"serial_btuart") &&
+		strcmp(console,"serial_stuart") &&
+		strcmp(console,"serial_ffuart"))) {
+			console = BOOT_CONSOLE;
 	}
+	setenv("stdout",console);
+	setenv("stdin", console);
+	setenv("stderr",console);
 #endif
 	return 0;
 }