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authorFabio Estevam <fabio.estevam@freescale.com>2015-04-16 22:11:47 -0300
committerStefano Babic <sbabic@denx.de>2015-04-22 16:02:46 +0200
commit407be42d736804c674b68f4e3978606c7841553b (patch)
tree49445bbd8c964609af359b6b6d46de368e59538f /board
parent761bc19501d6daefa37dbdd75f76914a339ac0d3 (diff)
downloadblackbird-obmc-uboot-407be42d736804c674b68f4e3978606c7841553b.tar.gz
blackbird-obmc-uboot-407be42d736804c674b68f4e3978606c7841553b.zip
mx6sabresd: Fix SPL memory description
mx6sabresd has four MT41K128M16JT-125 chips. Each memory has 16-bit bus and 2GiB, so fix the width and density fields accordingly. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Diffstat (limited to 'board')
-rw-r--r--board/freescale/mx6sabresd/mx6sabresd.c9
1 files changed, 5 insertions, 4 deletions
diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c
index bb2dd9624b..a4f3a944f6 100644
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -753,10 +753,11 @@ const struct mx6_mmdc_calibration mx6_mmcd_calib = {
.p1_mpwrdlctl = 0x48254A36,
};
+/* MT41K128M16JT-125 */
static struct mx6_ddr3_cfg mem_ddr = {
.mem_speed = 1600,
- .density = 4,
- .width = 64,
+ .density = 2,
+ .width = 16,
.banks = 8,
.rowaddr = 14,
.coladdr = 10,
@@ -798,7 +799,7 @@ static void spl_dram_init(void)
{
struct mx6_ddr_sysinfo sysinfo = {
/* width of data bus:0=16,1=32,2=64 */
- .dsize = mem_ddr.width/32,
+ .dsize = 2,
/* config for full 4GB range so that get_mem_size() works */
.cs_density = 32, /* 32Gb per CS */
/* single chip select */
@@ -818,7 +819,7 @@ static void spl_dram_init(void)
.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
};
- mx6dq_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
+ mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
}
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