Merge branch 'master' of git://git.denx.de/u-boot-arm

34 files changed, 2516 insertions, 40 deletions

diff --git a/board/LaCie/common/common.c b/board/LaCie/common/common.c
index 78d0edc66d..a62bf9f189 100644
--- a/board/LaCie/common/common.c
+++ b/board/LaCie/common/common.c
@@ -13,10 +13,11 @@
 
 #if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
 
+#define MII_MARVELL_PHY_PAGE		22
+
 #define MV88E1116_LED_FCTRL_REG		10
 #define MV88E1116_CPRSP_CR3_REG		21
 #define MV88E1116_MAC_CTRL_REG		21
-#define MV88E1116_PGADR_REG		22
 #define MV88E1116_RGMII_TXTM_CTRL	(1 << 4)
 #define MV88E1116_RGMII_RXTM_CTRL	(1 << 5)
 
@@ -31,15 +32,44 @@ void mv_phy_88e1116_init(const char *name, u16 phyaddr)
 	 * Enable RGMII delay on Tx and Rx for CPU port
 	 * Ref: sec 4.7.2 of chip datasheet
 	 */
-	miiphy_write(name, phyaddr, MV88E1116_PGADR_REG, 2);
+	miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 2);
 	miiphy_read(name, phyaddr, MV88E1116_MAC_CTRL_REG, &reg);
 	reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
 	miiphy_write(name, phyaddr, MV88E1116_MAC_CTRL_REG, reg);
-	miiphy_write(name, phyaddr, MV88E1116_PGADR_REG, 0);
+	miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 0);
 
 	if (miiphy_reset(name, phyaddr) == 0)
 		printf("88E1116 Initialized on %s\n", name);
 }
+
+void mv_phy_88e1318_init(const char *name, u16 phyaddr)
+{
+	u16 reg;
+
+	if (miiphy_set_current_dev(name))
+		return;
+
+	/*
+	 * Set control mode 4 for LED[0].
+	 */
+	miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 3);
+	miiphy_read(name, phyaddr, 16, &reg);
+	reg |= 0xf;
+	miiphy_write(name, phyaddr, 16, reg);
+
+	/*
+	 * Enable RGMII delay on Tx and Rx for CPU port
+	 * Ref: sec 4.7.2 of chip datasheet
+	 */
+	miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 2);
+	miiphy_read(name, phyaddr, MV88E1116_MAC_CTRL_REG, &reg);
+	reg |= (MV88E1116_RGMII_TXTM_CTRL | MV88E1116_RGMII_RXTM_CTRL);
+	miiphy_write(name, phyaddr, MV88E1116_MAC_CTRL_REG, reg);
+	miiphy_write(name, phyaddr, MII_MARVELL_PHY_PAGE, 0);
+
+	if (miiphy_reset(name, phyaddr) == 0)
+		printf("88E1318 Initialized on %s\n", name);
+}
 #endif /* CONFIG_CMD_NET && CONFIG_RESET_PHY_R */
 
 #if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR)
diff --git a/board/LaCie/common/common.h b/board/LaCie/common/common.h
index 2edd5abbcd..85e433c931 100644
--- a/board/LaCie/common/common.h
+++ b/board/LaCie/common/common.h
@@ -12,6 +12,7 @@
 
 #if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
 void mv_phy_88e1116_init(const char *name, u16 phyaddr);
+void mv_phy_88e1318_init(const char *name, u16 phyaddr);
 #endif
 #if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR)
 int lacie_read_mac_address(uchar *mac);
diff --git a/board/LaCie/netspace_v2/kwbimage-ns2l.cfg b/board/LaCie/netspace_v2/kwbimage-ns2l.cfg
new file mode 100644
index 0000000000..d008eb0ab0
--- /dev/null
+++ b/board/LaCie/netspace_v2/kwbimage-ns2l.cfg
@@ -0,0 +1,162 @@
+#
+# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
+#
+# Based on Kirkwood support:
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM	spi	# Boot from SPI flash
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1B1B1B9B
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xFFD01400 0x43000618	# DDR Configuration register
+# bit13-0:  0xa00 (2560 DDR2 clks refresh rate)
+# bit23-14: zero
+# bit24: 1= enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: zero
+# bit31-30: 01
+
+DATA 0xFFD01404 0x34143000	# DDR Controller Control Low
+# bit 4:    0=addr/cmd in smame cycle
+# bit 5:    0=clk is driven during self refresh, we don't care for APX
+# bit 6:    0=use recommended falling edge of clk for addr/cmd
+# bit14:    0=input buffer always powered up
+# bit18:    1=cpu lock transaction enabled
+# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31:    0=no additional STARTBURST delay
+
+DATA 0xFFD01408 0x11012228	# DDR Timing (Low) (active cycles value +1)
+# bit7-4:   TRCD
+# bit11- 8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20:    TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xFFD0140C 0x00000A19	#  DDR Timing (High)
+# bit6-0:   TRFC
+# bit8-7:   TR2R
+# bit10-9:  TR2W
+# bit12-11: TW2W
+# bit31-13: zero required
+
+DATA 0xFFD01410 0x0000DDDD	#  DDR Address Control
+# bit1-0:   00, Cs0width=x8
+# bit3-2:   10, Cs0size=512Mb
+# bit5-4:   00, Cs2width=nonexistent
+# bit7-6:   00, Cs1size =nonexistent
+# bit9-8:   00, Cs2width=nonexistent
+# bit11-10: 00, Cs2size =nonexistent
+# bit13-12: 00, Cs3width=nonexistent
+# bit15-14: 00, Cs3size =nonexistent
+# bit16:    0,  Cs0AddrSel
+# bit17:    0,  Cs1AddrSel
+# bit18:    0,  Cs2AddrSel
+# bit19:    0,  Cs3AddrSel
+# bit31-20: 0 required
+
+DATA 0xFFD01414 0x00000000	#  DDR Open Pages Control
+# bit0:    0,  OpenPage enabled
+# bit31-1: 0 required
+
+DATA 0xFFD01418 0x00000000	#  DDR Operation
+# bit3-0:   0x0, DDR cmd
+# bit31-4:  0 required
+
+DATA 0xFFD0141C 0x00000632	#  DDR Mode
+# bit2-0:   2, BurstLen=2 required
+# bit3:     0, BurstType=0 required
+# bit6-4:   4, CL=5
+# bit7:     0, TestMode=0 normal
+# bit8:     0, DLL reset=0 normal
+# bit11-9:  6, auto-precharge write recovery ????????????
+# bit12:    0, PD must be zero
+# bit31-13: 0 required
+
+DATA 0xFFD01420 0x00000004	#  DDR Extended Mode
+# bit0:    0,  DDR DLL enabled
+# bit1:    1,  DDR drive strenght reduced
+# bit2:    1,  DDR ODT control lsd enabled
+# bit5-3:  000, required
+# bit6:    1,  DDR ODT control msb, enabled
+# bit9-7:  000, required
+# bit10:   0,  differential DQS enabled
+# bit11:   0, required
+# bit12:   0, DDR output buffer enabled
+# bit31-13: 0 required
+
+DATA 0xFFD01424 0x0000F07F	#  DDR Controller Control High
+# bit2-0:  111, required
+# bit3  :  1  , MBUS Burst Chop disabled
+# bit6-4:  111, required
+# bit7  :  1  , D2P Latency enabled
+# bit8  :  1  , add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9  :  0  , no half clock cycle addition to dataout
+# bit10 :  0  , 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11 :  0  , 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 1111 required
+# bit31-16: 0    required
+
+DATA 0xFFD01428 0x00085520	# DDR2 ODT Read Timing (default values)
+DATA 0xFFD0147C 0x00008552	# DDR2 ODT Write Timing (default values)
+
+DATA 0xFFD01500 0x00000000	# CS[0]n Base address to 0x0
+DATA 0xFFD01504 0x07FFFFF1	# CS[0]n Size
+# bit0:    1,  Window enabled
+# bit1:    0,  Write Protect disabled
+# bit3-2:  00, CS0 hit selected
+# bit23-4: ones, required
+# bit31-24: 0x07, Size (i.e. 128MB)
+
+DATA 0xFFD0150C 0x00000000	# CS[1]n Size, window disabled
+DATA 0xFFD01514 0x00000000	# CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000	# CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00010000	#  DDR ODT Control (Low)
+# bit3-0:  1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
+# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
+
+DATA 0xFFD01498 0x00000000	#  DDR ODT Control (High)
+# bit1-0:  00, ODT0 controlled by ODT Control (low) register above
+# bit3-2:  01, ODT1 active NEVER!
+# bit31-4: zero, required
+
+DATA 0xFFD0149C 0x0000E40F	# CPU ODT Control
+# bit3-0:  1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
+# bit7-4:  1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
+# bit11-10:1, DQ_ODTSel. ODT select turned on
+
+DATA 0xFFD01480 0x00000001	# DDR Initialization Control
+#bit0=1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/board/LaCie/netspace_v2/netspace_v2.c b/board/LaCie/netspace_v2/netspace_v2.c
index 68e8a770c7..101a80a70a 100644
--- a/board/LaCie/netspace_v2/netspace_v2.c
+++ b/board/LaCie/netspace_v2/netspace_v2.c
@@ -107,7 +107,11 @@ int misc_init_r(void)
 /* Configure and initialize PHY */
 void reset_phy(void)
 {
+#if defined(CONFIG_NETSPACE_LITE_V2) || defined(CONFIG_NETSPACE_MINI_V2)
+	mv_phy_88e1318_init("egiga0", 0);
+#else
 	mv_phy_88e1116_init("egiga0", 8);
+#endif
 }
 #endif
 
diff --git a/board/altera/socfpga_cyclone5/Makefile b/board/altera/socfpga_cyclone5/Makefile
new file mode 100644
index 0000000000..43bbc3785f
--- /dev/null
+++ b/board/altera/socfpga_cyclone5/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= socfpga_cyclone5.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/altera/socfpga_cyclone5/socfpga_cyclone5.c b/board/altera/socfpga_cyclone5/socfpga_cyclone5.c
new file mode 100644
index 0000000000..7725be12f4
--- /dev/null
+++ b/board/altera/socfpga_cyclone5/socfpga_cyclone5.c
@@ -0,0 +1,80 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/io.h>
+
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Print CPU information
+ */
+int print_cpuinfo(void)
+{
+	puts("CPU   : Altera SOCFPGA Platform\n");
+	return 0;
+}
+
+/*
+ * Print Board information
+ */
+int checkboard(void)
+{
+	puts("BOARD : Altera SOCFPGA Cyclone5 Board\n");
+	return 0;
+}
+
+/*
+ * Initialization function which happen at early stage of c code
+ */
+int board_early_init_f(void)
+{
+	return 0;
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+int board_init(void)
+{
+	icache_enable();
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	return 0;
+}
+
+#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
+int overwrite_console(void)
+{
+	return 0;
+}
+#endif
+
+/*
+ * DesignWare Ethernet initialization
+ */
+/* We know all the init functions have been run now */
+int board_eth_init(bd_t *bis)
+{
+	return 0;
+}
diff --git a/board/atmark-techno/armadillo-800eva/Makefile b/board/atmark-techno/armadillo-800eva/Makefile
new file mode 100644
index 0000000000..9f9618b518
--- /dev/null
+++ b/board/atmark-techno/armadillo-800eva/Makefile
@@ -0,0 +1,46 @@
+#
+# Copyright (C) 2012  Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	+= armadillo-800eva.o
+COBJS   := $(COBJS-y)
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
+
diff --git a/board/atmark-techno/armadillo-800eva/armadillo-800eva.c b/board/atmark-techno/armadillo-800eva/armadillo-800eva.c
new file mode 100644
index 0000000000..0e9c22296a
--- /dev/null
+++ b/board/atmark-techno/armadillo-800eva/armadillo-800eva.c
@@ -0,0 +1,328 @@
+/*
+ * Copyright (C) 2012  Renesas Solutions Corp.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/arch/rmobile.h>
+
+#define s_init_wait(cnt) \
+		({	\
+			volatile u32 i = 0x10000 * cnt;	\
+			while (i > 0)	\
+				i--;	\
+		})
+
+#define USBCR1 0xE605810A
+
+void s_init(void)
+{
+	struct r8a7740_rwdt *rwdt0 = (struct r8a7740_rwdt *)RWDT0_BASE;
+	struct r8a7740_rwdt *rwdt1 = (struct r8a7740_rwdt *)RWDT1_BASE;
+	struct r8a7740_cpg *cpg = (struct r8a7740_cpg *)CPG_BASE;
+	struct r8a7740_bsc *bsc = (struct r8a7740_bsc *)BSC_BASE;
+	struct r8a7740_ddrp *ddrp = (struct r8a7740_ddrp *)DDRP_BASE;
+	struct r8a7740_dbsc *dbsc = (struct r8a7740_dbsc *)DBSC_BASE;
+
+	/* Watchdog init */
+	writew(0xA500, &rwdt0->rwtcsra0);
+	writew(0xA500, &rwdt1->rwtcsra0);
+
+	/* CPG */
+	writel(0xFF800080, &cpg->rmstpcr4);
+	writel(0xFF800080, &cpg->smstpcr4);
+
+	/* USB clock */
+	writel(0x00000080, &cpg->usbckcr);
+	s_init_wait(1);
+
+	/* USBCR1 */
+	writew(0x0710, USBCR1);
+
+	/* FRQCR */
+	writel(0x00000000, &cpg->frqcrb);
+	writel(0x62030533, &cpg->frqcra);
+	writel(0x208A354E, &cpg->frqcrc);
+	writel(0x80331050, &cpg->frqcrb);
+	s_init_wait(1);
+
+	writel(0x00000000, &cpg->frqcrd);
+	s_init_wait(1);
+
+	/* SUBClk */
+	writel(0x0000010B, &cpg->subckcr);
+
+	/* PLL */
+	writel(0x00004004, &cpg->pllc01cr);
+	s_init_wait(1);
+
+	writel(0xa0000000, &cpg->pllc2cr);
+	s_init_wait(2);
+
+	/* BSC */
+	writel(0x0000001B, &bsc->cmncr);
+
+	writel(0x20000000, &dbsc->dbcmd);
+	writel(0x10009C40, &dbsc->dbcmd);
+	s_init_wait(1);
+
+	writel(0x00000007, &dbsc->dbkind);
+	writel(0x0E030A02, &dbsc->dbconf0);
+	writel(0x00000001, &dbsc->dbphytype);
+	writel(0x00000000, &dbsc->dbbl);
+	writel(0x00000006, &dbsc->dbtr0);
+	writel(0x00000005, &dbsc->dbtr1);
+	writel(0x00000000, &dbsc->dbtr2);
+	writel(0x00000006, &dbsc->dbtr3);
+	writel(0x00080006, &dbsc->dbtr4);
+	writel(0x00000015, &dbsc->dbtr5);
+	writel(0x0000000f, &dbsc->dbtr6);
+	writel(0x00000004, &dbsc->dbtr7);
+	writel(0x00000018, &dbsc->dbtr8);
+	writel(0x00000006, &dbsc->dbtr9);
+	writel(0x00000006, &dbsc->dbtr10);
+	writel(0x0000000F, &dbsc->dbtr11);
+	writel(0x0000000D, &dbsc->dbtr12);
+	writel(0x000000A0, &dbsc->dbtr13);
+	writel(0x000A0003, &dbsc->dbtr14);
+	writel(0x00000003, &dbsc->dbtr15);
+	writel(0x40005005, &dbsc->dbtr16);
+	writel(0x0C0C0000, &dbsc->dbtr17);
+	writel(0x00000200, &dbsc->dbtr18);
+	writel(0x00000040, &dbsc->dbtr19);
+	writel(0x00000001, &dbsc->dbrnk0);
+	writel(0x00000110, &dbsc->dbdficnt);
+	writel(0x00000101, &ddrp->funcctrl);
+	writel(0x00000001, &ddrp->dllctrl);
+	writel(0x00000186, &ddrp->zqcalctrl);
+	writel(0xB3440051, &ddrp->zqodtctrl);
+	writel(0x94449443, &ddrp->rdctrl);
+	writel(0x000000C0, &ddrp->rdtmg);
+	writel(0x00000101, &ddrp->fifoinit);
+	writel(0x02060506, &ddrp->outctrl);
+	writel(0x00004646, &ddrp->dqcalofs1);
+	writel(0x00004646, &ddrp->dqcalofs2);
+	writel(0x800000aa, &ddrp->dqcalexp);
+	writel(0x00000000, &ddrp->dllctrl);
+	writel(0x00000000, DDRPNCNT);
+
+	writel(0x0000000C, &dbsc->dbcmd);
+	readl(&dbsc->dbwait);
+	s_init_wait(1);
+
+	writel(0x00000002, DDRPNCNT);
+
+	writel(0x0000000C, &dbsc->dbcmd);
+	readl(&dbsc->dbwait);
+	s_init_wait(1);
+
+	writel(0x00000187, &ddrp->zqcalctrl);
+
+	writel(0x00009C40, &dbsc->dbcmd);
+	readl(&dbsc->dbwait);
+	s_init_wait(1);
+
+	writel(0x00009C40, &dbsc->dbcmd);
+	readl(&dbsc->dbwait);
+	s_init_wait(1);
+
+	writel(0x00000010, &dbsc->dbdficnt);
+	writel(0x02060507, &ddrp->outctrl);
+
+	writel(0x00009C40, &dbsc->dbcmd);
+	readl(&dbsc->dbwait);
+	s_init_wait(1);
+
+	writel(0x21009C40, &dbsc->dbcmd);
+	readl(&dbsc->dbwait);
+	s_init_wait(1);
+
+	writel(0x00009C40, &dbsc->dbcmd);
+	readl(&dbsc->dbwait);
+	s_init_wait(1);
+
+	writel(0x00009C40, &dbsc->dbcmd);
+	readl(&dbsc->dbwait);
+	s_init_wait(1);
+
+	writel(0x00009C40, &dbsc->dbcmd);
+	readl(&dbsc->dbwait);
+	s_init_wait(1);
+
+	writel(0x00009C40, &dbsc->dbcmd);
+	readl(&dbsc->dbwait);
+	s_init_wait(1);
+
+	writel(0x11000044, &dbsc->dbcmd);
+	readl(&dbsc->dbwait);
+	s_init_wait(1);
+
+	writel(0x2A000000, &dbsc->dbcmd);
+	readl(&dbsc->dbwait);
+	s_init_wait(1);
+
+	writel(0x2B000000, &dbsc->dbcmd);
+	readl(&dbsc->dbwait);
+
+	writel(0x29000004, &dbsc->dbcmd);
+	readl(&dbsc->dbwait);
+
+	writel(0x28001520, &dbsc->dbcmd);
+	readl(&dbsc->dbwait);
+	s_init_wait(1);
+
+	writel(0x03000200, &dbsc->dbcmd);
+	readl(&dbsc->dbwait);
+	s_init_wait(1);
+
+	writel(0x000001FF, &dbsc->dbrfcnf0);
+	writel(0x00010C30, &dbsc->dbrfcnf1);
+	writel(0x00000000, &dbsc->dbrfcnf2);
+
+	writel(0x00000001, &dbsc->dbrfen);
+	writel(0x00000001, &dbsc->dbacen);
+
+	/* BSC */
+	writel(0x00410400, &bsc->cs0bcr);
+	writel(0x00410400, &bsc->cs2bcr);
+	writel(0x00410400, &bsc->cs5bbcr);
+	writel(0x02CB0400, &bsc->cs6abcr);
+
+	writel(0x00000440, &bsc->cs0wcr);
+	writel(0x00000440, &bsc->cs2wcr);
+	writel(0x00000240, &bsc->cs5bwcr);
+	writel(0x00000240, &bsc->cs6awcr);
+
+	writel(0x00000005, &bsc->rbwtcnt);
+	writel(0x00000002, &bsc->cs0wcr2);
+	writel(0x00000002, &bsc->cs2wcr2);
+	writel(0x00000002, &bsc->cs4wcr2);
+}
+
+#define GPIO_ICCR (0xE60581A0)
+#define ICCR_15BIT (1 << 15) /* any time 1 */
+#define IIC0_CONTA (1 << 7)
+#define IIC0_CONTB (1 << 6)
+#define IIC1_CONTA (1 << 5)
+#define IIC1_CONTB (1 << 4)
+#define IIC0_PS33E (1 << 1)
+#define IIC1_PS33E (1 << 0)
+#define GPIO_ICCR_DATA	\
+		(ICCR_15BIT |	\
+		IIC0_CONTA | IIC0_CONTB | IIC1_CONTA |	\
+		IIC1_CONTB | IIC0_PS33E | IIC1_PS33E)
+
+#define MSTPCR1         0xE6150134
+#define TMU0_MSTP125    (1 << 25)
+#define I2C0_MSTP116    (1 << 16)
+
+#define MSTPCR3         0xE615013C
+#define I2C1_MSTP323    (1 << 23)
+#define GETHER_MSTP309	(1 << 9)
+
+#define GPIO_SCIFA1_TXD (0xE60520C4)
+#define GPIO_SCIFA1_RXD (0xE60520C3)
+
+int board_early_init_f(void)
+{
+	/* TMU */
+	clrbits_le32(MSTPCR1, TMU0_MSTP125);
+
+	/* GETHER */
+	clrbits_le32(MSTPCR3, GETHER_MSTP309);
+
+	/* I2C 0/1 */
+	clrbits_le32(MSTPCR1, I2C0_MSTP116);
+	clrbits_le32(MSTPCR3, I2C1_MSTP323);
+
+	/* SCIFA1 */
+	writeb(1, GPIO_SCIFA1_TXD); /* SCIFA1_TXD */
+	writeb(1, GPIO_SCIFA1_RXD); /* SCIFA1_RXD */
+
+	/* IICCR */
+	writew(GPIO_ICCR_DATA, GPIO_ICCR);
+
+	return 0;
+}
+
+DECLARE_GLOBAL_DATA_PTR;
+int board_init(void)
+{
+	/* board id for linux */
+	gd->bd->bi_arch_number = MACH_TYPE_ARMADILLO_800EVA;
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = ARMADILLO_800EVA_SDRAM_BASE + 0x100;
+
+	/* Init PFC controller */
+	r8a7740_pinmux_init();
+
+	/* GETHER Enable */
+	gpio_request(GPIO_FN_ET_CRS, NULL);
+	gpio_request(GPIO_FN_ET_MDC, NULL);
+	gpio_request(GPIO_FN_ET_MDIO, NULL);
+	gpio_request(GPIO_FN_ET_TX_ER, NULL);
+	gpio_request(GPIO_FN_ET_RX_ER, NULL);
+	gpio_request(GPIO_FN_ET_ERXD0, NULL);
+	gpio_request(GPIO_FN_ET_ERXD1, NULL);
+	gpio_request(GPIO_FN_ET_ERXD2, NULL);
+	gpio_request(GPIO_FN_ET_ERXD3, NULL);
+	gpio_request(GPIO_FN_ET_TX_CLK, NULL);
+	gpio_request(GPIO_FN_ET_TX_EN, NULL);
+	gpio_request(GPIO_FN_ET_ETXD0, NULL);
+	gpio_request(GPIO_FN_ET_ETXD1, NULL);
+	gpio_request(GPIO_FN_ET_ETXD2, NULL);
+	gpio_request(GPIO_FN_ET_ETXD3, NULL);
+	gpio_request(GPIO_FN_ET_PHY_INT, NULL);
+	gpio_request(GPIO_FN_ET_COL, NULL);
+	gpio_request(GPIO_FN_ET_RX_DV, NULL);
+	gpio_request(GPIO_FN_ET_RX_CLK, NULL);
+
+	gpio_request(GPIO_PORT18, NULL); /* PHY_RST */
+	gpio_direction_output(GPIO_PORT18, 1);
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+const struct rmobile_sysinfo sysinfo = {
+	CONFIG_RMOBILE_BOARD_STRING
+};
+
+int board_late_init(void)
+{
+	return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+}
diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/board/atmel/at91sam9x5ek/at91sam9x5ek.c
index ae408bc9db..06028aa01e 100644
--- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c
+++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c
@@ -62,6 +62,10 @@ static void at91sam9x5ek_nand_hw_init(void)
 	csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
 	/* NAND flash on D16 */
 	csa |= AT91_MATRIX_NFD0_ON_D16;
+
+	/* Configure IO drive */
+	csa &= ~AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
+
 	writel(csa, &matrix->ebicsa);
 
 	/* Configure SMC CS3 for NAND/SmartMedia */
diff --git a/board/buffalo/lsxl/lsxl.c b/board/buffalo/lsxl/lsxl.c
index b3f31d6b69..57776fb077 100644
--- a/board/buffalo/lsxl/lsxl.c
+++ b/board/buffalo/lsxl/lsxl.c
@@ -195,9 +195,11 @@ int board_init(void)
 static void check_power_switch(void)
 {
 	if (kw_gpio_get_value(GPIO_POWER_SWITCH)) {
-		/* turn off HDD and USB power */
+		/* turn off fan, HDD and USB power */
 		kw_gpio_set_value(GPIO_HDD_POWER, 0);
 		kw_gpio_set_value(GPIO_USB_VBUS, 0);
+		kw_gpio_set_value(GPIO_FAN_HIGH, 1);
+		kw_gpio_set_value(GPIO_FAN_LOW, 1);
 		set_led(LED_OFF);
 
 		/* loop until released */
@@ -207,6 +209,8 @@ static void check_power_switch(void)
 		/* turn power on again */
 		kw_gpio_set_value(GPIO_HDD_POWER, 1);
 		kw_gpio_set_value(GPIO_USB_VBUS, 1);
+		kw_gpio_set_value(GPIO_FAN_HIGH, 0);
+		kw_gpio_set_value(GPIO_FAN_LOW, 0);
 		set_led(LED_POWER_BLINKING);
 	}
 }
diff --git a/board/davinci/ea20/ea20.c b/board/davinci/ea20/ea20.c
index 7e000404ee..0edd910210 100644
--- a/board/davinci/ea20/ea20.c
+++ b/board/davinci/ea20/ea20.c
@@ -176,6 +176,9 @@ int board_early_init_f(void)
 	if (davinci_configure_pin_mux(gpio_pins, ARRAY_SIZE(gpio_pins)) != 0)
 		return 1;
 
+	/* Set DISP_ON high to enable LCD output*/
+	gpio_direction_output(97, 1);
+
 	/* Set the RESETOUTn low */
 	gpio_direction_output(111, 0);
 
@@ -188,9 +191,6 @@ int board_early_init_f(void)
 	/* Set LCD_B_PWR low to power down LCD Backlight*/
 	gpio_direction_output(102, 0);
 
-	/* Set DISP_ON low to disable LCD output*/
-	gpio_direction_output(97, 0);
-
 #ifndef CONFIG_USE_IRQ
 	irq_init();
 #endif
@@ -250,15 +250,19 @@ int board_early_init_f(void)
 	writel(readl(&davinci_syscfg_regs->mstpri[2]) & 0x0fffffff,
 	       &davinci_syscfg_regs->mstpri[2]);
 
-	/* Set LCD_B_PWR low to power up LCD Backlight*/
-	gpio_set_value(102, 1);
-
-	/* Set DISP_ON low to disable LCD output*/
-	gpio_set_value(97, 1);
 
 	return 0;
 }
 
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+	return 1;
+}
+
 int board_init(void)
 {
 	/* arch number of the board */
@@ -276,6 +280,9 @@ int board_init(void)
 
 int board_late_init(void)
 {
+	unsigned char buf[2];
+	int ret;
+
 	/* PinMux for HALTEN */
 	if (davinci_configure_pin_mux(halten_pin, ARRAY_SIZE(halten_pin)) != 0)
 		return 1;
@@ -283,8 +290,15 @@ int board_late_init(void)
 	/* Set HALTEN to high */
 	gpio_direction_output(134, 1);
 
-	setenv("stdout", "serial");
+	/* Set fixed contrast settings for LCD via I2C potentiometer */
+	buf[0] = 0x00;
+	buf[1] = 0xd7;
+	ret = i2c_write(0x2e, 6, 1, buf, 2);
+	if (ret)
+		puts("\nContrast Settings FAILED\n");
 
+	/* Set LCD_B_PWR high to power up LCD Backlight*/
+	gpio_set_value(102, 1);
 	return 0;
 }
 #endif /* CONFIG_BOARD_LATE_INIT */
diff --git a/board/freescale/mx28evk/mx28evk.c b/board/freescale/mx28evk/mx28evk.c
index d782aea61b..6e719ffc39 100644
--- a/board/freescale/mx28evk/mx28evk.c
+++ b/board/freescale/mx28evk/mx28evk.c
@@ -100,19 +100,6 @@ int board_mmc_init(bd_t *bis)
 
 #ifdef	CONFIG_CMD_NET
 
-#define	MII_OPMODE_STRAP_OVERRIDE	0x16
-#define	MII_PHY_CTRL1			0x1e
-#define	MII_PHY_CTRL2			0x1f
-
-int fecmxc_mii_postcall(int phy)
-{
-	miiphy_write("FEC1", phy, MII_BMCR, 0x9000);
-	miiphy_write("FEC1", phy, MII_OPMODE_STRAP_OVERRIDE, 0x0202);
-	if (phy == 3)
-		miiphy_write("FEC1", 3, MII_PHY_CTRL2, 0x8180);
-	return 0;
-}
-
 int board_eth_init(bd_t *bis)
 {
 	struct mxs_clkctrl_regs *clkctrl_regs =
@@ -152,24 +139,12 @@ int board_eth_init(bd_t *bis)
 		return -EINVAL;
 	}
 
-	ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
-	if (ret) {
-		puts("FEC MXS: Unable to register FEC0 mii postcall\n");
-		return ret;
-	}
-
 	dev = eth_get_dev_by_name("FEC1");
 	if (!dev) {
 		puts("FEC MXS: Unable to get FEC1 device entry\n");
 		return -EINVAL;
 	}
 
-	ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
-	if (ret) {
-		puts("FEC MXS: Unable to register FEC1 mii postcall\n");
-		return ret;
-	}
-
 	return ret;
 }
 
diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c
index 7a0682a7e9..a94701cbf1 100644
--- a/board/freescale/mx51evk/mx51evk.c
+++ b/board/freescale/mx51evk/mx51evk.c
@@ -60,6 +60,14 @@ int dram_init(void)
 	return 0;
 }
 
+u32 get_board_rev(void)
+{
+	u32 rev = get_cpu_rev();
+	if (!gpio_get_value(IMX_GPIO_NR(1, 22)))
+		rev |= BOARD_REV_2_0 << BOARD_VER_OFFSET;
+	return rev;
+}
+
 static void setup_iomux_uart(void)
 {
 	unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
diff --git a/board/friendlyarm/mini2440/Makefile b/board/friendlyarm/mini2440/Makefile
new file mode 100644
index 0000000000..b88e569074
--- /dev/null
+++ b/board/friendlyarm/mini2440/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2012
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= mini2440.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/friendlyarm/mini2440/mini2440.c b/board/friendlyarm/mini2440/mini2440.c
new file mode 100644
index 0000000000..e97d981cab
--- /dev/null
+++ b/board/friendlyarm/mini2440/mini2440.c
@@ -0,0 +1,134 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ *
+ * (C) Copyright 2009
+ * Michel Pollet <buserror@gmail.com>
+ *
+ * (C) Copyright 2012
+ * Gabriel Huau <contact@huau-gabriel.fr>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/s3c2440.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/gpio.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <netdev.h>
+#include "mini2440.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static inline void pll_delay(unsigned long loops)
+{
+	__asm__ volatile ("1:\n"
+	  "subs %0, %1, #1\n"
+	  "bne 1b" : "=r" (loops) : "0" (loops));
+}
+
+int board_early_init_f(void)
+{
+	struct s3c24x0_clock_power * const clk_power =
+					s3c24x0_get_base_clock_power();
+
+	/* to reduce PLL lock time, adjust the LOCKTIME register */
+	clk_power->locktime = 0xFFFFFF; /* Max PLL Lock time count */
+	clk_power->clkdivn = CLKDIVN_VAL;
+
+	/* configure UPLL */
+	clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
+	/* some delay between MPLL and UPLL */
+	pll_delay(100);
+
+	/* configure MPLL */
+	clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
+
+	/* some delay between MPLL and UPLL */
+	pll_delay(10000);
+
+	return 0;
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+int board_init(void)
+{
+	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
+
+	/* IOMUX Port H : UART Configuration */
+	gpio->gphcon = IOMUXH_nCTS0 | IOMUXH_nRTS0 | IOMUXH_TXD0 | IOMUXH_RXD0 |
+		IOMUXH_TXD1 | IOMUXH_RXD1 | IOMUXH_TXD2 | IOMUXH_RXD2;
+
+	gpio_direction_output(GPH8, 0);
+	gpio_direction_output(GPH9, 0);
+	gpio_direction_output(GPH10, 0);
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_BOOT_PARAM_ADDR;
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	struct s3c24x0_memctl *memctl = s3c24x0_get_base_memctl();
+
+	/*
+	 * Configuring bus width and timing
+	 * Initialize clocks for each bank 0..5
+	 * Bank 3 and 4 are used for DM9000
+	 */
+	writel(BANK_CONF, &memctl->bwscon);
+	writel(B0_CONF, &memctl->bankcon[0]);
+	writel(B1_CONF, &memctl->bankcon[1]);
+	writel(B2_CONF, &memctl->bankcon[2]);
+	writel(B3_CONF, &memctl->bankcon[3]);
+	writel(B4_CONF, &memctl->bankcon[4]);
+	writel(B5_CONF, &memctl->bankcon[5]);
+
+	/* Bank 6 and 7 are used for DRAM */
+	writel(SDRAM_64MB, &memctl->bankcon[6]);
+	writel(SDRAM_64MB, &memctl->bankcon[7]);
+
+	writel(MEM_TIMING, &memctl->refresh);
+	writel(BANKSIZE_CONF, &memctl->banksize);
+	writel(B6_MRSR, &memctl->mrsrb6);
+	writel(B7_MRSR, &memctl->mrsrb7);
+
+	gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
+			PHYS_SDRAM_SIZE);
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_DRIVER_DM9000
+	return dm9000_initialize(bis);
+#else
+	return 0;
+#endif
+}
diff --git a/board/friendlyarm/mini2440/mini2440.h b/board/friendlyarm/mini2440/mini2440.h
new file mode 100644
index 0000000000..db386eac01
--- /dev/null
+++ b/board/friendlyarm/mini2440/mini2440.h
@@ -0,0 +1,144 @@
+#ifndef __MINI2440_BOARD_CONF_H__
+#define __MINI2440_BOARD_CONF_H__
+
+/* PLL Parameters */
+#define CLKDIVN_VAL	7
+#define M_MDIV		0x7f
+#define M_PDIV		0x2
+#define M_SDIV		0x1
+
+#define U_M_MDIV	0x38
+#define U_M_PDIV	0x2
+#define U_M_SDIV	0x2
+
+/* BWSCON */
+#define DW8				0x0
+#define DW16			0x1
+#define DW32			0x2
+#define WAIT			(0x1<<2)
+#define UBLB			(0x1<<3)
+
+#define B1_BWSCON		(DW32)
+#define B2_BWSCON		(DW16)
+#define B3_BWSCON		(DW16 + WAIT + UBLB)
+#define B4_BWSCON		(DW16 + WAIT + UBLB)
+#define B5_BWSCON		(DW16)
+#define B6_BWSCON		(DW32)
+#define B7_BWSCON		(DW32)
+
+/*
+ * Bank Configuration
+ */
+#define B0_Tacs			0x0	/*  0clk */
+#define B0_Tcos			0x0	/*  0clk */
+#define B0_Tacc			0x7	/* 14clk */
+#define B0_Tcoh			0x0	/*  0clk */
+#define B0_Tah			0x0	/*  0clk */
+#define B0_Tacp			0x0 /*  0clk */
+#define B0_PMC			0x0	/* normal */
+
+#define B1_Tacs			0x0
+#define B1_Tcos			0x0
+#define B1_Tacc			0x7
+#define B1_Tcoh			0x0
+#define B1_Tah			0x0
+#define B1_Tacp			0x0
+#define B1_PMC			0x0
+
+#define B2_Tacs			0x0
+#define B2_Tcos			0x0
+#define B2_Tacc			0x7
+#define B2_Tcoh			0x0
+#define B2_Tah			0x0
+#define B2_Tacp			0x0
+#define B2_PMC			0x0
+
+#define B3_Tacs			0x0
+#define B3_Tcos			0x3	/*  4clk */
+#define B3_Tacc			0x7
+#define B3_Tcoh			0x1	/*  1clk */
+#define B3_Tah			0x3	/*  4clk */
+#define B3_Tacp			0x0
+#define B3_PMC			0x0
+
+#define B4_Tacs			0x0
+#define B4_Tcos			0x3
+#define B4_Tacc			0x7
+#define B4_Tcoh			0x1
+#define B4_Tah			0x3
+#define B4_Tacp			0x0
+#define B4_PMC			0x0
+
+#define B5_Tacs			0x0
+#define B5_Tcos			0x0
+#define B5_Tacc			0x7
+#define B5_Tcoh			0x0
+#define B5_Tah			0x0
+#define B5_Tacp			0x0
+#define B5_PMC			0x0
+
+/*
+ * SDRAM Configuration
+ */
+#define SDRAM_MT		0x3	/* SDRAM */
+#define SDRAM_Trcd		0x0	/* 2clk */
+#define SDRAM_SCAN_9	0x1	/* 9bit */
+#define SDRAM_SCAN_10	0x2	/* 10bit */
+
+#define SDRAM_64MB	((SDRAM_MT<<15) + (SDRAM_Trcd<<2) + (SDRAM_SCAN_9))
+
+/*
+ * Refresh Parameter
+ */
+#define REFEN		0x1	/* Refresh enable */
+#define TREFMD		0x0	/* CBR(CAS before RAS)/Auto refresh */
+#define Trp			0x1	/* 3clk */
+#define Trc			0x3	/* 7clk */
+#define Tchr		0x0	/* unused */
+#define REFCNT	1012 /* period=10.37us, HCLK=100Mhz, (2048 + 1-10.37*100) */
+
+/*
+ * MRSR Parameter
+ */
+#define BL	0x0
+#define BT	0x0
+#define CL	0x3 /* 3 clocks */
+#define TM	0x0
+#define WBL	0x0
+
+/*
+ * BankSize Parameter
+ */
+#define BK76MAP	0x2 /* 128MB/128MB */
+#define SCLK_EN	0x1 /* SCLK active */
+#define SCKE_EN	0x1 /* SDRAM power down mode enable */
+#define BURST_EN	0x1 /* Burst enable */
+
+/*
+ * Register values
+ */
+#define BANK_CONF ((0 + (B1_BWSCON<<4) + (B2_BWSCON<<8) + (B3_BWSCON<<12) + \
+			(B4_BWSCON<<16) + (B5_BWSCON<<20) + (B6_BWSCON<<24) + \
+			(B7_BWSCON<<28)))
+
+#define B0_CONF	((B0_Tacs<<13) + (B0_Tcos<<11) + (B0_Tacc<<8) + \
+		(B0_Tcoh<<6) + (B0_Tah<<4) + (B0_Tacp<<2) + (B0_PMC))
+#define B1_CONF	((B1_Tacs<<13) + (B1_Tcos<<11) + (B1_Tacc<<8) + \
+		(B1_Tcoh<<6) + (B1_Tah<<4) + (B1_Tacp<<2) + (B1_PMC))
+#define B2_CONF	((B2_Tacs<<13) + (B2_Tcos<<11) + (B2_Tacc<<8) + \
+		(B2_Tcoh<<6) + (B2_Tah<<4) + (B2_Tacp<<2) + (B2_PMC))
+#define B3_CONF	((B3_Tacs<<13) + (B3_Tcos<<11) + (B3_Tacc<<8) + \
+		(B3_Tcoh<<6) + (B3_Tah<<4) + (B3_Tacp<<2) + (B3_PMC))
+#define B4_CONF	((B4_Tacs<<13) + (B4_Tcos<<11) + (B4_Tacc<<8) + \
+		(B4_Tcoh<<6) + (B4_Tah<<4) + (B4_Tacp<<2) + (B4_PMC))
+#define B5_CONF	((B5_Tacs<<13) + (B5_Tcos<<11) + (B5_Tacc<<8) + \
+		(B5_Tcoh<<6) + (B5_Tah<<4) + (B5_Tacp<<2) + (B5_PMC))
+
+#define MEM_TIMING (REFEN<<23) + (TREFMD<<22) + (Trp<<20) + \
+	(Trc<<18) + (Tchr<<16) + REFCNT
+
+#define BANKSIZE_CONF	(BK76MAP) + (SCLK_EN<<4) + (SCKE_EN<<5) + (BURST_EN<<7)
+#define B6_MRSR			(CL<<4)
+#define B7_MRSR			(CL<<4)
+
+#endif
diff --git a/board/iomega/iconnect/Makefile b/board/iomega/iconnect/Makefile
new file mode 100644
index 0000000000..f77fcfb990
--- /dev/null
+++ b/board/iomega/iconnect/Makefile
@@ -0,0 +1,43 @@
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= iconnect.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/iomega/iconnect/iconnect.c b/board/iomega/iconnect/iconnect.c
new file mode 100644
index 0000000000..6ee2128aab
--- /dev/null
+++ b/board/iomega/iconnect/iconnect.c
@@ -0,0 +1,107 @@
+/*
+ * Copyright (C) 2009-2012
+ * Wojciech Dubowik <wojciech.dubowik@neratec.com>
+ * Luka Perkov <uboot@lukaperkov.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/kirkwood.h>
+#include <asm/arch/mpp.h>
+#include "iconnect.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+	/*
+	 * default gpio configuration
+	 * There are maximum 64 gpios controlled through 2 sets of registers
+	 * the below configuration configures mainly initial LED status
+	 */
+	kw_config_gpio(ICONNECT_OE_VAL_LOW,
+			ICONNECT_OE_VAL_HIGH,
+			ICONNECT_OE_LOW, ICONNECT_OE_HIGH);
+
+	/* Multi-Purpose Pins Functionality configuration */
+	u32 kwmpp_config[] = {
+		MPP0_NF_IO2,
+		MPP1_NF_IO3,
+		MPP2_NF_IO4,
+		MPP3_NF_IO5,
+		MPP4_NF_IO6,
+		MPP5_NF_IO7,
+		MPP6_SYSRST_OUTn,	/* Reset signal */
+		MPP7_GPO,
+		MPP8_TW_SDA,		/* I2C */	
+		MPP9_TW_SCK,		/* I2C */
+		MPP10_UART0_TXD,
+		MPP11_UART0_RXD,
+		MPP12_GPO,		/* Reset button */
+		MPP13_SD_CMD,
+		MPP14_SD_D0,
+		MPP15_SD_D1,
+		MPP16_SD_D2,
+		MPP17_SD_D3,
+		MPP18_NF_IO0,
+		MPP19_NF_IO1,
+		MPP20_GE1_0,
+		MPP21_GE1_1,
+		MPP22_GE1_2,
+		MPP23_GE1_3,
+		MPP24_GE1_4,
+		MPP25_GE1_5,
+		MPP26_GE1_6,
+		MPP27_GE1_7,
+		MPP28_GPIO,
+		MPP29_GPIO,
+		MPP30_GE1_10,
+		MPP31_GE1_11,
+		MPP32_GE1_12,
+		MPP33_GE1_13,
+		MPP34_GE1_14,
+		MPP35_GPIO,		/* OTB button */
+		MPP36_AUDIO_SPDIFI,
+		MPP37_AUDIO_SPDIFO,
+		MPP38_GPIO,
+		MPP39_TDM_SPI_CS0,
+		MPP40_TDM_SPI_SCK,
+		MPP41_GPIO,		/* LED brightness */
+		MPP42_GPIO,		/* LED power (blue) */
+		MPP43_GPIO,		/* LED power (red) */
+		MPP44_GPIO,		/* LED USB 1 */
+		MPP45_GPIO,		/* LED USB 2 */
+		MPP46_GPIO,		/* LED USB 3 */
+		MPP47_GPIO,		/* LED USB 4 */
+		MPP48_GPIO,		/* LED OTB */
+		MPP49_GPIO,
+		0
+	};
+	kirkwood_mpp_conf(kwmpp_config, NULL);
+	return 0;
+}
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+
+	return 0;
+}
diff --git a/board/iomega/iconnect/iconnect.h b/board/iomega/iconnect/iconnect.h
new file mode 100644
index 0000000000..2fb3e5ed8f
--- /dev/null
+++ b/board/iomega/iconnect/iconnect.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (C) 2009-2012
+ * Wojciech Dubowik <wojciech.dubowik@neratec.com>
+ * Luka Perkov <uboot@lukaperkov.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __ICONNECT_H
+#define __ICONNECT_H
+
+#define ICONNECT_OE_LOW			(~(1 << 7))
+#define ICONNECT_OE_HIGH		(~(1 << 10))
+#define ICONNECT_OE_VAL_LOW		(0)
+#define ICONNECT_OE_VAL_HIGH		(1 << 10)
+
+/* PHY related */
+#define MV88E1116_LED_FCTRL_REG		10
+#define MV88E1116_CPRSP_CR3_REG		21
+#define MV88E1116_MAC_CTRL_REG		21
+#define MV88E1116_PGADR_REG		22
+#define MV88E1116_RGMII_TXTM_CTRL	(1 << 4)
+#define MV88E1116_RGMII_RXTM_CTRL	(1 << 5)
+
+#endif /* __ICONNECT_H */
diff --git a/board/iomega/iconnect/kwbimage.cfg b/board/iomega/iconnect/kwbimage.cfg
new file mode 100644
index 0000000000..6c9dfe3d31
--- /dev/null
+++ b/board/iomega/iconnect/kwbimage.cfg
@@ -0,0 +1,165 @@
+#
+# (C) Copyright 2009-2012
+# Wojciech Dubowik <wojciech.dubowik@neratec.com>
+# Luka Perkov <uboot@lukaperkov.net>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM	nand
+NAND_ECC_MODE	default
+NAND_PAGE_SIZE	0x0800
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xffd100e0 0x1b1b1b9b
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xffd01400 0x43000c30	# DDR Configuration register
+# bit13-0:  0xc30, (3120 DDR2 clks refresh rate)
+# bit23-14: 0x0,
+# bit24:    0x1,   enable exit self refresh mode on DDR access
+# bit25:    0x1,   required
+# bit29-26: 0x0,
+# bit31-30: 0x1,
+
+DATA 0xffd01404 0x37543000	# DDR Controller Control Low
+# bit4:     0x0, addr/cmd in smame cycle
+# bit5:     0x0, clk is driven during self refresh, we don't care for APX
+# bit6:     0x0, use recommended falling edge of clk for addr/cmd
+# bit14:    0x0, input buffer always powered up
+# bit18:    0x1, cpu lock transaction enabled
+# bit23-20: 0x5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 0x7, CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 0x3, required
+# bit31:    0x0, no additional STARTBURST delay
+
+DATA 0xffd01408 0x22125451	# DDR Timing (Low) (active cycles value +1)
+# bit3-0:   TRAS lsbs
+# bit7-4:   TRCD
+# bit11-8:  TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20:    TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xffd0140c 0x00000a33	# DDR Timing (High)
+# bit6-0:   TRFC
+# bit8-7:   TR2R
+# bit10-9:  TR2W
+# bit12-11: TW2W
+# bit31-13: 0x0, required
+
+DATA 0xffd01410 0x000000cc	# DDR Address Control
+# bit1-0:   00,  Cs0width (x8)
+# bit3-2:   11,  Cs0size (1Gb)
+# bit5-4:   00,  Cs1width (x8)
+# bit7-6:   11,  Cs1size (1Gb)
+# bit9-8:   00,  Cs2width (nonexistent)
+# bit11-10: 00,  Cs2size (nonexistent)
+# bit13-12: 00,  Cs3width (nonexistent)
+# bit15-14: 00,  Cs3size (nonexistent)
+# bit16:    0,   Cs0AddrSel
+# bit17:    0,   Cs1AddrSel
+# bit18:    0,   Cs2AddrSel
+# bit19:    0,   Cs3AddrSel
+# bit31-20: 0x0, required
+
+DATA 0xffd01414 0x00000000	# DDR Open Pages Control
+# bit0:    0,   OpenPage enabled
+# bit31-1: 0x0, required
+
+DATA 0xffd01418 0x00000000	# DDR Operation
+# bit3-0:   0x0, DDR cmd
+# bit31-4:  0x0, required
+
+DATA 0xffd0141c 0x00000c52	# DDR Mode
+# bit2-0:   0x2, BurstLen=2 required
+# bit3:     0x0, BurstType=0 required
+# bit6-4:   0x4, CL=5
+# bit7:     0x0, TestMode=0 normal
+# bit8:     0x0, DLL reset=0 normal
+# bit11-9:  0x6, auto-precharge write recovery ????????????
+# bit12:    0x0, PD must be zero
+# bit31-13: 0x0, required
+
+DATA 0xffd01420 0x00000040	# DDR Extended Mode
+# bit0:     0,   DDR DLL enabled
+# bit1:     0,   DDR drive strenght normal
+# bit2:     0,   DDR ODT control lsd (disabled)
+# bit5-3:   0x0, required
+# bit6:     1,   DDR ODT control msb, (disabled)
+# bit9-7:   0x0, required
+# bit10:    0,   differential DQS enabled
+# bit11:    0,   required
+# bit12:    0,   DDR output buffer enabled
+# bit31-13: 0x0, required
+
+DATA 0xffd01424 0x0000f17f	# DDR Controller Control High
+# bit2-0:   0x7, required
+# bit3:     0x1, MBUS Burst Chop disabled
+# bit6-4:   0x7, required
+# bit7:     0x0,
+# bit8:     0x1, add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9:     0x0, no half clock cycle addition to dataout
+# bit10:    0x0, 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11:    0x0, 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 0xf, required
+# bit31-16: 0x0, required
+
+DATA 0xffd01428 0x00085520	# DDR2 ODT Read Timing (default values)
+DATA 0xffd0147c 0x00008552	# DDR2 ODT Write Timing (default values)
+
+DATA 0xffd01500 0x00000000	# CS[0]n Base address to 0x0
+DATA 0xffd01504 0x0ffffff1	# CS[0]n Size
+# bit0:     0x1,     Window enabled
+# bit1:     0x0,     Write Protect disabled
+# bit3-2:   0x0,     CS0 hit selected
+# bit23-4:  0xfffff, required
+# bit31-24: 0x0f,    Size (i.e. 256MB)
+
+DATA 0xffd01508 0x00000000	# CS[1]n Base address to 256Mb
+DATA 0xffd0150c 0x00000000	# CS[1]n Size, window disabled
+
+DATA 0xffd01514 0x00000000	# CS[2]n Size, window disabled
+DATA 0xffd0151c 0x00000000	# CS[3]n Size, window disabled
+
+DATA 0xffd01494 0x00030000	# DDR ODT Control (Low)
+# bit3-0:     ODT0Rd, MODT[0] asserted during read from DRAM CS1
+# bit7-4:     ODT0Rd, MODT[0] asserted during read from DRAM CS0
+# bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1
+# bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
+
+DATA 0xffd01498 0x00000000	# DDR ODT Control (High)
+# bit1-0:  0x0, ODT0 controlled by ODT Control (low) register above
+# bit3-2:  0x1, ODT1 active NEVER!
+# bit31-4: 0x0, required
+
+DATA 0xffd0149c 0x0000e803	# CPU ODT Control
+DATA 0xffd01480 0x00000001	# DDR Initialization Control
+# bit0: 0x1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/board/karo/tx25/lowlevel_init.S b/board/karo/tx25/lowlevel_init.S
index 823df10701..eb3f187806 100644
--- a/board/karo/tx25/lowlevel_init.S
+++ b/board/karo/tx25/lowlevel_init.S
@@ -67,6 +67,14 @@
 	write32	0x53f80008, 0x20034000
 
 	/*
+	 * PCDR2: NFC = 33.25 MHz
+	 * This is required for the NAND Flash of this board, which is a Samsung
+	 * K9F1G08U0B with 25-ns R/W cycle times, in order to make it work with
+	 * the NFC driver in symmetric (i.e. one-cycle) mode.
+	 */
+	write32	0x53f80020, 0x01010103
+
+	/*
 	 * enable all implemented clocks in all three
 	 * clock control registers
 	 */
diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c
index be8f51c2fc..0c4dddc617 100644
--- a/board/keymile/km_arm/km_arm.c
+++ b/board/keymile/km_arm/km_arm.c
@@ -250,7 +250,8 @@ int board_early_init_f(void)
 	tmp = readl(KW_GPIO0_BASE + 4);
 	writel(tmp & (~KM_KIRKWOOD_SOFT_I2C_GPIOS) , KW_GPIO0_BASE + 4);
 #endif
-
+	/* adjust SDRAM size for bank 0 */
+	kw_sdram_size_adjust(0);
 	kirkwood_mpp_conf(kwmpp_config, NULL);
 	return 0;
 }
@@ -365,6 +366,71 @@ void reset_phy(void)
 	/* reset the phy */
 	miiphy_reset(name, CONFIG_PHY_BASE_ADR);
 }
+#elif defined(CONFIG_KM_PIGGY4_88E6352)
+
+#include <mv88e6352.h>
+
+#if defined(CONFIG_KM_NUSA)
+struct mv88e_sw_reg extsw_conf[] = {
+	/*
+	 * port 0, PIGGY4, autoneg 
+	 * first the fix for the 1000Mbits Autoneg, this is from
+	 * a Marvell errata, the regs are undocumented
+	 */
+	{ PHY(0), PHY_PAGE, AN1000FIX_PAGE },
+	{ PHY(0), PHY_STATUS, AN1000FIX },
+	{ PHY(0), PHY_PAGE, 0 },
+	/* now the real port and phy configuration */
+	{ PORT(0), PORT_PHY, NO_SPEED_FOR },
+	{ PORT(0), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
+	{ PHY(0), PHY_1000_CTRL, NO_ADV },
+	{ PHY(0), PHY_SPEC_CTRL, AUTO_MDIX_EN },
+	{ PHY(0), PHY_CTRL, PHY_100_MBPS | AUTONEG_EN | AUTONEG_RST |
+		FULL_DUPLEX },
+	/* port 1, unused */
+	{ PORT(1), PORT_CTRL, PORT_DIS },
+	{ PHY(1), PHY_CTRL, PHY_PWR_DOWN },
+	{ PHY(1), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
+	/* port 2, unused */
+	{ PORT(2), PORT_CTRL, PORT_DIS },
+	{ PHY(2), PHY_CTRL, PHY_PWR_DOWN },
+	{ PHY(2), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
+	/* port 3, unused */
+	{ PORT(3), PORT_CTRL, PORT_DIS },
+	{ PHY(3), PHY_CTRL, PHY_PWR_DOWN },
+	{ PHY(3), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
+	/* port 4, ICNEV, SerDes, SGMII */
+	{ PORT(4), PORT_STATUS, NO_PHY_DETECT },
+	{ PORT(4), PORT_PHY, SPEED_1000_FOR },
+	{ PORT(4), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
+	{ PHY(4), PHY_CTRL, PHY_PWR_DOWN },
+	{ PHY(4), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
+	/* port 5, CPU_RGMII */
+	{ PORT(5), PORT_PHY, RX_RGMII_TIM | TX_RGMII_TIM | FLOW_CTRL_EN |
+		FLOW_CTRL_FOR | LINK_VAL | LINK_FOR | FULL_DPX |
+		FULL_DPX_FOR | SPEED_1000_FOR },
+	{ PORT(5), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
+	/* port 6, unused, this port has no phy */
+	{ PORT(6), PORT_CTRL, PORT_DIS },
+};
+#else
+struct mv88e_sw_reg extsw_conf[] = {};
+#endif
+
+void reset_phy(void)
+{
+#if defined(CONFIG_KM_MVEXTSW_ADDR)
+	char *name = "egiga0";
+
+	if (miiphy_set_current_dev(name))
+		return;
+
+	mv88e_sw_program(name, CONFIG_KM_MVEXTSW_ADDR, extsw_conf,
+		ARRAY_SIZE(extsw_conf));
+	mv88e_sw_reset(name, CONFIG_KM_MVEXTSW_ADDR);
+#endif
+}
+
 #else
 /* Configure and enable MV88E1118 PHY on the piggy*/
 void reset_phy(void)
diff --git a/board/kmc/kzm9g/Makefile b/board/kmc/kzm9g/Makefile
new file mode 100644
index 0000000000..bae79f5088
--- /dev/null
+++ b/board/kmc/kzm9g/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+# (C) Copyright 2012 Renesas Solutions Corp.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= kzm9g.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj) .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/kmc/kzm9g/kzm9g.c b/board/kmc/kzm9g/kzm9g.c
new file mode 100644
index 0000000000..525c97aea6
--- /dev/null
+++ b/board/kmc/kzm9g/kzm9g.c
@@ -0,0 +1,377 @@
+/*
+ * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ * (C) Copyright 2012 Renesas Solutions Corp.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <netdev.h>
+#include <i2c.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CS0BCR_D (0x06C00400)
+#define CS4BCR_D (0x16c90400)
+#define CS0WCR_D (0x55062C42)
+#define CS4WCR_D (0x1e071dc3)
+
+#define CMNCR_BROMMD0   (1 << 21)
+#define CMNCR_BROMMD1   (1 << 22)
+#define CMNCR_BROMMD	(CMNCR_BROMMD0|CMNCR_BROMMD1)
+#define VCLKCR1_D	(0x27)
+
+#define SMSTPCR1_CMT0	(1 << 24)
+#define SMSTPCR1_I2C0	(1 << 16)
+#define SMSTPCR3_USB	(1 << 22)
+
+#define PORT32CR (0xE6051020)
+#define PORT33CR (0xE6051021)
+#define PORT34CR (0xE6051022)
+#define PORT35CR (0xE6051023)
+
+static int cmp_loop(u32 *addr, u32 data, u32 cmp)
+{
+	int err = -1;
+	int timeout = 100;
+	u32 value;
+
+	while (timeout > 0) {
+		value = readl(addr);
+		if ((value & data) == cmp) {
+			err = 0;
+			break;
+		}
+		timeout--;
+	}
+
+	return err;
+}
+
+/* SBSC Init function */
+static void sbsc_init(struct sh73a0_sbsc *sbsc)
+{
+	writel(readl(&sbsc->dllcnt0)|0x2, &sbsc->dllcnt0);
+	writel(0x5, &sbsc->sdgencnt);
+	cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0);
+
+	writel(0xacc90159, &sbsc->sdcr0);
+	writel(0x00010059, &sbsc->sdcr1);
+	writel(0x50874114, &sbsc->sdwcrc0);
+	writel(0x33199b37, &sbsc->sdwcrc1);
+	writel(0x008f2313, &sbsc->sdwcrc2);
+	writel(0x31020707, &sbsc->sdwcr00);
+	writel(0x0017040a, &sbsc->sdwcr01);
+	writel(0x31020707, &sbsc->sdwcr10);
+	writel(0x0017040a, &sbsc->sdwcr11);
+	writel(0x05555555, &sbsc->sddrvcr0);
+	writel(0x30000000, &sbsc->sdwcr2);
+
+	writel(readl(&sbsc->sdpcr) | 0x80, &sbsc->sdpcr);
+	cmp_loop(&sbsc->sdpcr, 0x80, 0x80);
+
+	writel(0x00002710, &sbsc->sdgencnt);
+	cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0);
+
+	writel(0x0000003f, &sbsc->sdmracr0);
+	writel(0x0, SDMRA1A);
+	writel(0x000001f4, &sbsc->sdgencnt);
+	cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0);
+
+	writel(0x0000ff0a, &sbsc->sdmracr0);
+	if (sbsc == (struct sh73a0_sbsc *)SBSC1_BASE)
+		writel(0x0, SDMRA3A);
+	else
+		writel(0x0, SDMRA3B);
+
+	writel(0x00000032, &sbsc->sdgencnt);
+	cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0);
+
+	if (sbsc == (struct sh73a0_sbsc *)SBSC1_BASE) {
+		writel(0x00002201, &sbsc->sdmracr0);
+		writel(0x0, SDMRA1A);
+		writel(0x00000402, &sbsc->sdmracr0);
+		writel(0x0, SDMRA1A);
+		writel(0x00000403, &sbsc->sdmracr0);
+		writel(0x0, SDMRA1A);
+		writel(0x0, SDMRA2A);
+	} else {
+		writel(0x00002201, &sbsc->sdmracr0);
+		writel(0x0, SDMRA1B);
+		writel(0x00000402, &sbsc->sdmracr0);
+		writel(0x0, SDMRA1B);
+		writel(0x00000403, &sbsc->sdmracr0);
+		writel(0x0, SDMRA1B);
+		writel(0x0, SDMRA2B);
+	}
+
+	writel(0x88800004, &sbsc->sdmrtmpcr);
+	writel(0x00000004, &sbsc->sdmrtmpmsk);
+	writel(0xa55a0032, &sbsc->rtcor);
+	writel(0xa55a000c, &sbsc->rtcorh);
+	writel(0xa55a2048, &sbsc->rtcsr);
+	writel(readl(&sbsc->sdcr0)|0x800, &sbsc->sdcr0);
+	writel(readl(&sbsc->sdcr1)|0x400, &sbsc->sdcr1);
+	writel(0xfff20000, &sbsc->zqccr);
+
+	/* SCBS2 only */
+	if (sbsc == (struct sh73a0_sbsc *)SBSC2_BASE) {
+		writel(readl(&sbsc->sdpdcr0)|0x00030000, &sbsc->sdpdcr0);
+		writel(0xa5390000, &sbsc->dphycnt1);
+		writel(0x00001200, &sbsc->dphycnt0);
+		writel(0x07ce0000, &sbsc->dphycnt1);
+		writel(0x00001247, &sbsc->dphycnt0);
+		cmp_loop(&sbsc->dphycnt2, 0xffffffff, 0x07ce0000);
+		writel(readl(&sbsc->sdpdcr0) & 0xfffcffff, &sbsc->sdpdcr0);
+	}
+}
+
+void s_init(void)
+{
+	struct sh73a0_rwdt *rwdt = (struct sh73a0_rwdt *)RWDT_BASE;
+	struct sh73a0_sbsc_cpg *cpg = (struct sh73a0_sbsc_cpg *)CPG_BASE;
+	struct sh73a0_sbsc_cpg_srcr *cpg_srcr =
+		(struct sh73a0_sbsc_cpg_srcr *)CPG_SRCR_BASE;
+	struct sh73a0_sbsc *sbsc1 = (struct sh73a0_sbsc *)SBSC1_BASE;
+	struct sh73a0_sbsc *sbsc2 = (struct sh73a0_sbsc *)SBSC2_BASE;
+	struct sh73a0_hpb *hpb = (struct sh73a0_hpb *)HPB_BASE;
+	struct sh73a0_hpb_bscr *hpb_bscr =
+		(struct sh73a0_hpb_bscr *)HPBSCR_BASE;
+
+	/* Watchdog init */
+	writew(0xA507, &rwdt->rwtcsra0);
+
+	/* Secure control register Init */
+	#define LIFEC_SEC_SRC_BIT	(1 << 15)
+	writel(readl(LIFEC_SEC_SRC) & ~LIFEC_SEC_SRC_BIT, LIFEC_SEC_SRC);
+
+	clrbits_le32(&cpg->smstpcr3, (1 << 15));
+	clrbits_le32(&cpg_srcr->srcr3, (1 << 15));
+	clrbits_le32(&cpg->smstpcr2, (1 << 18));
+	clrbits_le32(&cpg_srcr->srcr2, (1 << 18));
+	writel(0x0, &cpg->pllecr);
+
+	cmp_loop(&cpg->pllecr, 0x00000F00, 0x0);
+	cmp_loop(&cpg->frqcrb, 0x80000000, 0x0);
+
+	writel(0x2D000000, &cpg->pll0cr);
+	writel(0x17100000, &cpg->pll1cr);
+	writel(0x96235880, &cpg->frqcrb);
+	cmp_loop(&cpg->frqcrb, 0x80000000, 0x0);
+
+	writel(0xB, &cpg->flckcr);
+	clrbits_le32(&cpg->smstpcr0, (1 << 1));
+
+	clrbits_le32(&cpg_srcr->srcr0, (1 << 1));
+	writel(0x0514, &hpb_bscr->smgpiotime);
+	writel(0x0514, &hpb_bscr->smcmt2time);
+	writel(0x0514, &hpb_bscr->smcpgtime);
+	writel(0x0514, &hpb_bscr->smsysctime);
+
+	writel(0x00092000, &cpg->dvfscr4);
+	writel(0x000000DC, &cpg->dvfscr5);
+	writel(0x0, &cpg->pllecr);
+	cmp_loop(&cpg->pllecr, 0x00000F00, 0x0);
+
+	/* FRQCR Init */
+	writel(0x0012453C, &cpg->frqcra);
+	writel(0x80331350, &cpg->frqcrb);
+	cmp_loop(&cpg->frqcrb, 0x80000000, 0x0);
+	writel(0x00000B0B, &cpg->frqcrd);
+	cmp_loop(&cpg->frqcrd, 0x80000000, 0x0);
+
+	/* Clock Init */
+	writel(0x00000003, PCLKCR);
+	writel(0x0000012F, &cpg->vclkcr1);
+	writel(0x00000119, &cpg->vclkcr2);
+	writel(0x00000119, &cpg->vclkcr3);
+	writel(0x00000002, &cpg->zbckcr);
+	writel(0x00000005, &cpg->flckcr);
+	writel(0x00000080, &cpg->sd0ckcr);
+	writel(0x00000080, &cpg->sd1ckcr);
+	writel(0x00000080, &cpg->sd2ckcr);
+	writel(0x0000003F, &cpg->fsiackcr);
+	writel(0x0000003F, &cpg->fsibckcr);
+	writel(0x00000080, &cpg->subckcr);
+	writel(0x0000000B, &cpg->spuackcr);
+	writel(0x0000000B, &cpg->spuvckcr);
+	writel(0x0000013F, &cpg->msuckcr);
+	writel(0x00000080, &cpg->hsickcr);
+	writel(0x0000003F, &cpg->mfck1cr);
+	writel(0x0000003F, &cpg->mfck2cr);
+	writel(0x00000107, &cpg->dsitckcr);
+	writel(0x00000313, &cpg->dsi0pckcr);
+	writel(0x0000130D, &cpg->dsi1pckcr);
+	writel(0x2A800E0E, &cpg->dsi0phycr);
+	writel(0x1E000000, &cpg->pll0cr);
+	writel(0x2D000000, &cpg->pll0cr);
+	writel(0x17100000, &cpg->pll1cr);
+	writel(0x27000080, &cpg->pll2cr);
+	writel(0x1D000000, &cpg->pll3cr);
+	writel(0x00080000, &cpg->pll0stpcr);
+	writel(0x000120C0, &cpg->pll1stpcr);
+	writel(0x00012000, &cpg->pll2stpcr);
+	writel(0x00000030, &cpg->pll3stpcr);
+
+	writel(0x0000000B, &cpg->pllecr);
+	cmp_loop(&cpg->pllecr, 0x00000B00, 0x00000B00);
+
+	writel(0x000120F0, &cpg->dvfscr3);
+	writel(0x00000020, &cpg->mpmode);
+	writel(0x0000028A, &cpg->vrefcr);
+	writel(0xE4628087, &cpg->rmstpcr0);
+	writel(0xFFFFFFFF, &cpg->rmstpcr1);
+	writel(0x53FFFFFF, &cpg->rmstpcr2);
+	writel(0xFFFFFFFF, &cpg->rmstpcr3);
+	writel(0x00800D3D, &cpg->rmstpcr4);
+	writel(0xFFFFF3FF, &cpg->rmstpcr5);
+	writel(0x00000000, &cpg->smstpcr2);
+	writel(0x00040000, &cpg_srcr->srcr2);
+
+	clrbits_le32(&cpg->pllecr, (1 << 3));
+	cmp_loop(&cpg->pllecr, 0x00000800, 0x0);
+
+	writel(0x00000001, &hpb->hpbctrl6);
+	cmp_loop(&hpb->hpbctrl6, 0x1, 0x1);
+
+	writel(0x00001414, &cpg->frqcrd);
+	cmp_loop(&cpg->frqcrd, 0x80000000, 0x0);
+
+	writel(0x1d000000, &cpg->pll3cr);
+	setbits_le32(&cpg->pllecr, (1 << 3));
+	cmp_loop(&cpg->pllecr, 0x800, 0x800);
+
+	/* SBSC1 Init*/
+	sbsc_init(sbsc1);
+
+	/* SBSC2 Init*/
+	sbsc_init(sbsc2);
+
+	writel(0x00000b0b, &cpg->frqcrd);
+	cmp_loop(&cpg->frqcrd, 0x80000000, 0x0);
+	writel(0xfffffffc, &cpg->cpgxxcs4);
+}
+
+int board_early_init_f(void)
+{
+	struct sh73a0_sbsc_cpg *cpg = (struct sh73a0_sbsc_cpg *)CPG_BASE;
+	struct sh73a0_bsc *bsc = (struct sh73a0_bsc *)BSC_BASE;
+	struct sh73a0_sbsc_cpg_srcr *cpg_srcr =
+		(struct sh73a0_sbsc_cpg_srcr *)CPG_SRCR_BASE;
+
+	writel(CS0BCR_D, &bsc->cs0bcr);
+	writel(CS4BCR_D, &bsc->cs4bcr);
+	writel(CS0WCR_D, &bsc->cs0wcr);
+	writel(CS4WCR_D, &bsc->cs4wcr);
+
+	clrsetbits_le32(&bsc->cmncr, ~CMNCR_BROMMD, CMNCR_BROMMD);
+
+	clrbits_le32(&cpg->smstpcr1, (SMSTPCR1_CMT0|SMSTPCR1_I2C0));
+	clrbits_le32(&cpg_srcr->srcr1, (SMSTPCR1_CMT0|SMSTPCR1_I2C0));
+	clrbits_le32(&cpg->smstpcr3, SMSTPCR3_USB);
+	clrbits_le32(&cpg_srcr->srcr3, SMSTPCR3_USB);
+	writel(VCLKCR1_D, &cpg->vclkcr1);
+
+	/* Setup SCIF4 / workaround */
+	writeb(0x12, PORT32CR);
+	writeb(0x22, PORT33CR);
+	writeb(0x12, PORT34CR);
+	writeb(0x22, PORT35CR);
+
+	return 0;
+}
+
+int board_init(void)
+{
+	sh73a0_pinmux_init();
+
+    /* SCIFA 4 */
+	gpio_request(GPIO_FN_SCIFA4_TXD, NULL);
+	gpio_request(GPIO_FN_SCIFA4_RXD, NULL);
+	gpio_request(GPIO_FN_SCIFA4_RTS_, NULL);
+	gpio_request(GPIO_FN_SCIFA4_CTS_, NULL);
+
+	/* Ethernet/SMSC */
+	gpio_request(GPIO_PORT224, NULL);
+	gpio_direction_input(GPIO_PORT224);
+
+	/* SMSC/USB */
+	gpio_request(GPIO_FN_CS4_, NULL);
+
+	/* MMCIF */
+	gpio_request(GPIO_FN_MMCCLK0, NULL);
+	gpio_request(GPIO_FN_MMCCMD0_PU, NULL);
+	gpio_request(GPIO_FN_MMCD0_0_PU, NULL);
+	gpio_request(GPIO_FN_MMCD0_1_PU, NULL);
+	gpio_request(GPIO_FN_MMCD0_2_PU, NULL);
+	gpio_request(GPIO_FN_MMCD0_3_PU, NULL);
+	gpio_request(GPIO_FN_MMCD0_4_PU, NULL);
+	gpio_request(GPIO_FN_MMCD0_5_PU, NULL);
+	gpio_request(GPIO_FN_MMCD0_6_PU, NULL);
+	gpio_request(GPIO_FN_MMCD0_7_PU, NULL);
+
+	/* SDHI */
+	gpio_request(GPIO_FN_SDHIWP0, NULL);
+	gpio_request(GPIO_FN_SDHICD0, NULL);
+	gpio_request(GPIO_FN_SDHICMD0, NULL);
+	gpio_request(GPIO_FN_SDHICLK0,  NULL);
+	gpio_request(GPIO_FN_SDHID0_3,  NULL);
+	gpio_request(GPIO_FN_SDHID0_2,  NULL);
+	gpio_request(GPIO_FN_SDHID0_1,  NULL);
+	gpio_request(GPIO_FN_SDHID0_0,  NULL);
+	gpio_request(GPIO_FN_SDHI0_VCCQ_MC0_ON, NULL);
+	gpio_request(GPIO_PORT15, NULL);
+	gpio_direction_output(GPIO_PORT15, 1);
+
+	/* I2C */
+	gpio_request(GPIO_FN_PORT27_I2C_SCL3, NULL);
+	gpio_request(GPIO_FN_PORT28_I2C_SDA3, NULL);
+
+	gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
+
+	return 0;
+}
+
+const struct rmobile_sysinfo sysinfo = {
+	CONFIG_RMOBILE_BOARD_STRING
+};
+
+int dram_init(void)
+{
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	int ret = 0;
+#ifdef CONFIG_SMC911X
+	ret = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+	return ret;
+}
+
+void reset_cpu(ulong addr)
+{
+	/* Soft Power On Reset */
+	writel((1 << 31), RESCNT2);
+}
diff --git a/board/raidsonic/ib62x0/ib62x0.c b/board/raidsonic/ib62x0/ib62x0.c
index 1164d6bf3f..b7e6e4107c 100644
--- a/board/raidsonic/ib62x0/ib62x0.c
+++ b/board/raidsonic/ib62x0/ib62x0.c
@@ -23,6 +23,7 @@
 
 #include <common.h>
 #include <miiphy.h>
+#include <asm/io.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/kirkwood.h>
 #include <asm/arch/mpp.h>
@@ -41,6 +42,8 @@ int board_early_init_f(void)
 			IB62x0_OE_VAL_HIGH,
 			IB62x0_OE_LOW, IB62x0_OE_HIGH);
 
+	/* Set SATA activity LEDs to default off */
+	writel(MVSATAHC_LED_POLARITY_CTRL, MVSATAHC_LED_CONF_REG);
 	/* Multi-Purpose Pins Functionality configuration */
 	u32 kwmpp_config[] = {
 		MPP0_NF_IO2,
diff --git a/board/raidsonic/ib62x0/ib62x0.h b/board/raidsonic/ib62x0/ib62x0.h
index 0c30690697..0118c2b69a 100644
--- a/board/raidsonic/ib62x0/ib62x0.h
+++ b/board/raidsonic/ib62x0/ib62x0.h
@@ -37,4 +37,8 @@
 #define MV88E1116_RGMII_TXTM_CTRL	(1 << 4)
 #define MV88E1116_RGMII_RXTM_CTRL	(1 << 5)
 
+/* SATAHC related */
+#define MVSATAHC_LED_CONF_REG       (MV_SATA_BASE + 0x2C)
+#define MVSATAHC_LED_POLARITY_CTRL  (1 << 3)
+
 #endif /* __IB62x0_H */
diff --git a/board/spear/x600/Makefile b/board/spear/x600/Makefile
new file mode 100644
index 0000000000..8c4e7e2987
--- /dev/null
+++ b/board/spear/x600/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+ifndef CONFIG_SPL_BUILD
+COBJS	:= fpga.o $(BOARD).o
+endif
+SOBJS	:=
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/spear/x600/fpga.c b/board/spear/x600/fpga.c
new file mode 100644
index 0000000000..85eb31be7b
--- /dev/null
+++ b/board/spear/x600/fpga.c
@@ -0,0 +1,280 @@
+/*
+ * Copyright (C) 2012 Stefan Roese <sr@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <spartan3.h>
+#include <command.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/spr_misc.h>
+#include <asm/arch/spr_ssp.h>
+
+/*
+ * FPGA program pin configuration on X600:
+ *
+ * Only PROG and DONE are connected to GPIOs. INIT is not connected to the
+ * SoC at all. And CLOCK and DATA are connected to the SSP2 port. We use
+ * 16bit serial writes via this SSP port to write the data bits into the
+ * FPGA.
+ */
+#define CONFIG_SYS_FPGA_PROG		2
+#define CONFIG_SYS_FPGA_DONE		3
+
+/*
+ * Set the active-low FPGA reset signal.
+ */
+static void fpga_reset(int assert)
+{
+	/*
+	 * On x600 we have no means to toggle the FPGA reset signal
+	 */
+	debug("%s:%d: RESET (%d)\n", __func__, __LINE__, assert);
+}
+
+/*
+ * Set the FPGA's active-low SelectMap program line to the specified level
+ */
+static int fpga_pgm_fn(int assert, int flush, int cookie)
+{
+	debug("%s:%d: FPGA PROG (%d)\n", __func__, __LINE__, assert);
+
+	gpio_set_value(CONFIG_SYS_FPGA_PROG, assert);
+
+	return assert;
+}
+
+/*
+ * Test the state of the active-low FPGA INIT line.  Return 1 on INIT
+ * asserted (low).
+ */
+static int fpga_init_fn(int cookie)
+{
+	static int state;
+
+	debug("%s:%d: init (state=%d)\n", __func__, __LINE__, state);
+
+	/*
+	 * On x600, the FPGA INIT signal is not connected to the SoC.
+	 * We can't read the INIT status. Let's return the "correct"
+	 * INIT signal state generated via a local state-machine.
+	 */
+	if (++state == 1) {
+		return 1;
+	} else {
+		state = 0;
+		return 0;
+	}
+}
+
+/*
+ * Test the state of the active-high FPGA DONE pin
+ */
+static int fpga_done_fn(int cookie)
+{
+	struct ssp_regs *ssp = (struct ssp_regs *)CONFIG_SSP2_BASE;
+
+	/*
+	 * Wait for Tx-FIFO to become empty before looking for DONE
+	 */
+	while (!(readl(&ssp->sspsr) & SSPSR_TFE))
+		;
+
+	if (gpio_get_value(CONFIG_SYS_FPGA_DONE))
+		return 1;
+	else
+		return 0;
+}
+
+/*
+ * FPGA pre-configuration function. Just make sure that
+ * FPGA reset is asserted to keep the FPGA from starting up after
+ * configuration.
+ */
+static int fpga_pre_config_fn(int cookie)
+{
+	debug("%s:%d: FPGA pre-configuration\n", __func__, __LINE__);
+	fpga_reset(TRUE);
+
+	return 0;
+}
+
+/*
+ * FPGA post configuration function. Blip the FPGA reset line and then see if
+ * the FPGA appears to be running.
+ */
+static int fpga_post_config_fn(int cookie)
+{
+	int rc = 0;
+
+	debug("%s:%d: FPGA post configuration\n", __func__, __LINE__);
+
+	fpga_reset(TRUE);
+	udelay(100);
+	fpga_reset(FALSE);
+	udelay(100);
+
+	return rc;
+}
+
+static int fpga_clk_fn(int assert_clk, int flush, int cookie)
+{
+	/*
+	 * No dedicated clock signal on x600 (data & clock generated)
+	 * in SSP interface. So we don't have to do anything here.
+	 */
+	return assert_clk;
+}
+
+static int fpga_wr_fn(int assert_write, int flush, int cookie)
+{
+	struct ssp_regs *ssp = (struct ssp_regs *)CONFIG_SSP2_BASE;
+	static int count;
+	static u16 data;
+
+	/*
+	 * First collect 16 bits of data
+	 */
+	data = data << 1;
+	if (assert_write)
+		data |= 1;
+
+	/*
+	 * If 16 bits are not available, return for more bits
+	 */
+	count++;
+	if (count != 16)
+		return assert_write;
+
+	count = 0;
+
+	/*
+	 * Wait for Tx-FIFO to become ready
+	 */
+	while (!(readl(&ssp->sspsr) & SSPSR_TNF))
+		;
+
+	/* Send 16 bits to FPGA via SSP bus */
+	writel(data, &ssp->sspdr);
+
+	return assert_write;
+}
+
+static Xilinx_Spartan3_Slave_Serial_fns x600_fpga_fns = {
+	fpga_pre_config_fn,
+	fpga_pgm_fn,
+	fpga_clk_fn,
+	fpga_init_fn,
+	fpga_done_fn,
+	fpga_wr_fn,
+	fpga_post_config_fn,
+};
+
+static Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
+	XILINX_XC3S1200E_DESC(slave_serial, &x600_fpga_fns, 0)
+};
+
+/*
+ * Initialize the SelectMap interface.  We assume that the mode and the
+ * initial state of all of the port pins have already been set!
+ */
+static void fpga_serialslave_init(void)
+{
+	debug("%s:%d: Initialize serial slave interface\n", __func__, __LINE__);
+	fpga_pgm_fn(FALSE, FALSE, 0);	/* make sure program pin is inactive */
+}
+
+static int expi_setup(int freq)
+{
+	struct misc_regs *misc = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+	int pll2_m, pll2_n, pll2_p, expi_x, expi_y;
+
+	pll2_m = (freq * 2) / 1000;
+	pll2_n = 15;
+	pll2_p = 1;
+	expi_x = 1;
+	expi_y = 2;
+
+	/*
+	 * Disable reset, Low compression, Disable retiming, Enable Expi,
+	 * Enable soft reset, DMA, PLL2, Internal
+	 */
+	writel(EXPI_CLK_CFG_LOW_COMPR | EXPI_CLK_CFG_CLK_EN | EXPI_CLK_CFG_RST |
+	       EXPI_CLK_SYNT_EN | EXPI_CLK_CFG_SEL_PLL2 |
+	       EXPI_CLK_CFG_INT_CLK_EN | (expi_y << 16) | (expi_x << 24),
+	       &misc->expi_clk_cfg);
+
+	/*
+	 * 6 uA, Internal feedback, 1st order, Non-dithered, Sample Parameters,
+	 * Enable PLL2, Disable reset
+	 */
+	writel((pll2_m << 24) | (pll2_p << 8) | (pll2_n), &misc->pll2_frq);
+	writel(PLL2_CNTL_6UA | PLL2_CNTL_SAMPLE | PLL2_CNTL_ENABLE |
+	       PLL2_CNTL_RESETN | PLL2_CNTL_LOCK, &misc->pll2_cntl);
+
+	/*
+	 * Disable soft reset
+	 */
+	clrbits_le32(&misc->expi_clk_cfg, EXPI_CLK_CFG_RST);
+
+	return 0;
+}
+
+/*
+ * Initialize the fpga
+ */
+int x600_init_fpga(void)
+{
+	struct ssp_regs *ssp = (struct ssp_regs *)CONFIG_SSP2_BASE;
+	struct misc_regs *misc = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+
+	/* Enable SSP2 clock */
+	writel(readl(&misc->periph1_clken) | MISC_SSP2ENB | MISC_GPIO4ENB,
+	       &misc->periph1_clken);
+
+	/* Set EXPI clock to 45 MHz */
+	expi_setup(45000);
+
+	/* Configure GPIO directions */
+	gpio_direction_output(CONFIG_SYS_FPGA_PROG, 0);
+	gpio_direction_input(CONFIG_SYS_FPGA_DONE);
+
+	writel(SSPCR0_DSS_16BITS, &ssp->sspcr0);
+	writel(SSPCR1_SSE, &ssp->sspcr1);
+
+	/*
+	 * Set lowest prescale divisor value (CPSDVSR) of 2 for max download
+	 * speed.
+	 *
+	 * Actual data clock rate is: 80MHz / (CPSDVSR * (SCR + 1))
+	 * With CPSDVSR at 2 and SCR at 0, the maximume clock rate is 40MHz.
+	 */
+	writel(2, &ssp->sspcpsr);
+
+	fpga_init();
+	fpga_serialslave_init();
+
+	debug("%s:%d: Adding fpga 0\n", __func__, __LINE__);
+	fpga_add(fpga_xilinx, &fpga[0]);
+
+	return 0;
+}
diff --git a/board/spear/x600/fpga.h b/board/spear/x600/fpga.h
new file mode 100644
index 0000000000..2b1855716b
--- /dev/null
+++ b/board/spear/x600/fpga.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2012 Stefan Roese <sr@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+int x600_init_fpga(void);
diff --git a/board/spear/x600/x600.c b/board/spear/x600/x600.c
new file mode 100644
index 0000000000..96ec0ad8a5
--- /dev/null
+++ b/board/spear/x600/x600.c
@@ -0,0 +1,124 @@
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ *
+ * Copyright (C) 2012 Stefan Roese <sr@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <nand.h>
+#include <netdev.h>
+#include <phy.h>
+#include <rtc.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/spr_defs.h>
+#include <asm/arch/spr_misc.h>
+#include <linux/mtd/fsmc_nand.h>
+#include "fpga.h"
+
+static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
+
+int board_init(void)
+{
+	/*
+	 * X600 is equipped with an M41T82 RTC. This RTC has the
+	 * HT bit (Halt Update), which needs to be cleared upon
+	 * power-up. Otherwise the RTC is halted.
+	 */
+	rtc_reset();
+
+	return spear_board_init(MACH_TYPE_SPEAR600);
+}
+
+int board_late_init(void)
+{
+	/*
+	 * Monitor and env protection on by default
+	 */
+	flash_protect(FLAG_PROTECT_SET,
+		      CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE +
+		      CONFIG_SYS_SPL_LEN + CONFIG_SYS_MONITOR_LEN +
+		      2 * CONFIG_ENV_SECT_SIZE - 1,
+		      &flash_info[0]);
+
+	/* Init FPGA subsystem */
+	x600_init_fpga();
+
+	return 0;
+}
+
+/*
+ * board_nand_init - Board specific NAND initialization
+ * @nand:	mtd private chip structure
+ *
+ * Called by nand_init_chip to initialize the board specific functions
+ */
+
+void board_nand_init(void)
+{
+	struct misc_regs *const misc_regs_p =
+		(struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+	struct nand_chip *nand = &nand_chip[0];
+
+	if (!(readl(&misc_regs_p->auto_cfg_reg) & MISC_NANDDIS))
+		fsmc_nand_init(nand);
+}
+
+int designware_board_phy_init(struct eth_device *dev, int phy_addr,
+	int (*mii_write)(struct eth_device *, u8, u8, u16),
+	int dw_reset_phy(struct eth_device *))
+{
+	/* Extended PHY control 1, select GMII */
+	mii_write(dev, phy_addr, 23, 0x0020);
+
+	/* Software reset necessary after GMII mode selction */
+	dw_reset_phy(dev);
+
+	/* Enable extended page register access */
+	mii_write(dev, phy_addr, 31, 0x0001);
+
+	/* 17e: Enhanced LED behavior, needs to be written twice */
+	mii_write(dev, phy_addr, 17, 0x09ff);
+	mii_write(dev, phy_addr, 17, 0x09ff);
+
+	/* 16e: Enhanced LED method select */
+	mii_write(dev, phy_addr, 16, 0xe0ea);
+
+	/* Disable extended page register access */
+	mii_write(dev, phy_addr, 31, 0x0000);
+
+	/* Enable clock output pin */
+	mii_write(dev, phy_addr, 18, 0x0049);
+
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	int ret = 0;
+
+	if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_PHY_ADDR,
+				  PHY_INTERFACE_MODE_GMII) >= 0)
+		ret++;
+
+	return ret;
+}
diff --git a/board/st-ericsson/snowball/snowball.c b/board/st-ericsson/snowball/snowball.c
index 8c743c0adb..e750df189d 100644
--- a/board/st-ericsson/snowball/snowball.c
+++ b/board/st-ericsson/snowball/snowball.c
@@ -253,6 +253,10 @@ int board_late_init(void)
 	if ((raise_ab8500_gpio16() < 0))
 		printf("error: cant' raise GPIO16\n");
 
+	/* empty UART RX FIFO */
+	while (tstc())
+		(void) getc();
+
 	return 0;
 }
 
diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c
index 99f833f041..4954475553 100644
--- a/board/ti/beagle/beagle.c
+++ b/board/ti/beagle/beagle.c
@@ -488,7 +488,7 @@ int board_mmc_init(bd_t *bis)
 }
 #endif
 
-#ifdef CONFIG_USB_EHCI
+#if defined(CONFIG_USB_EHCI) && !defined(CONFIG_SPL_BUILD)
 /* Call usb_stop() before starting the kernel */
 void show_boot_progress(int val)
 {
diff --git a/board/xilinx/zynq/Makefile b/board/xilinx/zynq/Makefile
new file mode 100644
index 0000000000..ef4faa125e
--- /dev/null
+++ b/board/xilinx/zynq/Makefile
@@ -0,0 +1,54 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	:= board.o
+
+COBJS	:= $(sort $(COBJS-y))
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
new file mode 100644
index 0000000000..8ed75c3d38
--- /dev/null
+++ b/board/xilinx/zynq/board.c
@@ -0,0 +1,54 @@
+/*
+ * (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	icache_enable();
+
+	return 0;
+}
+
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+	u32 ret = 0;
+
+#if defined(CONFIG_ZYNQ_GEM) && defined(CONFIG_ZYNQ_GEM_BASEADDR0)
+	ret = zynq_gem_initialize(bis, CONFIG_ZYNQ_GEM_BASEADDR0);
+#endif
+
+	return ret;
+}
+#endif
+
+int dram_init(void)
+{
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+	return 0;
+}