Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

* 'master' of git://git.denx.de/u-boot-mpc85xx:
  fsl_lbc: add printout of LCRR and LBCR to local bus regs
  sbc8548: Fix up local bus init to be frequency aware
  sbc8548: enable support for hardware SPD errata workaround
  sbc8548: relocate fixed ddr init code to ddr.c file
  sbc8548: Make enabling SPD RAM configuration work
  sbc8548: Fix LBC SDRAM initialization settings
  sbc8548: enable ability to boot from alternate flash
  sbc8548: relocate 64MB user flash to sane boundary
  Revert "SBC8548: fix address mask to allow 64M flash"
  MPC85xxCDS: Fix missing LCRR_DBYP bits for 66-133MHz LBC
  eXMeritus HWW-1U-1A: Add support for the AT24C128N I2C EEPROM
  eXMeritus HWW-1U-1A: Minor environment variable tweaks

1 files changed, 19 insertions, 5 deletions

diff --git a/board/sbc8548/tlb.c b/board/sbc8548/tlb.c
index bb4c05210c..af927f165b 100644
--- a/board/sbc8548/tlb.c
+++ b/board/sbc8548/tlb.c
@@ -46,12 +46,14 @@ struct fsl_e_tlb_entry tlb_table[] = {
 
 	/*
 	 * TLB 0:	64M	Non-cacheable, guarded
-	 * 0xfc000000	56M	8MB -> 64MB of user flash
+	 * 0xfc000000	56M	unused
 	 * 0xff800000	8M	boot FLASH
+	 *	.... or ....
+	 * 0xfc000000	64M	user flash
+	 *
 	 * Out of reset this entry is only 4K.
 	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x800000,
-		      CONFIG_SYS_ALT_FLASH + 0x800000,
+	SET_TLB_ENTRY(1, 0xfc000000, 0xfc000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 0, BOOKE_PAGESZ_64M, 1),
 
@@ -74,6 +76,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 2, BOOKE_PAGESZ_64M, 1),
 
+#ifdef CONFIG_SYS_LBC_SDRAM_BASE
 	/*
 	 * TLB 3:	64M	Cacheable, non-guarded
 	 * 0xf0000000	64M	LBC SDRAM First half
@@ -90,6 +93,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 		      CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 4, BOOKE_PAGESZ_64M, 1),
+#endif
 
 	/*
 	 * TLB 5:	16M	Cacheable, non-guarded
@@ -102,9 +106,18 @@ struct fsl_e_tlb_entry tlb_table[] = {
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 5, BOOKE_PAGESZ_16M, 1),
 
+#ifndef CONFIG_SYS_ALT_BOOT
+	/*
+	 * TLB 6:	64M	Non-cacheable, guarded
+	 * 0xec000000	64M	64MB user FLASH
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 6, BOOKE_PAGESZ_64M, 1),
+#else
 	/*
 	 * TLB 6:	4M	Non-cacheable, guarded
-	 * 0xfb800000	4M	1st 4MB block of 64MB user FLASH
+	 * 0xef800000	4M	1st 1/2 8MB soldered FLASH
 	 */
 	SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
@@ -112,12 +125,13 @@ struct fsl_e_tlb_entry tlb_table[] = {
 
 	/*
 	 * TLB 7:	4M	Non-cacheable, guarded
-	 * 0xfbc00000	4M	2nd 4MB block of 64MB user FLASH
+	 * 0xefc00000	4M	2nd half 8MB soldered FLASH
 	 */
 	SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x400000,
 		      CONFIG_SYS_ALT_FLASH + 0x400000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 7, BOOKE_PAGESZ_4M, 1),
+#endif
 
 };