diff options
| author | Arun Bharadwaj <arun@gumstix.com> | 2015-04-28 16:55:29 -0700 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2015-05-10 09:54:54 -0400 |
| commit | fe5d488fbef192188bcddb8774154bd5527e468b (patch) | |
| tree | dd9ccaa3641910518c13c84e191b7ed34a98f7d0 /board/overo/spl.c | |
| parent | 88d89668b9d9d4553e630c1c4ce3b0bee725e6ec (diff) | |
| download | blackbird-obmc-uboot-fe5d488fbef192188bcddb8774154bd5527e468b.tar.gz blackbird-obmc-uboot-fe5d488fbef192188bcddb8774154bd5527e468b.zip | |
overo: Split overo.c into spl.c, common.c and overo.c
This separates the SPL-specific code from the u-boot-specific code for
the Overo board following the discussion at
http://lists.denx.de/pipermail/u-boot/2015-April/211622.html
The code is split up into spl.c, overo.c and common.c (which
has the code common to both)
Signed-off-by: Arun Bharadwaj <arun@gumstix.com>
Diffstat (limited to 'board/overo/spl.c')
| -rw-r--r-- | board/overo/spl.c | 60 |
1 files changed, 60 insertions, 0 deletions
diff --git a/board/overo/spl.c b/board/overo/spl.c new file mode 100644 index 0000000000..5af780efc9 --- /dev/null +++ b/board/overo/spl.c @@ -0,0 +1,60 @@ +/* + * Maintainer : Steve Sakoman <steve@sakoman.com> + * + * Derived from Beagle Board, 3430 SDP, and OMAP3EVM code by + * Richard Woodruff <r-woodruff2@ti.com> + * Syed Mohammed Khasim <khasim@ti.com> + * Sunil Kumar <sunilsaini05@gmail.com> + * Shashi Ranjan <shashiranjanmca05@gmail.com> + * + * (C) Copyright 2004-2008 + * Texas Instruments, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <asm/io.h> +#include <asm/arch/mem.h> +#include <asm/arch/sys_proto.h> +#include "overo.h" + +/* + * Routine: get_board_mem_timings + * Description: If we use SPL then there is no x-loader nor config header + * so we have to setup the DDR timings ourself on both banks. + */ +void get_board_mem_timings(struct board_sdrc_timings *timings) +{ + timings->mr = MICRON_V_MR_165; + switch (get_board_revision()) { + case REVISION_0: /* Micron 1286MB/256MB, 1/2 banks of 128MB */ + timings->mcfg = MICRON_V_MCFG_165(256 << 20); + timings->ctrla = MICRON_V_ACTIMA_165; + timings->ctrlb = MICRON_V_ACTIMB_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + break; + case REVISION_1: /* Micron 256MB/512MB, 1/2 banks of 256MB */ + case REVISION_4: + timings->mcfg = MICRON_V_MCFG_200(256 << 20); + timings->ctrla = MICRON_V_ACTIMA_200; + timings->ctrlb = MICRON_V_ACTIMB_200; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + break; + case REVISION_2: /* Hynix 256MB/512MB, 1/2 banks of 256MB */ + timings->mcfg = HYNIX_V_MCFG_200(256 << 20); + timings->ctrla = HYNIX_V_ACTIMA_200; + timings->ctrlb = HYNIX_V_ACTIMB_200; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + break; + case REVISION_3: /* Micron 512MB/1024MB, 1/2 banks of 512MB */ + timings->mcfg = MCFG(512 << 20, 15); + timings->ctrla = MICRON_V_ACTIMA_200; + timings->ctrlb = MICRON_V_ACTIMB_200; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + break; + default: + timings->mcfg = MICRON_V_MCFG_165(128 << 20); + timings->ctrla = MICRON_V_ACTIMA_165; + timings->ctrlb = MICRON_V_ACTIMB_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + } +} |
