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| author | Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | 2008-12-20 19:29:48 +0100 |
|---|---|---|
| committer | Nobuhiro Iwamatsu <iwamatsu@nigauri.org> | 2009-01-16 10:22:26 +0900 |
| commit | e4430779623af500de1cee7892c379f07ef59813 (patch) | |
| tree | 74942b62e37730488c59603d19f045de10c92c1e /board/mpr2 | |
| parent | 85cb052ee41675ca361e6a4c69455dc715c8f2d9 (diff) | |
| download | blackbird-obmc-uboot-e4430779623af500de1cee7892c379f07ef59813.tar.gz blackbird-obmc-uboot-e4430779623af500de1cee7892c379f07ef59813.zip | |
sh: lowlevel_init coding style cleanup
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Diffstat (limited to 'board/mpr2')
| -rw-r--r-- | board/mpr2/lowlevel_init.S | 44 |
1 files changed, 25 insertions, 19 deletions
diff --git a/board/mpr2/lowlevel_init.S b/board/mpr2/lowlevel_init.S index 060957ad06..187b5bbeba 100644 --- a/board/mpr2/lowlevel_init.S +++ b/board/mpr2/lowlevel_init.S @@ -33,17 +33,17 @@ lowlevel_init: /* * Set frequency multipliers and dividers in FRQCR. */ - mov.l WTCSR_A,r1 - mov.l WTCSR_D,r0 - mov.w r0,@r1 + mov.l WTCSR_A, r1 + mov.l WTCSR_D, r0 + mov.w r0, @r1 - mov.l WTCNT_A,r1 - mov.l WTCNT_D,r0 - mov.w r0,@r1 + mov.l WTCNT_A, r1 + mov.l WTCNT_D, r0 + mov.w r0, @r1 - mov.l FRQCR_A,r1 - mov.l FRQCR_D,r0 - mov.w r0,@r1 + mov.l FRQCR_A, r1 + mov.l FRQCR_D, r0 + mov.w r0, @r1 /* * Setup CS0 (Flash). @@ -112,21 +112,27 @@ WTCSR_D: .long 0xA507 /* divide by 4096 */ /* * Spansion S29GL256N11 @ 48 MHz */ -CS0BCR_D: .long 0x12490400 /* 1 idle cycle inserted, normal space, 16 bit */ -CS0WCR_D: .long 0x00000340 /* tSW=0.5ck, 6 wait cycles, NO external wait, tHW=0.5ck */ +/* 1 idle cycle inserted, normal space, 16 bit */ +CS0BCR_D: .long 0x12490400 +/* tSW=0.5ck, 6 wait cycles, NO external wait, tHW=0.5ck */ +CS0WCR_D: .long 0x00000340 /* * Samsung K4S511632B-UL75 @ 48 MHz * Micron MT48LC32M16A2-75 @ 48 MHz */ -CS3BCR_D: .long 0x10004400 /* CS3BCR = 0x10004400, minimum idle cycles, SDRAM, 16 bit */ -CS3WCR_D: .long 0x00000091 /* tRP=1ck, tRCD=1ck, CL=2, tRWL=2ck, tRC=4ck */ -SDCR_D1: .long 0x00000012 /* no refresh, 13 rows, 10 cols, NO bank active mode */ -SDCR_D2: .long 0x00000812 /* refresh */ -RTCSR_D: .long 0xA55A0008 /* 1/4, once */ -RTCNT_D: .long 0xA55A005D /* count 93 */ -RTCOR_D: .long 0xa55a005d /* count 93 */ -SDMR3_D: .long 0x440 /* mode register CL2, burst read and SINGLE WRITE */ +/* CS3BCR = 0x10004400, minimum idle cycles, SDRAM, 16 bit */ +CS3BCR_D: .long 0x10004400 +/* tRP=1ck, tRCD=1ck, CL=2, tRWL=2ck, tRC=4ck */ +CS3WCR_D: .long 0x00000091 +/* no refresh, 13 rows, 10 cols, NO bank active mode */ +SDCR_D1: .long 0x00000012 +SDCR_D2: .long 0x00000812 /* refresh */ +RTCSR_D: .long 0xA55A0008 /* 1/4, once */ +RTCNT_D: .long 0xA55A005D /* count 93 */ +RTCOR_D: .long 0xa55a005d /* count 93 */ +/* mode register CL2, burst read and SINGLE WRITE */ +SDMR3_D: .long 0x440 /* * Registers |
