VCMA9: various cleanups/code style fixes

Signed-off-by: David Müller <d.mueller@elsoft.ch>

5 files changed, 513 insertions, 489 deletions

diff --git a/board/mpl/vcma9/Makefile b/board/mpl/vcma9/Makefile
index 59c25f9606..6228762774 100644
--- a/board/mpl/vcma9/Makefile
+++ b/board/mpl/vcma9/Makefile
@@ -28,8 +28,8 @@ endif
 
 LIB	= $(obj)lib$(BOARD).o
 
-COBJS	:= vcma9.o cmd_vcma9.o
-COBJS	+= ../common/common_util.o
+COBJS	:= ../common/common_util.o
+COBJS	+= $(BOARD).o cmd_$(BOARD).o
 
 SOBJS	:= lowlevel_init.o
 
diff --git a/board/mpl/vcma9/cmd_vcma9.c b/board/mpl/vcma9/cmd_vcma9.c
index 0d5f46e5cd..fa49918ab8 100644
--- a/board/mpl/vcma9/cmd_vcma9.c
+++ b/board/mpl/vcma9/cmd_vcma9.c
@@ -43,15 +43,6 @@ static uchar cs8900_chksum(ushort data)
 
 DECLARE_GLOBAL_DATA_PTR;
 
-extern void print_vcma9_info(void);
-extern int vcma9_cantest(int);
-extern int vcma9_nandtest(void);
-extern int vcma9_nanderase(void);
-extern int vcma9_nandread(ulong);
-extern int vcma9_nandwrite(ulong);
-extern int vcma9_dactest(int);
-extern int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
-
 /* ------------------------------------------------------------------------- */
 
 int do_vcma9(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
@@ -60,7 +51,7 @@ int do_vcma9(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	char cs8900_name[10];
 	if (strcmp(argv[1], "info") == 0)
 	{
-		print_vcma9_info();
+		vcma9_print_info();
 		return 0;
 	}
 #if defined(CONFIG_CS8900)
@@ -133,48 +124,6 @@ int do_vcma9(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 		return 0;
 	}
 #endif
-#if 0
-	if (strcmp(argv[1], "cantest") == 0) {
-		if (argc >= 3)
-			vcma9_cantest(strcmp(argv[2], "s") ? 0 : 1);
-		else
-			vcma9_cantest(0);
-		return 0;
-	}
-	if (strcmp(argv[1], "nandtest") == 0) {
-		vcma9_nandtest();
-		return 0;
-	}
-	if (strcmp(argv[1], "nanderase") == 0) {
-		vcma9_nanderase();
-		return 0;
-	}
-	if (strcmp(argv[1], "nandread") == 0) {
-		ulong offset = 0;
-
-		if (argc >= 3)
-			offset = simple_strtoul(argv[2], NULL, 16);
-
-		vcma9_nandread(offset);
-		return 0;
-	}
-	if (strcmp(argv[1], "nandwrite") == 0) {
-		ulong offset = 0;
-
-		if (argc >= 3)
-			offset = simple_strtoul(argv[2], NULL, 16);
-
-		vcma9_nandwrite(offset);
-		return 0;
-	}
-	if (strcmp(argv[1], "dactest") == 0) {
-		if (argc >= 3)
-			vcma9_dactest(strcmp(argv[2], "s") ? 0 : 1);
-		else
-		vcma9_dactest(0);
-		return 0;
-	}
-#endif
 
 	return (do_mplcommon(cmdtp, flag, argc, argv));
 }
@@ -182,5 +131,6 @@ int do_vcma9(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 U_BOOT_CMD(
 	vcma9, 6, 1, do_vcma9,
 	"VCMA9 specific commands",
-	"flash mem [SrcAddr]\n    - updates U-Boot with image in memory"
+	"flash mem [SrcAddr] - updates U-Boot with image in memory\n"
+	"vcma9 info                - displays board information"
 );
diff --git a/board/mpl/vcma9/lowlevel_init.S b/board/mpl/vcma9/lowlevel_init.S
index 062e868a35..dadaac7299 100644
--- a/board/mpl/vcma9/lowlevel_init.S
+++ b/board/mpl/vcma9/lowlevel_init.S
@@ -4,9 +4,9 @@
  * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
  *                     Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
  *
- * Modified for the Samsung SMDK2410 by
- * (C) Copyright 2002
+ * Modified for MPL VCMA9 by
  * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+ * (C) Copyright 2002, 2003, 2004, 2005
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -32,12 +32,21 @@
 #include <version.h>
 
 
-/* some parameters for the board */
+/* register definitions */
 
+#define PLD_BASE	0x28000000
+#define MISC_REG	0x103
+#define SDRAM_REG	0x106
 #define BWSCON		0x48000000
-#define PLD_BASE	0x2C000000
-#define SDRAM_REG	0x2C000106
+#define CLKBASE		0x4C000000
+#define LOCKTIME	0x0
+#define MPLLCON		0x4
+#define UPLLCON		0x8
+#define GPIOBASE	0x56000000
+#define GSTATUS1	0xB0
+#define FASTCPU		0x02
 
+/* some parameters for the board */
 /* BWSCON */
 #define DW8			(0x0)
 #define DW16			(0x1)
@@ -48,83 +57,160 @@
 /* BANKSIZE */
 #define BURST_EN		(0x1<<7)
 
-#define B1_BWSCON		(DW16)
-#define B2_BWSCON		(DW32)
-#define B3_BWSCON		(DW32)
-#define B4_BWSCON		(DW16 + WAIT + UBLB)
-#define B5_BWSCON		(DW8 + UBLB)
-#define B6_BWSCON		(DW32)
-#define B7_BWSCON		(DW32)
-
-/* BANK0CON */
-#define B0_Tacs			0x0	/*  0clk */
-#define B0_Tcos			0x1	/*  1clk */
-/*#define B0_Tcos		0x0	  0clk */
-#define B0_Tacc			0x7	/*  14clk */
-/*#define B0_Tacc		0x5	  8clk */
-#define B0_Tcoh			0x0	/*  0clk */
-#define B0_Tah			0x0	/*  0clk */
-#define B0_Tacp			0x0     /* page mode is not used */
-#define B0_PMC			0x0	/* page mode disabled */
-
-/* BANK1CON */
-#define B1_Tacs			0x0	/*  0clk */
-#define B1_Tcos			0x1	/*  1clk */
-/*#define B1_Tcos		0x0	  0clk */
-#define B1_Tacc			0x7	/*  14clk */
-/*#define B1_Tacc		0x5	  8clk */
-#define B1_Tcoh			0x0	/*  0clk */
-#define B1_Tah			0x0	/*  0clk */
-#define B1_Tacp			0x0     /* page mode is not used */
-#define B1_PMC			0x0	/* page mode disabled */
+/* BANK0CON 200 */
+#define B0_Tacs_200		0x0	/*  0clk  (or 0x1 1clk) */
+#define B0_Tcos_200		0x1	/*  1clk  (or 0x2 2clk) */
+#define B0_Tacc_200		0x5	/*  8clk  (or 0x6 10clk) */
+#define B0_Tcoh_200		0x0	/*  0clk */
+#define B0_Tcah_200		0x3	/*  4clk  (or0x01 1clk) */
+#define B0_Tacp_200		0x0     /* page mode is not used */
+#define B0_PMC_200		0x0	/* page mode disabled */
+
+/* BANK0CON 250 */
+#define B0_Tacs_250		0x0	/*  0clk  (or 0x1 1clk) */
+#define B0_Tcos_250		0x1	/*  1clk  (or 0x2 2clk) */
+#define B0_Tacc_250		0x5	/*  8clk  (or 0x7 14clk) */
+#define B0_Tcoh_250		0x0	/*  0clk */
+#define B0_Tcah_250		0x3	/*  4clk  (or 0x1 1clk) */
+#define B0_Tacp_250		0x0     /* page mode is not used */
+#define B0_PMC_250		0x0	/* page mode disabled */
+
+/* BANK0CON 266 */
+#define B0_Tacs_266		0x0	/*  0clk  (or 0x1 1clk) */
+#define B0_Tcos_266		0x1	/*  1clk  (or 0x2 2clk) */
+#define B0_Tacc_266		0x6	/*  10clk (or 0x7 14clk) */
+#define B0_Tcoh_266		0x0	/*  0clk */
+#define B0_Tcah_266		0x3	/*  4clk  (or 0x1 1clk) */
+#define B0_Tacp_266		0x0     /* page mode is not used */
+#define B0_PMC_266		0x0	/* page mode disabled */
+
+/* BANK1CON 200 */
+#define B1_Tacs_200		0x0	/*  0clk  (or 0x1 1clk) */
+#define B1_Tcos_200		0x1	/*  1clk  (or 0x2 2clk) */
+#define B1_Tacc_200		0x5	/*  8clk  (or 0x6 10clk) */
+#define B1_Tcoh_200		0x0	/*  0clk */
+#define B1_Tcah_200		0x3	/*  4clk  (or 0x1 1clk) */
+#define B1_Tacp_200		0x0     /* page mode is not used */
+#define B1_PMC_200		0x0	/* page mode disabled */
+
+/* BANK1CON 250 */
+#define B1_Tacs_250		0x0	/*  0clk  (or 0x1 1clk) */
+#define B1_Tcos_250		0x1	/*  1clk  (or 0x2 2clk) */
+#define B1_Tacc_250		0x5	/*  8clk  (or 0x7 14clk) */
+#define B1_Tcoh_250		0x0	/*  0clk */
+#define B1_Tcah_250		0x3	/*  4clk  (or 0x1 1clk) */
+#define B1_Tacp_250		0x0     /* page mode is not used */
+#define B1_PMC_250		0x0	/* page mode disabled */
+
+/* BANK1CON 266 */
+#define B1_Tacs_266		0x0	/*  0clk  (or 0x1 1clk) */
+#define B1_Tcos_266		0x1	/*  1clk  (or 0x2 2clk) */
+#define B1_Tacc_266		0x6	/*  10clk (or 0x7 14clk) */
+#define B1_Tcoh_266		0x0	/*  0clk */
+#define B1_Tcah_266		0x3	/*  4clk  (or 0x1 1clk) */
+#define B1_Tacp_266		0x0     /* page mode is not used */
+#define B1_PMC_266		0x0	/* page mode disabled */
 
+/* BANK2CON 200 + 250 + 266 */
 #define B2_Tacs			0x3	/*  4clk */
 #define B2_Tcos			0x3	/*  4clk */
 #define B2_Tacc			0x7     /* 14clk */
 #define B2_Tcoh			0x3	/*  4clk */
-#define B2_Tah			0x3	/*  4clk */
+#define B2_Tcah			0x3	/*  4clk */
 #define B2_Tacp			0x0	/* page mode is not used */
 #define B2_PMC			0x0     /* page mode disabled */
 
+/* BANK3CON 200 + 250 + 266 */
 #define B3_Tacs			0x3	/*  4clk */
 #define B3_Tcos			0x3	/*  4clk */
 #define B3_Tacc			0x7     /* 14clk */
 #define B3_Tcoh			0x3	/*  4clk */
-#define B3_Tah			0x3	/*  4clk */
+#define B3_Tcah			0x3	/*  4clk */
 #define B3_Tacp			0x0	/* page mode is not used */
 #define B3_PMC			0x0     /* page mode disabled */
 
-#define B4_Tacs			0x3	/*  4clk */
-#define B4_Tcos			0x1	/*  1clk */
-#define B4_Tacc			0x7	/* 14clk */
-#define B4_Tcoh			0x1	/*  1clk */
-#define B4_Tah			0x0	/*  0clk */
-#define B4_Tacp			0x0     /* page mode is not used */
-#define B4_PMC			0x0	/* page mode disabled */
-
-#define B5_Tacs			0x0	/*  0clk */
-#define B5_Tcos			0x3	/*  4clk */
-#define B5_Tacc			0x5	/*  8clk */
-#define B5_Tcoh			0x2	/*  2clk */
-#define B5_Tah			0x1	/*  1clk */
-#define B5_Tacp			0x0     /* page mode is not used */
-#define B5_PMC			0x0	/* page mode disabled */
+/* BANK4CON 200 */
+#define B4_Tacs_200		0x1	/*  1clk */
+#define B4_Tcos_200		0x3	/*  4clk */
+#define B4_Tacc_200		0x7	/* 14clk */
+#define B4_Tcoh_200		0x3	/*  4clk */
+#define B4_Tcah_200		0x2	/*  2clk */
+#define B4_Tacp_200		0x0     /* page mode is not used */
+#define B4_PMC_200		0x0	/* page mode disabled */
+
+/* BANK4CON 250 */
+#define B4_Tacs_250		0x1	/*  1clk */
+#define B4_Tcos_250		0x3	/*  4clk */
+#define B4_Tacc_250		0x7	/* 14clk */
+#define B4_Tcoh_250		0x3	/*  4clk */
+#define B4_Tcah_250		0x2	/*  2clk */
+#define B4_Tacp_250		0x0     /* page mode is not used */
+#define B4_PMC_250		0x0	/* page mode disabled */
+
+/* BANK4CON 266 */
+#define B4_Tacs_266		0x1	/*  1clk */
+#define B4_Tcos_266		0x3	/*  4clk */
+#define B4_Tacc_266		0x7	/* 14clk */
+#define B4_Tcoh_266		0x3	/*  4clk */
+#define B4_Tcah_266		0x2	/*  2clk */
+#define B4_Tacp_266		0x0     /* page mode is not used */
+#define B4_PMC_266		0x0	/* page mode disabled */
+
+/* BANK5CON 200 */
+#define B5_Tacs_200		0x0	/*  0clk */
+#define B5_Tcos_200		0x3	/*  4clk */
+#define B5_Tacc_200		0x4	/*  6clk */
+#define B5_Tcoh_200		0x3	/*  4clk */
+#define B5_Tcah_200		0x1	/*  1clk */
+#define B5_Tacp_200		0x0     /* page mode is not used */
+#define B5_PMC_200		0x0	/* page mode disabled */
+
+/* BANK5CON 250 */
+#define B5_Tacs_250		0x0	/*  0clk */
+#define B5_Tcos_250		0x3	/*  4clk */
+#define B5_Tacc_250		0x5	/*  8clk */
+#define B5_Tcoh_250		0x3	/*  4clk */
+#define B5_Tcah_250		0x1	/*  1clk */
+#define B5_Tacp_250		0x0     /* page mode is not used */
+#define B5_PMC_250		0x0	/* page mode disabled */
+
+/* BANK5CON 266 */
+#define B5_Tacs_266		0x0	/*  0clk */
+#define B5_Tcos_266		0x3	/*  4clk */
+#define B5_Tacc_266		0x5	/*  8clk */
+#define B5_Tcoh_266		0x3	/*  4clk */
+#define B5_Tcah_266		0x1	/*  1clk */
+#define B5_Tacp_266		0x0     /* page mode is not used */
+#define B5_PMC_266		0x0	/* page mode disabled */
 
 #define B6_MT			0x3	/* SDRAM */
-#define B6_Trcd			0x1	/* 3clk */
+#define B6_Trcd_200		0x0	/* 2clk */
+#define B6_Trcd_250		0x1	/* 3clk */
+#define B6_Trcd_266		0x1	/* 3clk */
 #define B6_SCAN			0x2	/* 10bit */
 
 #define B7_MT			0x3	/* SDRAM */
-#define B7_Trcd			0x1	/* 3clk */
+#define B7_Trcd_200		0x0	/* 2clk */
+#define B7_Trcd_250		0x1	/* 3clk */
+#define B7_Trcd_266		0x1	/* 3clk */
 #define B7_SCAN			0x2	/* 10bit */
 
 /* REFRESH parameter */
 #define REFEN			0x1	/* Refresh enable */
 #define TREFMD			0x0	/* CBR(CAS before RAS)/Auto refresh */
-#define Trp			0x0	/* 2clk */
-#define Trc			0x3	/* 7clk */
-#define Tchr			0x2	/* 3clk */
-#define REFCNT			1113	/* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */
+#define Trp_200			0x0	/* 2clk */
+#define Trp_250			0x1	/* 3clk */
+#define Trp_266			0x1	/* 3clk */
+#define Tsrc_200		0x1	/* 5clk */
+#define Tsrc_250		0x2	/* 6clk */
+#define Tsrc_266		0x3	/* 7clk */
+
+/* period=15.6us, HCLK=100Mhz, (2048+1-15.6*100) */
+#define REFCNT_200		489
+/* period=15.6us, HCLK=125Mhz, (2048+1-15.6*125) */
+#define REFCNT_250		99
+/* period=15.6us, HCLK=133Mhz, (2048+1-15.6*133) */
+#define REFCNT_266		0
 /**************************************/
 
 _TEXT_BASE:
@@ -132,81 +218,304 @@ _TEXT_BASE:
 
 .globl lowlevel_init
 lowlevel_init:
+	/* use r0 to relocate DATA read/write to flash rather than memory ! */
+	ldr	r0, _TEXT_BASE
+	ldr	r13, =BWSCON
+
+	/* enable minimal access to PLD */
+	ldr	r1, [r13]			/* load default BWSCON */
+	orr	r1, r1, #(DW8 + UBLB) << 20	/* set necessary CS attrs */
+	str	r1, [r13]			/* set BWSCON */
+	ldr	r1, =0x7FF0			/* select slowest timing */
+	str	r1, [r13, #0x18]		/* set BANKCON5 */
+
+	ldr	r1, =PLD_BASE
+	ldr	r2, =SETUPDATA
+	ldrb	r1, [r1, #MISC_REG]
+	sub	r2, r2, r0
+	tst	r1, #FASTCPU			/* FASTCPU available ? */
+	addeq	r2, r2, #SETUPENTRY_SIZE
+
 	/* memory control configuration */
-	/* make r0 relative the current location so that it */
-	/* reads SMRDATA out of FLASH rather than memory ! */
-	ldr     r0, =CSDATA
-	ldr	r1, _TEXT_BASE
-	sub	r0, r0, r1
-	ldr	r1, =BWSCON	/* Bus Width Status Controller */
-	add     r2, r0, #CSDATA_END-CSDATA
+	/* r2 = pointer into timing table */
+	/* r13 = pointer to MEM controller regs (starting with BWSCON) */
+	add     r3, r2, #CSDATA_OFFSET
+	add     r4, r3, #CSDATAENTRY_SIZE
 0:
-	ldr     r3, [r0], #4
-	str     r3, [r1], #4
-	cmp     r2, r0
+	ldr     r1, [r3], #4
+	str     r1, [r13], #4
+	cmp     r3, r4
 	bne     0b
 
 	/* PLD access is now possible */
-	/* r0 == SDRAMDATA */
-	/* r1 == SDRAM controller regs */
-	ldr	r2, =PLD_BASE
-	ldrb	r3, [r2, #SDRAM_REG-PLD_BASE]
-	mov	r4, #SDRAMDATA1_END-SDRAMDATA
+	/* r3 = SDRAMDATA
+	/* r13 = pointer to MEM controller regs */
+	ldr	r1, =PLD_BASE
+	mov	r4, #SDRAMENTRY_SIZE
+	ldrb	r1, [r1, #SDRAM_REG]
 	/* calculate start and end point */
-	mla	r0, r3, r4, r0
-	add     r2, r0, r4
+	mla	r3, r4, r1, r3
+	add     r4, r3, r4
 0:
-	ldr     r3, [r0], #4
-	str     r3, [r1], #4
-	cmp     r2, r0
+	ldr     r1, [r3], #4
+	str     r1, [r13], #4
+	cmp     r3, r4
 	bne     0b
 
+	/* setup MPLL registers */
+	ldr	r1, =CLKBASE
+	ldr	r4, =0xFFFFFF
+	add	r3, r2, #4		/* r3 points to PLL values */
+	str	r4, [r1, #LOCKTIME]
+	ldmia	r3, {r4,r5}
+	str	r5, [r1, #UPLLCON]	/* writing PLL register */
+					/* !! order seems to be important !! */
+	/* a little delay */
+	ldr	r3, =0x4000
+0:
+	subs	r3, r3, #1
+	bne	0b
+
+	str	r4, [r1, #MPLLCON]	/* writing PLL register */
+					/* !! order seems to be important !! */
+	/* a little delay */
+	ldr	r3, =0x4000
+0:
+	subs	r3, r3, #1
+	bne	0b
+
 	/* everything is fine now */
 	mov	pc, lr
 
 	.ltorg
 /* the literal pools origin */
 
-CSDATA:
-    .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
-    .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))
-    .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))
-    .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))
-    .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))
-    .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))
-    .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))
-CSDATA_END:
-
-SDRAMDATA:
-/* 4Mx8x4 */
-    .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
-    .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
-    .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
-    .word 0x32 + BURST_EN
-    .word 0x30
-    .word 0x30
-SDRAMDATA1_END:
-
-/* 8Mx8x4 (not implemented yet) */
-    .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
-    .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
-    .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
-    .word 0x32 + BURST_EN
-    .word 0x30
-    .word 0x30
-
-/* 2Mx8x4 (not implemented yet) */
-    .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
-    .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
-    .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
-    .word 0x32 + BURST_EN
-    .word 0x30
-    .word 0x30
-
-/* 4Mx8x2 (not implemented yet) */
-    .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
-    .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
-    .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
-    .word 0x32 + BURST_EN
-    .word 0x30
-    .word 0x30
+#define MK_BWSCON(bws1, bws2, bws3, bws4, bws5, bws6, bws7) \
+	((bws1) << 4) + \
+	((bws2) << 8) + \
+	((bws3) << 12) + \
+	((bws4) << 16) + \
+	((bws5) << 20) + \
+	((bws6) << 24) + \
+	((bws7) << 28)
+
+#define MK_BANKCON(tacs, tcos, tacc, tcoh, tcah, tacp, pmc) \
+	((tacs) << 13) + \
+	((tcos) << 11) + \
+	((tacc) << 8) + \
+	((tcoh) << 6) + \
+	((tcah) << 4) + \
+	((tacp) << 2) + \
+	(pmc)
+
+#define MK_BANKCON_SDRAM(trcd, scan) \
+	((0x03) << 15) + \
+	((trcd) << 2) + \
+	(scan)
+
+#define MK_SDRAM_REFRESH(enable, trefmd, trp, tsrc, cnt) \
+	((enable) << 23) + \
+	((trefmd) << 22) + \
+	((trp) << 20) + \
+	((tsrc) << 18) + \
+	(cnt)
+
+SETUPDATA:
+	.word 0x32410002
+	/* PLL values (MDIV, PDIV, SDIV) for 250 MHz */
+	.word (0x75 << 12) + (0x01 << 4) + (0x01 << 0)
+	/* PLL values for USB clock */
+	.word (0x48 << 12) + (0x03 << 4) + (0x02 << 0)
+
+	/* timing for 250 MHz*/
+0:
+	.equiv CSDATA_OFFSET, (. - SETUPDATA)
+	.word MK_BWSCON(DW16, \
+			DW32, \
+			DW32, \
+			DW16 + WAIT + UBLB, \
+			DW8 + UBLB, \
+			DW32, \
+			DW32)
+
+	.word MK_BANKCON(B0_Tacs_250, \
+			 B0_Tcos_250, \
+			 B0_Tacc_250, \
+			 B0_Tcoh_250, \
+			 B0_Tcah_250, \
+			 B0_Tacp_250, \
+			 B0_PMC_250)
+
+	.word MK_BANKCON(B1_Tacs_250, \
+			 B1_Tcos_250, \
+			 B1_Tacc_250, \
+			 B1_Tcoh_250, \
+			 B1_Tcah_250, \
+			 B1_Tacp_250, \
+			 B1_PMC_250)
+
+	.word MK_BANKCON(B2_Tacs, \
+			 B2_Tcos, \
+			 B2_Tacc, \
+			 B2_Tcoh, \
+			 B2_Tcah, \
+			 B2_Tacp, \
+			 B2_PMC)
+
+	.word MK_BANKCON(B3_Tacs, \
+			 B3_Tcos, \
+			 B3_Tacc, \
+			 B3_Tcoh, \
+			 B3_Tcah, \
+			 B3_Tacp, \
+			 B3_PMC)
+
+	.word MK_BANKCON(B4_Tacs_250, \
+			 B4_Tcos_250, \
+			 B4_Tacc_250, \
+			 B4_Tcoh_250, \
+			 B4_Tcah_250, \
+			 B4_Tacp_250, \
+			 B4_PMC_250)
+
+	.word MK_BANKCON(B5_Tacs_250, \
+			 B5_Tcos_250, \
+			 B5_Tacc_250, \
+			 B5_Tcoh_250, \
+			 B5_Tcah_250, \
+			 B5_Tacp_250, \
+			 B5_PMC_250)
+
+	.equiv CSDATAENTRY_SIZE, (. - 0b)
+	/* 4Mx8x4 */
+0:
+	.word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN)
+	.word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN)
+	.word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250)
+	.word 0x32 + BURST_EN
+	.word 0x30
+	.word 0x30
+	.equiv SDRAMENTRY_SIZE, (. - 0b)
+
+	/* 8Mx8x4 */
+	.word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN)
+	.word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN)
+	.word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250)
+	.word 0x32 + BURST_EN
+	.word 0x30
+	.word 0x30
+
+	/* 2Mx8x4 */
+	.word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN)
+	.word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN)
+	.word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250)
+	.word 0x32 + BURST_EN
+	.word 0x30
+	.word 0x30
+
+	/* 4Mx8x2 */
+	.word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN)
+	.word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN)
+	.word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250)
+	.word 0x32 + BURST_EN
+	.word 0x30
+	.word 0x30
+
+	.equiv SETUPENTRY_SIZE, (. - SETUPDATA)
+
+	.word 0x32410000
+	/* PLL values (MDIV, PDIV, SDIV) for 200 MHz (Fout = 202.8MHz) */
+	.word (0xA1 << 12) + (0x03 << 4) + (0x01 << 0)
+	/* PLL values for USB clock */
+	.word (0x48 << 12) + (0x03 << 4) + (0x02 << 0)
+
+	/* timing for 200 MHz and default*/
+	.word MK_BWSCON(DW16, \
+			DW32, \
+			DW32, \
+			DW16 + WAIT + UBLB, \
+			DW8 + UBLB, \
+			DW32, \
+			DW32)
+
+	.word MK_BANKCON(B0_Tacs_200, \
+			 B0_Tcos_200, \
+			 B0_Tacc_200, \
+			 B0_Tcoh_200, \
+			 B0_Tcah_200, \
+			 B0_Tacp_200, \
+			 B0_PMC_200)
+
+	.word MK_BANKCON(B1_Tacs_200, \
+			 B1_Tcos_200, \
+			 B1_Tacc_200, \
+			 B1_Tcoh_200, \
+			 B1_Tcah_200, \
+			 B1_Tacp_200, \
+			 B1_PMC_200)
+
+	.word MK_BANKCON(B2_Tacs, \
+			 B2_Tcos, \
+			 B2_Tacc, \
+			 B2_Tcoh, \
+			 B2_Tcah, \
+			 B2_Tacp, \
+			 B2_PMC)
+
+	.word MK_BANKCON(B3_Tacs, \
+			 B3_Tcos, \
+			 B3_Tacc, \
+			 B3_Tcoh, \
+			 B3_Tcah, \
+			 B3_Tacp, \
+			 B3_PMC)
+
+	.word MK_BANKCON(B4_Tacs_200, \
+			 B4_Tcos_200, \
+			 B4_Tacc_200, \
+			 B4_Tcoh_200, \
+			 B4_Tcah_200, \
+			 B4_Tacp_200, \
+			 B4_PMC_200)
+
+	.word MK_BANKCON(B5_Tacs_200, \
+			 B5_Tcos_200, \
+			 B5_Tacc_200, \
+			 B5_Tcoh_200, \
+			 B5_Tcah_200, \
+			 B5_Tacp_200, \
+			 B5_PMC_200)
+
+	/* 4Mx8x4 */
+	.word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN)
+	.word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN)
+	.word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200)
+	.word 0x32 + BURST_EN
+	.word 0x30
+	.word 0x30
+
+	/* 8Mx8x4 */
+	.word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN)
+	.word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN)
+	.word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200)
+	.word 0x32 + BURST_EN
+	.word 0x30
+	.word 0x30
+
+	/* 2Mx8x4 */
+	.word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN)
+	.word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN)
+	.word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200)
+	.word 0x32 + BURST_EN
+	.word 0x30
+	.word 0x30
+
+	/* 4Mx8x2 */
+	.word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN)
+	.word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN)
+	.word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200)
+	.word 0x32 + BURST_EN
+	.word 0x30
+	.word 0x30
+
+	.equiv SETUPDATA_SIZE, (. - SETUPDATA)
diff --git a/board/mpl/vcma9/vcma9.c b/board/mpl/vcma9/vcma9.c
index 171a1288fc..e63625bf93 100644
--- a/board/mpl/vcma9/vcma9.c
+++ b/board/mpl/vcma9/vcma9.c
@@ -3,7 +3,7 @@
  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  * Marius Groeger <mgroeger@sysgo.de>
  *
- * (C) Copyright 2002
+ * (C) Copyright 2002, 2010
  * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
  *
  * See file CREDITS for list of people who contributed to this
@@ -27,100 +27,51 @@
 
 #include <common.h>
 #include <netdev.h>
-#include <asm/arch/s3c24x0_cpu.h>
-#include <stdio_dev.h>
 #include <i2c.h>
+#include <asm/io.h>
+#include <asm/arch/s3c24x0_cpu.h>
 
 #include "vcma9.h"
 #include "../common/common_util.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define FCLK_SPEED 1
-
-#if FCLK_SPEED==0		/* Fout = 203MHz, Fin = 12MHz for Audio */
-#define M_MDIV	0xC3
-#define M_PDIV	0x4
-#define M_SDIV	0x1
-#elif FCLK_SPEED==1		/* Fout = 202.8MHz */
-#define M_MDIV	0xA1
-#define M_PDIV	0x3
-#define M_SDIV	0x1
-#endif
-
-#define USB_CLOCK 1
-
-#if USB_CLOCK==0
-#define U_M_MDIV	0xA1
-#define U_M_PDIV	0x3
-#define U_M_SDIV	0x1
-#elif USB_CLOCK==1
-#define U_M_MDIV	0x48
-#define U_M_PDIV	0x3
-#define U_M_SDIV	0x2
-#endif
-
-static inline void delay(unsigned long loops)
-{
-	__asm__ volatile ("1:\n"
-	  "subs %0, %1, #1\n"
-	  "bne 1b":"=r" (loops):"0" (loops));
-}
-
 /*
  * Miscellaneous platform dependent initialisations
  */
 
-int board_init(void)
+int board_early_init_f(void)
 {
-	struct s3c24x0_clock_power * const clk_power =
-					s3c24x0_get_base_clock_power();
 	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
 
-	/* to reduce PLL lock time, adjust the LOCKTIME register */
-	clk_power->locktime = 0xFFFFFF;
-
-	/* configure MPLL */
-	clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
-
-	/* some delay between MPLL and UPLL */
-	delay (4000);
-
-	/* configure UPLL */
-	clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
-
-	/* some delay between MPLL and UPLL */
-	delay (8000);
-
 	/* set up the I/O ports */
-	gpio->gpacon = 0x007FFFFF;
-	gpio->gpbcon = 0x002AAAAA;
-	gpio->gpbup = 0x000002BF;
-	gpio->gpccon = 0xAAAAAAAA;
-	gpio->gpcup = 0x0000FFFF;
-	gpio->gpdcon = 0xAAAAAAAA;
-	gpio->gpdup = 0x0000FFFF;
-	gpio->gpecon = 0xAAAAAAAA;
-	gpio->gpeup = 0x000037F7;
-	gpio->gpfcon = 0x00000000;
-	gpio->gpfup = 0x00000000;
-	gpio->gpgcon = 0xFFEAFF5A;
-	gpio->gpgup = 0x0000F0DC;
-	gpio->gphcon = 0x0028AAAA;
-	gpio->gphup = 0x00000656;
-
-	/* setup correct IRQ modes for NIC */
-	/* rising edge mode */
-	gpio->extint2 = (gpio->extint2 & ~(7<<8)) | (4<<8);
-
-	/* select USB port 2 to be host or device (fix to host for now) */
-	gpio->misccr |= 0x08;
-
-	/* init serial */
-	gd->baudrate = CONFIG_BAUDRATE;
-	gd->have_console = 1;
-	serial_init();
+	writel(0x007FFFFF, &gpio->gpacon);
+	writel(0x002AAAAA, &gpio->gpbcon);
+	writel(0x000002BF, &gpio->gpbup);
+	writel(0xAAAAAAAA, &gpio->gpccon);
+	writel(0x0000FFFF, &gpio->gpcup);
+	writel(0xAAAAAAAA, &gpio->gpdcon);
+	writel(0x0000FFFF, &gpio->gpdup);
+	writel(0xAAAAAAAA, &gpio->gpecon);
+	writel(0x000037F7, &gpio->gpeup);
+	writel(0x00000000, &gpio->gpfcon);
+	writel(0x00000000, &gpio->gpfup);
+	writel(0xFFEAFF5A, &gpio->gpgcon);
+	writel(0x0000F0DC, &gpio->gpgup);
+	writel(0x0028AAAA, &gpio->gphcon);
+	writel(0x00000656, &gpio->gphup);
+
+	/* setup correct IRQ modes for NIC (rising edge mode) */
+	writel((readl(&gpio->extint2) & ~(7<<8)) | (4<<8),  &gpio->extint2);
+
+	/* select USB port 2 to be host or device (setup as host for now) */
+	writel(readl(&gpio->misccr) | 0x08, &gpio->misccr);
 
+	return 0;
+}
+
+int board_init(void)
+{
 	/* arch number of VCMA9-Board */
 	gd->bd->bi_arch_number = MACH_TYPE_MPL_VCMA9;
 
@@ -134,113 +85,32 @@ int board_init(void)
 }
 
 /*
- * NAND flash initialization.
- */
-#if defined(CONFIG_CMD_NAND)
-extern ulong
-nand_probe(ulong physadr);
-
-
-static inline void NF_Reset(void)
-{
-    int i;
-
-    NF_SetCE(NFCE_LOW);
-    NF_Cmd(0xFF);		/* reset command */
-    for(i = 0; i < 10; i++);	/* tWB = 100ns. */
-    NF_WaitRB();		/* wait 200~500us; */
-    NF_SetCE(NFCE_HIGH);
-}
-
-
-static inline void NF_Init(void)
-{
-#if 0 /* a little bit too optimistic */
-#define TACLS   0
-#define TWRPH0  3
-#define TWRPH1  0
-#else
-#define TACLS   0
-#define TWRPH0  4
-#define TWRPH1  2
-#endif
-
-    NF_Conf((1<<15)|(0<<14)|(0<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0));
-    /*nand->NFCONF = (1<<15)|(1<<14)|(1<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0); */
-    /* 1  1    1     1,   1      xxx,  r xxx,   r xxx */
-    /* En 512B 4step ECCR nFCE=H tACLS   tWRPH0   tWRPH1 */
-
-    NF_Reset();
-}
-
-void
-nand_init(void)
-{
-	struct s3c2410_nand * const nand = s3c2410_get_base_nand();
-
-	NF_Init();
-#ifdef DEBUG
-	printf("NAND flash probing at 0x%.8lX\n", (ulong)nand);
-#endif
-	printf ("%4lu MB\n", nand_probe((ulong)nand) >> 20);
-}
-#endif
-
-/*
  * Get some Board/PLD Info
  */
 
-static u8 Get_PLD_ID(void)
+static u8 get_pld_reg(enum vcma9_pld_regs reg)
 {
-	VCMA9_PLD * const pld = VCMA9_get_base_PLD();
-
-	return(pld->ID);
+	return readb(VCMA9_PLD_BASE + reg);
 }
 
-static u8 Get_PLD_BOARD(void)
+static u8 get_pld_version(void)
 {
-	VCMA9_PLD * const pld = VCMA9_get_base_PLD();
-
-	return(pld->BOARD);
+	return (get_pld_reg(VCMA9_PLD_ID) >> 4) & 0x0F;
 }
 
-static u8 Get_PLD_SDRAM(void)
+static u8 get_pld_revision(void)
 {
-	VCMA9_PLD * const pld = VCMA9_get_base_PLD();
-
-	return(pld->SDRAM);
+	return get_pld_reg(VCMA9_PLD_ID) & 0x0F;
 }
 
-static u8 Get_PLD_Version(void)
+static uchar get_board_pcb(void)
 {
-	return((Get_PLD_ID() >> 4) & 0x0F);
+	return ((get_pld_reg(VCMA9_PLD_BOARD) >> 4) & 0x03) + 'A';
 }
 
-static u8 Get_PLD_Revision(void)
+static u8 get_nr_chips(void)
 {
-	return(Get_PLD_ID() & 0x0F);
-}
-
-#if 0	/* not used */
-static int Get_Board_Config(void)
-{
-	u8 config = Get_PLD_BOARD() & 0x03;
-
-	if (config == 3)
-	    return 1;
-	else
-	    return 0;
-}
-#endif
-
-static uchar Get_Board_PCB(void)
-{
-	return(((Get_PLD_BOARD() >> 4) & 0x03) + 'A');
-}
-
-static u8 Get_SDRAM_ChipNr(void)
-{
-	switch ((Get_PLD_SDRAM() >> 4) & 0x0F) {
+	switch ((get_pld_reg(VCMA9_PLD_SDRAM) >> 4) & 0x0F) {
 		case 0: return 4;
 		case 1: return 1;
 		case 2: return 2;
@@ -248,9 +118,9 @@ static u8 Get_SDRAM_ChipNr(void)
 	}
 }
 
-static ulong Get_SDRAM_ChipSize(void)
+static ulong get_chip_size(void)
 {
-	switch (Get_PLD_SDRAM() & 0x0F) {
+	switch (get_pld_reg(VCMA9_PLD_SDRAM) & 0x0F) {
 		case 0: return 16 * (1024*1024);
 		case 1: return 32 * (1024*1024);
 		case 2: return  8 * (1024*1024);
@@ -258,9 +128,10 @@ static ulong Get_SDRAM_ChipSize(void)
 		default: return 0;
 	}
 }
-static const char * Get_SDRAM_ChipGeom(void)
+
+static const char *get_chip_geom(void)
 {
-	switch (Get_PLD_SDRAM() & 0x0F) {
+	switch (get_pld_reg(VCMA9_PLD_SDRAM) & 0x0F) {
 		case 0: return "4Mx8x4";
 		case 1: return "8Mx8x4";
 		case 2: return "2Mx8x4";
@@ -269,23 +140,21 @@ static const char * Get_SDRAM_ChipGeom(void)
 	}
 }
 
-static void Show_VCMA9_Info(char *board_name, char *serial)
+static void vcma9_show_info(char *board_name, char *serial)
 {
 	printf("Board: %s SN: %s  PCB Rev: %c PLD(%d,%d)\n",
-		board_name, serial, Get_Board_PCB(), Get_PLD_Version(), Get_PLD_Revision());
-	printf("SDRAM: %d chips %s\n", Get_SDRAM_ChipNr(), Get_SDRAM_ChipGeom());
+		board_name, serial,
+		get_board_pcb(), get_pld_version(), get_pld_revision());
+	printf("SDRAM: %d chips %s\n", get_nr_chips(), get_chip_geom());
 }
 
 int dram_init(void)
 {
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = Get_SDRAM_ChipSize() * Get_SDRAM_ChipNr();
-
+	/* dram_init must store complete ramsize in gd->ram_size */
+	gd->ram_size = get_chip_size() * get_nr_chips();
 	return 0;
 }
 
-/* ------------------------------------------------------------------------- */
-
 /*
  * Check Board Identity:
  */
@@ -303,50 +172,35 @@ int checkboard(void)
 			puts ("### No HW ID - assuming VCMA9");
 		} else {
 			b->serial_name[5] = 0;
-			Show_VCMA9_Info(b->serial_name, &b->serial_name[6]);
+			vcma9_show_info(b->serial_name, &b->serial_name[6]);
 		}
 	} else {
 		s[5] = 0;
-		Show_VCMA9_Info(s, &s[6]);
+		vcma9_show_info(s, &s[6]);
 	}
-	/*printf("\n");*/
-	return(0);
-}
 
-
-int last_stage_init(void)
-{
-	checkboard();
-	stdio_print_current_devices();
-	check_env();
 	return 0;
 }
 
-/***************************************************************************
- * some helping routines
- */
-#if !CONFIG_USB_KEYBOARD
-int overwrite_console(void)
+int board_late_init(void)
 {
-	/* return TRUE if console should be overwritten */
+	/*
+	 * check if environment is healthy, otherwise restore values
+	 * from shadow copy
+	 */
+	check_env();
 	return 0;
 }
-#endif
 
-/************************************************************************
-* Print VCMA9 Info
-************************************************************************/
-void print_vcma9_info(void)
+void vcma9_print_info(void)
 {
-	char s[50];
-	int i;
+	char *s = getenv("serial#");
 
-	if ((i = getenv_f("serial#", s, 32)) < 0) {
+	if (!s) {
 		puts ("### No HW ID - assuming VCMA9");
-		printf("i %d", i*24);
 	} else {
 		s[5] = 0;
-		Show_VCMA9_Info(s, &s[6]);
+		vcma9_show_info(s, &s[6]);
 	}
 }
 
diff --git a/board/mpl/vcma9/vcma9.h b/board/mpl/vcma9/vcma9.h
index 94fd2faf3b..7c44194794 100644
--- a/board/mpl/vcma9/vcma9.h
+++ b/board/mpl/vcma9/vcma9.h
@@ -27,108 +27,19 @@
 
 #include <asm/arch/s3c24x0_cpu.h>
 
-extern int  mem_test(unsigned long start, unsigned long ramsize,int mode);
-
-void print_vcma9_info(void);
-
-#if defined(CONFIG_CMD_NAND)
-typedef enum {
-	NFCE_LOW,
-	NFCE_HIGH
-} NFCE_STATE;
-
-static inline void NF_Conf(u16 conf)
-{
-	struct s3c2410_nand * const nand = s3c2410_get_base_nand();
-
-	nand->NFCONF = conf;
-}
-
-static inline void NF_Cmd(u8 cmd)
-{
-	struct s3c2410_nand * const nand = s3c2410_get_base_nand();
-
-	nand->NFCMD = cmd;
-}
-
-static inline void NF_CmdW(u8 cmd)
-{
-	NF_Cmd(cmd);
-	udelay(1);
-}
-
-static inline void NF_Addr(u8 addr)
-{
-	struct s3c2410_nand * const nand = s3c2410_get_base_nand();
-
-	nand->NFADDR = addr;
-}
-
-static inline void NF_SetCE(NFCE_STATE s)
-{
-	struct s3c2410_nand * const nand = s3c2410_get_base_nand();
-
-	switch (s) {
-		case NFCE_LOW:
-			nand->NFCONF &= ~(1<<11);
-			break;
-
-		case NFCE_HIGH:
-			nand->NFCONF |= (1<<11);
-			break;
-	}
-}
-
-static inline void NF_WaitRB(void)
-{
-	struct s3c2410_nand * const nand = s3c2410_get_base_nand();
-
-	while (!(nand->NFSTAT & (1<<0)));
-}
-
-static inline void NF_Write(u8 data)
-{
-	struct s3c2410_nand * const nand = s3c2410_get_base_nand();
-
-	nand->NFDATA = data;
-}
-
-static inline u8 NF_Read(void)
-{
-	struct s3c2410_nand * const nand = s3c2410_get_base_nand();
-
-	return(nand->NFDATA);
-}
-
-static inline void NF_Init_ECC(void)
-{
-	struct s3c2410_nand * const nand = s3c2410_get_base_nand();
-
-	nand->NFCONF |= (1<<12);
-}
-
-static inline u32 NF_Read_ECC(void)
-{
-	struct s3c2410_nand * const nand = s3c2410_get_base_nand();
-
-	return(nand->NFECC);
-}
-
-#endif
-
-/* VCMA9 PLD regsiters */
-typedef struct {
-	u8	ID;
-	u8	NIC;
-	u8	CAN;
-	u8	MISC;
-	u8	GPCD;
-	u8	BOARD;
-	u8	SDRAM;
-} /*__attribute__((__packed__))*/ VCMA9_PLD;
-
-#define VCMA9_PLD_BASE	0x2C000100
-static inline VCMA9_PLD *VCMA9_get_base_PLD(void)
-{
-	return (VCMA9_PLD * const)VCMA9_PLD_BASE;
-}
+extern void vcma9_print_info(void);
+extern int do_mplcommon(cmd_tbl_t *cmdtp, int flag,
+			int argc, char *const argv[]);
+
+/* VCMA9 PLD registers */
+enum vcma9_pld_regs {
+	VCMA9_PLD_ID,
+	VCMA9_PLD_NIC,
+	VCMA9_PLD_CAN,
+	VCMA9_PLD_MISC,
+	VCMA9_PLD_GPCD,
+	VCMA9_PLD_BOARD,
+	VCMA9_PLD_SDRAM
+};
+
+#define VCMA9_PLD_BASE	(0x2C000100)