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authorDirk Eibach <dirk.eibach@gdsys.cc>2014-07-03 09:28:17 +0200
committerTom Rini <trini@ti.com>2014-07-07 19:47:18 -0400
commitedfe9fea7ce0a1cfde67712a67f88b601eb7803f (patch)
tree7b53af54931d4de8d678153151d961acc8513cba /board/gdsys/common/dp501.c
parent35ecf752305aadd2b048c5942f56bec813d12ad4 (diff)
downloadblackbird-obmc-uboot-edfe9fea7ce0a1cfde67712a67f88b601eb7803f.tar.gz
blackbird-obmc-uboot-edfe9fea7ce0a1cfde67712a67f88b601eb7803f.zip
board: iocon: Support DisplayPort hardware
There is a new iocon hardware flavor, supporting DisplayPort finally. Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Diffstat (limited to 'board/gdsys/common/dp501.c')
-rw-r--r--board/gdsys/common/dp501.c33
1 files changed, 23 insertions, 10 deletions
diff --git a/board/gdsys/common/dp501.c b/board/gdsys/common/dp501.c
index 52f3ea167f..e00e58997b 100644
--- a/board/gdsys/common/dp501.c
+++ b/board/gdsys/common/dp501.c
@@ -60,8 +60,31 @@ void dp501_powerup(u8 addr)
i2c_reg_write(addr, 0x71, 0x20); /* Enable Aux burst write */
dp501_setbits(addr, 0x78, 0x30); /* Disable HPD2 IRQ */
dp501_clrbits(addr, 0x2f, 0x40); /* Link FIFO reset selection */
+
+#ifdef CONFIG_SYS_DP501_VCAPCTRL0
+ i2c_reg_write(addr, 0x24, CONFIG_SYS_DP501_VCAPCTRL0);
+#else
i2c_reg_write(addr, 0x24, 0xc0); /* SDR mode 0, ext. H/VSYNC */
+#endif
+
+#ifdef CONFIG_SYS_DP501_DIFFERENTIAL
+ i2c_reg_write(addr + 2, 0x24, 0x10); /* clock input differential */
+ i2c_reg_write(addr + 2, 0x25, 0x04);
+ i2c_reg_write(addr + 2, 0x26, 0x10);
+#else
i2c_reg_write(addr + 2, 0x24, 0x02); /* clock input single ended */
+#endif
+
+ i2c_reg_write(addr + 2, 0x00, 0x18); /* driving strength */
+ i2c_reg_write(addr + 2, 0x03, 0x06); /* driving strength */
+ i2c_reg_write(addr, 0x2c, 0x00); /* configure N value */
+ i2c_reg_write(addr, 0x2d, 0x00); /* configure N value */
+ i2c_reg_write(addr, 0x2e, 0x0c); /* configure N value */
+ i2c_reg_write(addr, 0x76, 0xff); /* clear all interrupt */
+ dp501_setbits(addr, 0x78, 0x03); /* clear all interrupt */
+ i2c_reg_write(addr, 0x75, 0xf8); /* aux channel reset */
+ i2c_reg_write(addr, 0x75, 0x00); /* clear aux channel reset */
+ i2c_reg_write(addr, 0x87, 0x70); /* set retry counter as 7 */
if (dp501_detect_cable_adapter(addr)) {
printf("DVI/HDMI cable adapter detected\n");
@@ -69,16 +92,6 @@ void dp501_powerup(u8 addr)
dp501_clrbits(addr, 0x00, 0x08); /* DVI/HDMI HDCP operation */
} else {
printf("no DVI/HDMI cable adapter detected\n");
- i2c_reg_write(addr + 2, 0x00, 0x18); /* driving strength */
- i2c_reg_write(addr + 2, 0x03, 0x06); /* driving strength */
- i2c_reg_write(addr, 0x2c, 0x00); /* configure N value */
- i2c_reg_write(addr, 0x2d, 0x00); /* configure N value */
- i2c_reg_write(addr, 0x2e, 0x0c); /* configure N value */
- i2c_reg_write(addr, 0x76, 0xff); /* clear all interrupt */
- dp501_setbits(addr, 0x78, 0x03); /* clear all interrupt */
- i2c_reg_write(addr, 0x75, 0xf8); /* aux channel reset */
- i2c_reg_write(addr, 0x75, 0x00); /* clear aux channel reset */
- i2c_reg_write(addr, 0x87, 0x70); /* set retry counter as 7 */
dp501_setbits(addr, 0x00, 0x08); /* for DP HDCP operation */
dp501_link_training(addr);
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