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| author | Shaohui Xie <Shaohui.Xie@freescale.com> | 2014-04-22 15:10:44 +0800 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2014-04-22 17:58:53 -0700 |
| commit | b6036993ebf12d360692a7df227537277afe3a1f (patch) | |
| tree | b063445f4cd8225d787bb5a3baa45d36243ada1f /board/freescale/t4qds/ddr.c | |
| parent | cb753850e8af5a224d7c08b4fd1d258082d3bbd5 (diff) | |
| download | blackbird-obmc-uboot-b6036993ebf12d360692a7df227537277afe3a1f.tar.gz blackbird-obmc-uboot-b6036993ebf12d360692a7df227537277afe3a1f.zip | |
powerpc/T4QDS: add two stage boot of nand/sd
Add support of 2 stage NAND/SD boot loader using SPL framework.
PBL initialise the internal SRAM and copy SPL, this further
initialise DDR using SPD and environment and copy u-boot from
NAND/SD to DDR, finally SPL transfer control to u-boot.
NOR uses CS1 instead of CS2 when NAND boot, fix it.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'board/freescale/t4qds/ddr.c')
| -rw-r--r-- | board/freescale/t4qds/ddr.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/board/freescale/t4qds/ddr.c b/board/freescale/t4qds/ddr.c index 7586cc3c4b..7abd38def1 100644 --- a/board/freescale/t4qds/ddr.c +++ b/board/freescale/t4qds/ddr.c @@ -117,11 +117,15 @@ phys_size_t initdram(int board_type) puts("Initializing....using SPD\n"); +#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) dram_size = fsl_ddr_sdram(); dram_size = setup_ddr_tlbs(dram_size / 0x100000); dram_size *= 0x100000; - puts(" DDR: "); +#else + /* DDR has been initialised by first stage boot loader */ + dram_size = fsl_ddr_sdram_size(); +#endif return dram_size; } |
