powerpc/T4240EMU: Add T4240EMU target

Add emulator support for T4240. Emulator has limited peripherals and
interfaces. Difference between emulator and T4240QDS includes:
	ECC for DDR is disabled due the procedure to load images
	No board FPGA (QIXIS)
	NOR flash has 32-bit port for higher loading speed
	IFC and I2C timing don't really matter, so set them fast
	No ethernet

Signed-off-by: York Sun <yorksun@freescale.com>

1 files changed, 1 insertions, 72 deletions

diff --git a/board/freescale/t4qds/ddr.c b/board/freescale/t4qds/ddr.c
index 058d62511f..26ac2a54d2 100644
--- a/board/freescale/t4qds/ddr.c
+++ b/board/freescale/t4qds/ddr.c
@@ -13,81 +13,10 @@
 #include <asm/fsl_ddr_sdram.h>
 #include <asm/fsl_ddr_dimm_params.h>
 #include <asm/fsl_law.h>
+#include "ddr.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
-struct board_specific_parameters {
-	u32 n_ranks;
-	u32 datarate_mhz_high;
-	u32 rank_gb;
-	u32 clk_adjust;
-	u32 wrlvl_start;
-	u32 wrlvl_ctl_2;
-	u32 wrlvl_ctl_3;
-	u32 cpo;
-	u32 write_data_delay;
-	u32 force_2T;
-};
-
-/*
- * This table contains all valid speeds we want to override with board
- * specific parameters. datarate_mhz_high values need to be in ascending order
- * for each n_ranks group.
- */
-static const struct board_specific_parameters udimm0[] = {
-	/*
-	 * memory controller 0
-	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl | cpo  |wrdata|2T
-	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |      |delay |
-	 */
-	{2,  1350, 4, 4,     8, 0x0809090b, 0x0c0c0d0a,   0xff,    2,  0},
-	{2,  1350, 0, 5,     7, 0x0709090b, 0x0c0c0d09,   0xff,    2,  0},
-	{2,  1666, 4, 4,     8, 0x080a0a0d, 0x0d10100b,   0xff,    2,  0},
-	{2,  1666, 0, 5,     7, 0x080a0a0c, 0x0d0d0e0a,   0xff,    2,  0},
-	{2,  1900, 0, 4,     8, 0x090a0b0e, 0x0f11120c,   0xff,    2,  0},
-	{2,  2140, 0, 4,     8, 0x090a0b0e, 0x0f11120c,   0xff,    2,  0},
-	{1,  1350, 0, 5,     8, 0x0809090b, 0x0c0c0d0a,   0xff,    2,  0},
-	{1,  1700, 0, 5,     8, 0x080a0a0c, 0x0c0d0e0a,   0xff,    2,  0},
-	{1,  1900, 0, 4,     8, 0x080a0a0c, 0x0e0e0f0a,   0xff,    2,  0},
-	{1,  2140, 0, 4,     8, 0x090a0b0c, 0x0e0f100b,   0xff,    2,  0},
-	{}
-};
-
-/*
- * The three slots have slightly different timing. The center values are good
- * for all slots. We use identical speed tables for them. In future use, if
- * DIMMs require separated tables, make more entries as needed.
- */
-static const struct board_specific_parameters *udimms[] = {
-	udimm0,
-};
-
-static const struct board_specific_parameters rdimm0[] = {
-	/*
-	 * memory controller 0
-	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl | cpo  |wrdata|2T
-	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |      |delay |
-	 */
-	{4,  1350, 0, 5,     9, 0x08070605, 0x07080805,   0xff,    2,  0},
-	{4,  1666, 0, 5,     8, 0x08070605, 0x07080805,   0xff,    2,  0},
-	{4,  2140, 0, 5,     8, 0x08070605, 0x07081805,   0xff,    2,  0},
-	{2,  1350, 0, 5,     7, 0x0809090b, 0x0c0c0d09,   0xff,    2,  0},
-	{2,  1666, 0, 5,     8, 0x080a0a0c, 0x0c0d0e0a,   0xff,    2,  0},
-	{2,  2140, 0, 5,     8, 0x090a0b0c, 0x0e0f100b,   0xff,    2,  0},
-	{1,  1350, 0, 5,     8, 0x0809090b, 0x0c0c0d0a,   0xff,    2,  0},
-	{1,  1700, 0, 5,     8, 0x080a0a0c, 0x0c0d0e0a,   0xff,    2,  0},
-	{1,  1900, 0, 4,     8, 0x080a0a0c, 0x0e0e0f0a,   0xff,    2,  0},
-	{1,  2140, 0, 4,     8, 0x090a0b0c, 0x0e0f100b,   0xff,    2,  0},
-	{}
-};
-
-/*
- * The three slots have slightly different timing. See comments above.
- */
-static const struct board_specific_parameters *rdimms[] = {
-	rdimm0,
-};
-
 void fsl_ddr_board_options(memctl_options_t *popts,
 				dimm_params_t *pdimm,
 				unsigned int ctrl_num)